KR100920379B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of improving image quality, the first thin film transistor being turned on according to a first gate signal from an i (i is a natural number) gate line, and the i th gate line; The second thin film transistor and the second thin film transistor are turned on when the second gate signal having a wider pulse width than the first gate signal is supplied and the first gate signal is supplied to an i + 1 th gate line. A first liquid crystal cell comprising a first liquid crystal capacitor that charges a first video signal from a data line when on, and a first storage capacitor connected to the first liquid crystal capacitor; And a third thin film transistor turned on according to the second gate signal supplied to the i-th gate line, and a second liquid crystal charging a second video signal from the data line when the third thin film transistor is turned on. And a second liquid crystal cell including a capacitor and a second storage capacitor connected to the second liquid crystal capacitor. The first liquid crystal cell and the second liquid crystal cell are alternately positioned on a column line basis, and the sum of capacitances of the capacitors existing in the first liquid crystal cell is the same as the sum of the capacitances of the capacitors existing in the second liquid crystal cell.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}             

1 is a view schematically showing a conventional liquid crystal display device.

2 is a schematic view of a liquid crystal display according to another exemplary embodiment of the prior art.

FIG. 3 is a waveform diagram illustrating driving waveforms supplied to the liquid crystal display shown in FIG. 2.

4 is a view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 5 is a diagram showing the structure of the thin film transistor shown in FIG.

6A and 6B show the structure of the storage capacitor shown in FIG.

<Description of Symbols for Main Parts of Drawings>

2,8 LCD panel 4,10 Data driver

6,12: gate driver 20,22: liquid crystal cell

30: gate electrode 32: gate insulating layer

34 active layer 36 ohmic contact layer                 

38: drain electrode 40: source electrode

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel having a pixel matrix and a driving circuit for driving the liquid crystal panel. The driving circuit drives the pixel matrix so that the image information is displayed on the display panel.

1 is a view showing a conventional liquid crystal display device.

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2, a data driver 4 for driving data lines DL1 to DLm of the liquid crystal panel 2, and a liquid crystal panel 2. A gate driver 6 for driving the gate lines GL0 to GLn is provided.

The liquid crystal panel 2 is a thin film transistor TFT formed at the intersection of the gate lines GL0 to GLn and the data lines DL1 to DLm, and a liquid crystal connected to the thin film transistor TFT and arranged in a matrix form. With cells.

The gate driver 6 sequentially supplies gate signals to the gate lines GL0 to GLn according to a control signal from a timing controller (not shown). The data driver 4 converts the data R, G, and B supplied from the timing controller into a video signal, which is an analog signal, so that one horizontal line is provided for each horizontal period in which the gate signal is supplied to the gate lines GL0 to GLn. Minute video signal is supplied to the data lines DL1 to DLm.

The thin film transistor TFT supplies data from the data lines DL1 to DLm to the liquid crystal cell in response to gate signals from the gate lines GL0 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween, and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor (not shown) connected to the previous gate line to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

Since the liquid crystal cells of the conventional liquid crystal display are positioned at the intersections of the gate lines GL0 to GLn and the data lines DL1 to DLm, the number of data lines DL1 to DLm is equal to (m). G) form a vertical line. In other words, the liquid crystal cells are arranged in a matrix to form m vertical lines and n horizontal lines.

As can be seen here, m data lines DL1 to DLm are conventionally required to drive m vertical liquid crystal cells. Therefore, in the related art, a plurality of data lines DL1 to DLm are formed to drive the liquid crystal panel 2, and thus, a process time and a manufacturing cost are wasted. In order to overcome such disadvantages, a liquid crystal display as shown in FIG. 2 has been proposed.

Referring to FIG. 2, a liquid crystal display according to another exemplary embodiment includes a liquid crystal panel 8, a data driver 10 for driving data lines DL1 to DLm / 2 of the liquid crystal panel 8, and a liquid crystal panel 8. And a gate driver 12 for driving the gate lines GL0 to GLn of the liquid crystal panel 8.

The liquid crystal panel 8 includes the first liquid crystal cell 9 and the second liquid crystal cell 11 formed at the intersection of the gate lines GL0 to GLn and the data lines DL1 to DLm / 2. The first liquid crystal cell 9 is formed on the left side of the data line DL. The second liquid crystal cell 11 is formed on the right side of the data line DL. That is, the first liquid crystal cell 9 and the second liquid crystal cell 11 are formed at left and right sides with one data line DL interposed therebetween, and supply a video signal from adjacent data lines DL. Receive. In other words, the first liquid crystal cell 9 and the second liquid crystal cell 11 which are vertically adjacent to each other are supplied with a video signal from one data line DL, and thus liquid crystals according to another conventional embodiment. In the display device, the number of data lines DL is reduced by half compared to the liquid crystal display device shown in FIG. 1.

On the other hand, the first liquid crystal cell 9 includes first and second thin film transistors TFT1 and TFT2. The gate terminal of the first thin film transistor TFT1 is connected to the i (i is an integer) th gate line GLi, and the drain terminal is connected to the i + 1 th gate line GLi + 1. The gate terminal of the second thin film transistor TFT2 is connected to the source terminal of the first thin film transistor TFT1 and the drain terminal is connected to the adjacent data line DL, and the source terminal is the liquid crystal capacitor Clc (that is, Pixel electrode). Here, the liquid crystal capacitor Clc is represented by equally representing the common electrode facing the liquid crystal and the pixel electrode connected to the second thin film transistor TFT2.                         

The second liquid crystal cell 11 includes a third thin film transistor TFT3. The gate terminal of the third thin film transistor TFT3 is connected to the i-th gate line GLi, the drain terminal is connected to an adjacent data line DL, and the source terminal is a liquid crystal capacitor Clc (ie, a pixel electrode). Is connected to.

The gate driver 12 sequentially supplies the second gate signal SP2 and the first gate signal SP1 to the gate lines GL0 to GLn according to a control signal from a timing controller (not shown). Here, the second gate signal SP2 has a wider width than the first gate signal SP1. The data driver 10 converts the data R, G, and B supplied from the timing controller into a video signal, which is an analog signal, and supplies them to the data lines DL1 through DLm / 2.

The driving process of the liquid crystal display according to another exemplary embodiment will be described in detail with reference to FIG. 3. FIG. 3 is a diagram illustrating a process of driving the i-th gate line GLi and the i + 1 th gate line GLi + 1.

Referring to FIG. 3, the gate driver 12 supplies the first gate signal SP1 to the i + 1 th gate line GLi + 1 and the second gate signal SP2 to the i th gate line GLi. ). Here, since the width of the second gate signal SP2 is set to be wider than the width of the first gate signal SP1, the first gate signal SP1 and the second gate signal SP2 simultaneously operate during the first period TA. Only the second gate signal SP2 is applied during the second period TB subsequent to the first period TA.

During a first period TA in which the first gate signal SP1 is applied to the i + 1 th gate line GLi + 1 and the second gate signal SP2 is applied to the i th gate line GLi. The first video signal DA is supplied to the first liquid crystal cell 9 connected to the i-th gate line GLi. In detail, the first gate signal SP1 supplied to the i + 1 th gate line GLi + 1 is the first thin film transistor formed on the first liquid crystal cell 9 of the i th gate line GLi. It is supplied to the drain terminal of (TFT1). In this case, since the first thin film transistor TFT1 is turned on by the second gate signal SP2 supplied to the i-th gate line GLi, the first thin film transistor TFT1 is supplied to the drain terminal of the first thin film transistor TFT1. The gate signal SP1 is supplied to the gate terminal of the second thin film transistor TFT2 to turn on the second thin film transistor TFT2. When the second thin film transistor TFT2 is turned on, the first video signal DA supplied to the data line DL is supplied to the liquid crystal capacitor Clc of the first liquid crystal cell 9. That is, the first period TA in which the first gate signal SP1 is applied to the i + 1 th gate line GLi + 1 and the second gate signal SP2 is applied to the i th gate line GLi. The first video signal DA is supplied to the first liquid crystal cells 9 formed in the i-th gate line GLi.

Subsequently, in the second period TB, the third thin film transistor TFT3 connected to the i-th gate line GLi is turned on. When the third thin film transistor TFT3 is turned on, the second video signal DB supplied to the data line DL is supplied to the second liquid crystal cell 11 during the second period TB.

That is, according to the liquid crystal display according to another exemplary embodiment of the present invention, the first liquid crystal cell 9 and the second liquid crystal cell 11 positioned to the left and right adjacent to each other may be driven using one data line DL. have.                         

However, the liquid crystal display according to another exemplary embodiment of the related art generates a vertical dim due to a difference in driving conditions between the first liquid crystal cell 9 and the second liquid crystal cell 11. In detail, the first liquid crystal cell 9 includes two thin film transistors TFT1 and TFT2, and the second liquid crystal cell 11 includes one thin film transistor TFT3. As described above, when the number of thin film transistors included between the first liquid crystal cell 9 and the second liquid crystal cell 11 is different, the capacitance value formed in the first liquid crystal cell 9 and the second liquid crystal cell 11 are different. The capacitance value formed is different. As described above, a difference in driving conditions occurs due to different capacitances between the first liquid crystal cell 9 and the second liquid crystal cell 11, and thus a vertical dim phenomenon occurs in the liquid crystal panel 8.

Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of improving image quality.

In order to achieve the above object, the liquid crystal display of the present invention includes a first thin film transistor turned on according to a first gate signal from an i (i is a natural number) gate line, and the first gate on the i th gate line. The second thin film transistor is turned on when the second gate signal having a wider pulse width than the signal is supplied and the first gate signal is supplied to the i + 1 th gate line, and the data is turned on when the second thin film transistor is turned on. A first liquid crystal cell comprising a first liquid crystal capacitor charging a first video signal from a line, and a first storage capacitor connected to the first liquid crystal capacitor; And a third thin film transistor turned on according to the second gate signal supplied to the i-th gate line, and a second liquid crystal charging a second video signal from the data line when the third thin film transistor is turned on. And a second liquid crystal cell including a capacitor and a second storage capacitor connected to the second liquid crystal capacitor.
The first liquid crystal cell and the second liquid crystal cell are alternately positioned on a column line basis, and the sum of capacitances of the capacitors existing in the first liquid crystal cell is the same as the sum of the capacitances of the capacitors existing in the second liquid crystal cell.
Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

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Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 6B.

4 is a view showing a liquid crystal display device according to an embodiment of the present invention. The liquid crystal display according to the embodiment of the present invention is supplied with the same structure and the same driving waveform as the conventional liquid crystal display shown in FIG. However, the liquid crystal display according to the exemplary embodiment of the present invention shown in FIG. 4 further illustrates storage capacitors Cst1 and Cst2 that are equivalently formed in the liquid crystal cells 20 and 22.

The liquid crystal display of FIG. 4 includes a first liquid crystal cell 20 and a second liquid crystal cell 22, and the first liquid crystal cell 20 and the second liquid crystal cell 22 are alternately formed for each column line. do. In addition, the first liquid crystal cell 20 and the second liquid crystal cell 22 which are formed adjacent to each other with one data line DL are driven by one data line DLi.

Meanwhile, the first liquid crystal cell 20 includes first and second thin film transistors TFT1 and TFT2. The gate terminal of the first thin film transistor TFT1 is connected to the i (i is an integer) th gate line GLi, and the drain terminal is connected to the i + 1 th gate line GLi + 1. The gate terminal of the second thin film transistor TFT2 is connected to the source terminal of the first thin film transistor TFT1, the drain terminal is connected to the adjacent data line DL, and the source terminal is the liquid crystal capacitor Clc1 (that is, Pixel electrode) and a storage capacitor Cst1. Here, the liquid crystal capacitor Clc1 is equivalently represented as a common electrode facing the liquid crystal with the liquid crystal interposed therebetween, and a pixel electrode connected to the second thin film transistor TFT2.

The second liquid crystal cell 11 includes a third thin film transistor TFT3. The gate terminal of the third thin film transistor TFT3 is connected to the i-th gate line GLi, the drain terminal is connected to an adjacent data line DL, and the source terminal is the liquid crystal capacitor Clc2 (ie, the pixel electrode). Is connected to.

In the embodiment of the present invention, the gate-source capacitor (equivalently formed between the gate electrode and the source electrode of the thin film transistors TFT1, TFT2, and TFT3 of the first liquid crystal cell 20 and the second liquid crystal cell 22) Cgs1, Cgs2, Cgs3) is determined by Equation 1.

1 / Cgs1 + 1 / Cgs2 = 1 / Cgs3 (and) Cgs1> Cgs2

However, in Equation 1, the storage capacitor Cst1 and the liquid crystal capacitor Clc1 of the first liquid crystal cell 20 have the same capacitance as the storage capacitor Cst2 and the liquid crystal capacitor Clc2 of the second liquid crystal cell 20. Have Therefore, the designer designes the storage capacitors Cst1 and Cst2 and the liquid crystal capacitors Clc1 and Clc2 of the first liquid crystal cell 20 and the second liquid crystal cell 22 to have the same capacitance, and then satisfies Equation 1. One liquid crystal cell 20 and the second liquid crystal cell 22 are formed.

As such, when the first liquid crystal cell 20 and the second liquid crystal cell 22 are formed to satisfy Equation 1, the first and second liquid crystal cells 20 and 22 have the same capacitance. The image quality (i.e., the vertical dim phenomenon can be prevented) can be improved. In other words, according to the present invention, the first liquid crystal cell 20 and the second liquid crystal cell 22 may have the same driving conditions, thereby improving image quality. On the other hand, the gate-source capacitor Cgs1 of the first thin film transistor TFT1 is always set larger than the gate-source capacitor Cgs2 of the second thin film transistor TFT2.

In detail, the first thin film transistor TFT1 supplies the gate signal supplied to the next stage to the second thin film transistor TFT2. The second thin film transistor TFT2 supplies a video signal supplied to the data line DL to the liquid crystal capacitor Clc and the storage capacitor Cst1 when the gate signal is supplied through the first thin film transistor TFT1. At this time, the absolute value of the voltage value of the gate signal is set higher than the absolute value of the voltage value of the video signal supplied to the data line (that is, since a high current is supplied to the first thin film transistor TFT1). The gate-source capacitor Cgs1 of is set to be larger than the gate-source capacitor Cgs2 of the second thin film transistor Cgs2.

Meanwhile, the length of the gate electrode 30 shown in FIG. 5 may be adjusted so that the first thin film transistor TFT1 supplies a higher current than the second thin film transistor TFT2. Referring to FIG. 5, the thin film transistors TFT1, TFT2, and TFT3 generally include the gate electrode 30, the gate insulating layer 32 and the gate insulating layer 32 formed on the gate electrode 30. ) And an ohmic contact layer 36 formed at portions except the central portion of the active layer 34 and drain and source electrodes 38 and 40 formed on the ohmic contact layer 36. It is provided. In this case, the length of the gate electrode 30 of the first thin film transistor TFT1 is smaller than the length of the gate electrode 30 of the second thin film transistor TFT2. As such, when the length of the gate electrode 30 of the first thin film transistor TFT1 is formed to be small, a lot of light may be supplied from a back light (not shown) to flow a current higher than that of the first thin film transistor TFT2.

Meanwhile, in the present invention, in order to set the driving conditions of the first liquid crystal cell 20 and the second liquid crystal cell 22 to be the same, Equation 2 shows that the first liquid crystal cell 20 and the second liquid crystal cell 22 Capacitance values can be set identically.

Cgs1 + Cgs2 + Cst1 + Clc1 = Cgs3 + Cst2 + Clc2

(and) 1 / Cgs1 + 1 / Cgs2 = 1 / Cgs3 (and) Cgs1> Cgs2

In Equation 2, the sum of the capacitances of the first liquid crystal cell 20 is set equal to the sum of the capacitances of the second liquid crystal cell 22. Equation 2 is a value of the storage capacitor Cst1 and the liquid crystal capacitor Clc1 of the first liquid crystal cell 20 and the storage capacitor Cst2 and the liquid crystal of the second liquid crystal cell 22 under the condition of Equation 1. The value of the capacitor Clc2 is set differently. In fact, since the first liquid crystal cell 20 includes two thin film transistors TFT1 and TFT2, and the second liquid crystal cell 22 includes one thin film transistor TFT3, the first liquid crystal cell 20 is included in the first liquid crystal cell 20. The size of the pixel electrode included is set larger than the size of the pixel electrode included in the second liquid crystal cell 22. Therefore, the capacitance of the liquid crystal capacitor Clc2 included in the second liquid crystal cell 22 is set larger than the capacitance value of the liquid crystal capacitor Clc1 included in the first liquid crystal cell 20.

Therefore, in order to satisfy the condition of Equation 2, the capacitance of the storage capacitor Cst1 included in the first liquid crystal cell 20 is the capacitance of the storage capacitor Cst2 included in the second liquid crystal cell 22. It is set larger than the value of. In other words, the first and second liquid crystal cells satisfying Equation 2 by setting the value of the capacitance of the storage capacitor Cst1 included in the first liquid crystal cell 20 as large as the capacitance difference of the liquid crystal capacitor Clc. To form (20,22).

When the first and second liquid crystal cells 20 and 22 are formed to satisfy Equation 2, the first and second liquid crystal cells are driven under the same driving conditions, thereby improving image quality. Meanwhile, in order to adjust the capacitance values of the storage capacitors Cst1 and Cst2, the capacitance values may be adjusted by changing the structures of the storage capacitors Cst1 and Cst2 as shown in FIGS. 6A and 6B. In detail, first, the storage capacitor Cst1 included in the first liquid crystal cell 20 includes the gate electrode 30 and the gate insulating layer 32 formed on the gate electrode 30 as shown in FIG. 6A. ) And drain / source electrodes 38 and 40 formed on the gate insulating layer 32. On the other hand, the storage capacitor Cst2 included in the second liquid crystal cell 22 has the gate electrode 30, the gate insulating layer 32 and the gate insulating layer formed on the gate electrode 30 as shown in FIG. 6B. An active layer 34 partially formed on the 32, an ohmic contact layer 36 formed on the active layer 34, and drain / source electrodes 38 and 40 formed on the ohmic contact layer 36. do. As described above, when the structures of the storage capacitors Cst1 and Cst2 included in the first and second liquid crystal cells 20 and 22 are different, the capacitance values are also different. In fact, when the storage capacitors Cst1 and Cst2 have the structures of FIGS. 6A and 6B, the value of the storage capacitor Cst1 included in the first liquid crystal cell 20 is set to be large, thereby satisfying Equation 2 below. The first and second liquid crystal cells 20 and 22 may be formed.

As described above, according to the liquid crystal display device according to the present invention, the image quality can be improved by setting the capacitance values of the first liquid crystal cell and the second liquid crystal cell which are formed in different shapes to be the same.

 Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

a first thin film transistor turned on according to a first gate signal from an i (i is a natural number) gate line, and a second gate signal having a wider pulse width than the first gate signal is supplied to the i th gate line, and i The second thin film transistor turned on when the first gate signal is supplied to a + 1th gate line, and a first liquid crystal capacitor charging a first video signal from a data line when the second thin film transistor is turned on A first liquid crystal cell including a first storage capacitor connected to the first liquid crystal capacitor; And A third thin film transistor turned on according to the second gate signal supplied to the i-th gate line, and a second liquid crystal capacitor charging a second video signal from the data line when the third thin film transistor is turned on And a second liquid crystal cell comprising a second storage capacitor connected to the second liquid crystal capacitor, The first liquid crystal cell and the second liquid crystal cell are alternately positioned in column line units, And the sum of capacitances of the capacitors present in the first liquid crystal cell is the same as the sum of capacitances of the capacitors existing in the second liquid crystal cell. The method of claim 1, The capacitance of the gate-source capacitor formed in the first thin film transistor is 'Cgs1', the capacitance of the gate-source capacitor formed in the second thin film transistor is 'Cgs2', and the capacitance of the gate-source capacitor formed in the third thin film transistor. In the case of 'Cgs3', 1 / Cgs1 + 1 / Cgs2 = 1 / Cgs3 characterized in that the liquid crystal display device. The method of claim 1, The capacitance of the gate-source capacitor formed in the first thin film transistor is 'Cgs1', the capacitance of the gate-source capacitor formed in the second thin film transistor is 'Cgs2', and the capacitance of the first storage capacitor is 'Cst1', The capacitance of one liquid crystal capacitor is 'Clc1', the capacitance of the gate-source capacitor formed in the third thin film transistor is 'Cgs3', the capacitance of the second storage capacitor is 'Cst2', and the capacitance of the second liquid crystal capacitor is 'Clc2'. 'Cgs1 + Cgs2 + Cst1 + Clc1 = Cgs3 + Cst2 + Clc2, and 1 / Cgs1 + 1 / Cgs2 = 1 / Cgs3. The method of claim 2 or 3, The first thin film transistor, A gate electrode connected to the i-th gate line; A drain electrode connected to the i + 1th gate line; And A source electrode connected to the gate electrode of the second thin film transistor, The second thin film transistor, A gate electrode connected to the source electrode of the first thin film transistor; A drain electrode connected to the data line; And And a source electrode connected to the pixel electrode of the first liquid crystal capacitor. The method of claim 2 or 3, When the capacitance of the gate-source capacitor formed in the first thin film transistor is referred to as 'Cgs1', and the capacitance of the gate-source capacitor formed in the second thin film transistor is referred to as 'Cgs2', Cgs1> Cgs2 is satisfied. LCD display device. The method of claim 2 or 3, The length of the gate electrode of the first thin film transistor is shorter than the length of the gate electrode of the second thin film transistor. The method according to claim 2 or 3, And the capacitance of the second liquid crystal capacitor is greater than the capacitance of the first liquid crystal capacitor. The method of claim 2 or 3, And the capacitance of the first storage capacitor is greater than the capacitance of the second storage capacitor. The method of claim 8, The first storage capacitor, Electrodes and a gate insulating layer formed between the electrodes, The second storage capacitor, And electrodes, and the gate insulating layer, the active layer, and the ohmic contact layer formed between the electrodes. The method of claim 4, wherein The third thin film transistor, A gate electrode connected to the i-th gate line; A drain electrode connected to the data line; And And a source electrode connected to the pixel electrode of the second liquid crystal capacitor.

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