KR100920037B1 - Method for forming trench of semiconductor device - Google Patents

Method for forming trench of semiconductor device Download PDF

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KR100920037B1
KR100920037B1 KR1020020079999A KR20020079999A KR100920037B1 KR 100920037 B1 KR100920037 B1 KR 100920037B1 KR 1020020079999 A KR1020020079999 A KR 1020020079999A KR 20020079999 A KR20020079999 A KR 20020079999A KR 100920037 B1 KR100920037 B1 KR 100920037B1
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trench
pad nitride
pad
etching
nitride layer
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KR20040053445A (en
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류상욱
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

본 발명은 반도체소자의 트렌치 형성방법에 관한 것으로, 반도체기판상에 패드산화막과 패드질화막을 차례로 형성한 후 상기 패드질화막과 상기 패드산화막 일부를 선택적으로 식각하는 단계; 상기 식각된 패드질화막을 마스크로 하여 상기 반도체기판을 식각하여 트렌치를 형성하는 단계; 상기 패드질화막을 리세스한 후 상기 패드질화막을 마스크로 하여 상기 패드산화막을 리세스하여 상기 트렌치의 상부모서리의 라운딩할 부분을 노출시키는 단계; 및 상기 트렌치의 상부모서리를 라운딩하는 단계를 포함하여 구성된다.
The present invention relates to a method of forming a trench in a semiconductor device, the method comprising: selectively forming a pad oxide film and a pad nitride film on a semiconductor substrate, and then selectively etching the pad nitride film and a portion of the pad oxide film; Etching the semiconductor substrate using the etched pad nitride layer as a mask to form a trench; Recessing the pad nitride layer and recessing the pad oxide layer using the pad nitride layer as a mask to expose a portion to be rounded at the upper edge of the trench; And rounding an upper edge of the trench.

Description

반도체소자의 트렌치 형성방법{Method for forming trench of semiconductor device} Method for forming trench of semiconductor device             

도 1은 종래기술에 따른 반도체소자의 트렌치 형성방법을 도시한 공정 단면도.1 is a process cross-sectional view showing a trench forming method of a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 트렌치 형성방법을 도시한 공정별 단면도.2A to 2D are cross-sectional views illustrating processes for forming trenches in the semiconductor device according to the present invention.

(도면의 주요부분에 대한 부호설명)(Code description of main parts of drawing)

100 : 실리콘기판 120 : 패드산화막100: silicon substrate 120: pad oxide film

140 : 패드질화막 160 : 감광막140: pad nitride film 160: photosensitive film

180 : 트렌치 200 : 상부모서리180: trench 200: upper corner

200a : 상부모서리 라운딩200a: upper corner rounding

본 발명은 반도체소자의 트렌치 형성방법에 관한 것으로, 보다 상세하게는 패싯(facet)현상을 이용하여 트렌치의 상부모서리 라운딩을 실현한 반도체소자의 트렌치 형성방법에 관한 것이다. The present invention relates to a trench forming method of a semiconductor device, and more particularly to a trench forming method of a semiconductor device that realizes the upper edge rounding of the trench by using a facet phenomenon.

현재의 반도체 제조기술은 고집적화와 고성능화를 요구한다. 따라서, MOSFET의 게이트 선폭축소 기술과 더불어 소자의 격리기술이 반도체소자의 고집적화에 가장 밀접하게 연관되어 있고 이를 향상시키기 위해 각 분야에서 많은 노력을 기울이고 있다. Current semiconductor manufacturing technology requires high integration and high performance. Therefore, the isolation technology of the device, together with the gate line reduction technology of the MOSFET, is most closely related to the high integration of the semiconductor device, and many efforts have been made in each field to improve it.

이에 부응하기 위해 소자격리 기술에서는 주로 R-LOCOS(Recessed LOCal Oxidation of Silicon) 기술로 어느 정도 효과를 나타내었으나, 0.25㎛ 이하 부터는 거의 모든 소자에 트렌치 형성기술을 이용하고 있다.In order to cope with this, device isolation technology mainly exhibited some effect with Recessed LOCal Oxidation of Silicon (R-LOCOS) technology, but trench forming technology is used for almost all devices from 0.25 μm or less.

이러한 트렌치 형성기술은 트렌치 건식식각시 발생하는 폴리머를 이용한 상부모서리 라운딩방법, 트렌치 형성후 열산화막 형성 및 제거를 통한 라운딩 산화방법등이 이용되고 있다.The trench forming technique uses a top corner rounding method using a polymer generated during trench dry etching, a rounding oxidation method through thermal oxide formation and removal after trench formation, and the like.

그러나, 상기 폴리머를 이용한 라운딩방법은 폴리머 그 자체가 플라즈마 건식식각시의 식각부산물을 이용한 것이어서 패턴의 밀도에 따라 생성되는 폴리머의 정도에 차이를 발생시키게 되는데, 이는 마이크로 로딩 효과(micro-loading effect)로인해 제어하는데 어려움이 있다.However, the rounding method using the polymer is that the polymer itself is an etching by-product of plasma dry etching, which causes a difference in the degree of the polymer produced according to the density of the pattern, which is a micro-loading effect. This makes it difficult to control.

또한, 상기 라운딩 산화방법도 트렌치의 양끝단에서 소오스/드레인을 형성해야 할 액티브영역으로 침범하는 정도가 동일하기 때문에, 액티브영역이 좁은 지역은 상대적으로 라운딩이 많게 되는데 반해 액티브영역이 넓은 지역은 좁은 지역과 비교해 라운딩이 적게 되는 현상이 발생하게 되는 문제점이 있다.In addition, since the rounding oxidation method has the same degree of invasion into the active region where the source / drain should be formed at both ends of the trench, the rounded oxidation region is relatively rounded, whereas the wider active region is narrower. There is a problem that less rounding occurs than the area.

특히, 0.13㎛ 이하에서는 그 영향이 커지게 되므로 상부모서리 라운딩의 안 정적인 제어는 매우 중요한 요소가 된다.In particular, since the influence is increased at 0.13㎛ or less, the stable control of the upper corner rounding is a very important factor.

이러한 트렌치 형성기술을 이용한 소자격리는 도 1에 도시된 바와 같이, 상부모서리 라운딩(30)과 하부모서리 라운딩(35)을 제어하는 것은 다음과 같은 이유로 쉽지 않은 것이 현실이다.As shown in FIG. 1, it is difficult to control the upper corner rounding 30 and the lower corner rounding 35 as shown in FIG. 1.

즉, 도 1에 도시된 바와 같이, 패드질화막(15)을 증착한 후 트렌치용 마스크(20)를 패터닝하고, 패드질화막 건식식각 후 실리콘기판(5)을 건식식각할 때 측벽 폴리머를 다량으로 생성하는 가스(예 : HBr)를 이용하여 실리콘기판(5)의 초기 식각때 부터 패드질화막(15)의 측벽에 폴리머를 형성하면서 식각한다. That is, as illustrated in FIG. 1, after the pad nitride layer 15 is deposited, the trench mask 20 is patterned, and the sidewall polymer is generated in a large amount when the silicon substrate 5 is dry-etched after the pad nitride layer is dry etched. From the initial etching of the silicon substrate 5 using a gas (for example, HBr) to form a polymer on the sidewall of the pad nitride film 15 is etched.

이렇게 하면 어느 정도 식각이 진행된 후 측벽 폴리머의 자연적 손실등으로 인해 패드질화막 측벽의 폴리머가 손실되면서 그 아래 부분의 실리콘기판이 새로이 노출되고, 이 부분의 식각이 상대적으로 늦게 시작되면서 상부모서리 라운딩(30)을 가능케 하는 등 다양한 측벽 폴리머 제어방법을 사용한다.In this case, after the etching is performed to some extent, the loss of the polymer on the sidewall of the pad nitride film is caused by the natural loss of the sidewall polymer, and the silicon substrate at the lower part is newly exposed. Various sidewall polymer control methods are used.

그러나, 측벽폴리머 역시 플라즈마 건식식각시의 식각부산물이어서 형성되는 폴리머 모양도 식각되는 패턴의 밀도에 따라 생성되는 폴리머의 정도에 차이를 발생하는데 이를 제어하기가 어렵다는 문제점이 있다. However, the sidewall polymer also has a problem in that the shape of the polymer formed by the etching by-product during the plasma dry etching also causes a difference in the degree of the polymer produced according to the density of the pattern to be etched.

또한, 0.13㎛이하급의 고성능 반도체소자일 경우 그 영향은 매우 심각하게 되고, 액티브영역의 좁은지역과 넓은 지역의 험프특성, 소자분리산화막의 전기적 특성에 차이를 가져오게 되는 문제점이 있다.In addition, in the case of a high-performance semiconductor device of 0.13㎛ or less, the effect is very serious, there is a problem that the difference in the hump characteristics of the narrow region and the large region of the active region, the electrical characteristics of the isolation oxide film.

따라서, 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 좁은 패턴이나 넓은 패턴이나 상관없이 상부모서리 라운딩 정도를 동일하게 구현할 수 있고, 매우 안정적으로 상부모서리 라운딩을 제어할 수 있는 반도체소자의 트렌치 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, and can implement the same upper corner rounding degree regardless of the narrow pattern or wide pattern, the semiconductor which can control the upper corner rounding very stably It is an object of the present invention to provide a method for forming a trench in a device.

상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 패드산화막과 패드질화막을 차례로 형성한 후 상기 패드질화막과 상기 패드산화막 일부를 선택적으로 식각하는 단계; 상기 식각된 패드질화막을 마스크로 하여 상기 반도체기판을 식각하여 트렌치를 형성하는 단계; 상기 패드질화막을 리세스한 후 상기 패드질화막을 마스크로 하여 상기 패드산화막을 리세스하여 상기 트렌치의 상부모서리의 라운딩할 부분을 노출시키는 단계; 및 상기 트렌치의 상부모서리를 라운딩하는 단계를 포함하여 구성됨을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a pad oxide film and a pad nitride film on a semiconductor substrate, and then selectively etching the pad nitride film and a portion of the pad oxide film; Etching the semiconductor substrate using the etched pad nitride layer as a mask to form a trench; Recessing the pad nitride layer and recessing the pad oxide layer using the pad nitride layer as a mask to expose a portion to be rounded at the upper edge of the trench; And rounding the upper edge of the trench.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 트렌치 형성방법을 도시한 공정별 단면도이다.2A through 2D are cross-sectional views illustrating processes for forming trenches in the semiconductor device according to the present invention.

먼저, 도 2a에 도시된 바와 같이, 실리콘기판(100)상에 패드산화막(120)을 20∼300Å 두께로 증착하고, 상기 패드산화막(120)의 상부에 패드질화막(140)을 500∼3000Å 두께로 증착한 후 트렌치 감광막(160)을 도포한다. 상기 패드질화막 대신에 SiON계열의 질산화막을 이용할 수도 있다. First, as shown in FIG. 2A, a pad oxide film 120 is deposited on the silicon substrate 100 to a thickness of 20 to 300 GPa, and the pad nitride film 140 is 500 to 3000 GPa thick on the pad oxide film 120. After deposition, the trench photoresist 160 is coated. Instead of the pad nitride film, a silicon nitride film of SiON series may be used.                     

그 다음, 트렌치 감광막(160)을 패터닝하여 상기 패드질화막(140)과 상기 패드산화막(120)을 건식식각한다.Next, the trench photoresist 160 is patterned to dry etch the pad nitride layer 140 and the pad oxide layer 120.

이어서, 도 2b에 도시된 바와 같이, 상기 결과물의 상부에 CF계열의 가스와 Cl2, HBr등의 가스를 이용한 건식식각으로 트렌치(180)를 형성한 후 감광막(160)을 제거한다.Subsequently, as shown in FIG. 2B, the trench 180 is formed by dry etching using a CF-based gas and a gas such as Cl 2, HBr, and the like, and then the photoresist layer 160 is removed.

여기서, 상기 패드질화막(140)의 건식식각 후, 상기 감광막(160)을 제거한 다음 트렌치 건식식각시 상기 패드질화막(140)을 하드마스크로서 이용한 건식식각으로 트렌치(180)를 형성할 수도 있다.After the dry etching of the pad nitride layer 140, the photoresist layer 160 may be removed, and then the trench 180 may be formed by dry etching using the pad nitride layer 140 as a hard mask during the trench dry etching.

그 다음, 도 2c에 도시된 바와 같이, 인산(H3PO4)등의 습식식각 용액으로 상기 패드질화막(140)을 20∼500Å정도 리세스하여 리세스패드질화막(140a)을 형성한 후, HF, NH4F등의 용액으로 패드산화막(120)을 20∼500Å정도 리세스하여 리세스산화막(120a)을 형성한다. 이로써, 상기 트렌치(180)의 상부모서리 라운딩(TCR : Top Corner Rounding)할 부분(200)을 노출시킨다.Next, as shown in FIG. 2C, the pad nitride film 140 is recessed by about 20 to 500 kPa with a wet etching solution such as phosphoric acid (H 3 PO 4) to form a recess pad nitride film 140a, and then HF and NH 4 F. The recessed oxide film 120a is formed by recessing the pad oxide film 120 at about 20 to 500 kPa with a solution such as the like. As a result, the portion 200 to be top corner rounded (TCR) of the trench 180 is exposed.

이때, 상기 패드질화막(140)을 습식식각하지 않고, CF계열을 중심으로 Cl2, O2, Ar 중 적어도 하나 이상이 첨가된 가스를 사용하여 패드질화막(140)을 리세스할 수도 있다.In this case, the pad nitride layer 140 may be recessed using a gas to which at least one of Cl 2, O 2, and Ar is added, based on the CF series, without wet etching the pad nitride layer 140.

또한, 상기 패드질화막(140)의 습식식각시 인산에 대한 식각속도를 이용하여 후속공정인 HF등의 식각제를 이용한 패드산화막의 리세스 단계를 생략할 수도 있다.In addition, the step of recessing the pad oxide layer using an etchant such as HF may be omitted by using an etching rate with respect to phosphoric acid during wet etching of the pad nitride layer 140.

이어서, 도 2d에 도시된 바와 같이, 상기 트렌치(180)의 상부모서리(200)를 블랭킷으로 플라즈마 건식식각하여 플라즈마 건식식각시 나타나는 고유현상인 패싯(facet)현상을 이용하여 트렌치(180)의 상부모서리(200)를 라운딩하여 상부모서리 라운딩부분(200a)을 형성한다.Subsequently, as shown in FIG. 2D, the upper edge 200 of the trench 180 is plasma-etched with a blanket to form an upper portion of the trench 180 using facet, which is an inherent phenomenon in plasma dry etching. Rounding the edge 200 forms an upper corner rounding portion 200a.

상술한 바와 같은 상부모서리 라운딩을 1차적으로 수행한 후, 2차적으로 트렌치 건식식각 완료 이후의 단계에서 추가로 열산화공정(Rounding Oxidation)을 수행하여 상부모서리 라운딩을 최종적으로 완성할 수도 있다.After the upper corner rounding as described above is primarily performed, the upper corner rounding may be finally completed by additionally performing a thermal oxidation process in a step after the completion of the trench dry etching.

또한, 상기 상부모서리부분(200)의 습식식각 속도가 빠른 점을 이용하여 인산, 초산등 실리콘의 습식식각제로 상기 상부모서리 부분(200)을 10∼500Å정도 라운딩할 수 있다.In addition, by using a wet etching speed of the upper edge portion 200 is fast, the upper edge portion 200 may be rounded about 10 to 500 kPa with a wet etchant of silicon, such as phosphoric acid and acetic acid.

상술한 바와 같이, 본 발명은 좁은 패턴이나 넓은 패턴이나 상관없이 상부모서리 라운딩 정도를 동일하게 구현할 수 있고, 매우 안정적으로 상부모서리 라운딩을 제어할 수 있다는 효과가 있다.As described above, the present invention can implement the upper corner rounding degree equally regardless of the narrow pattern or the wide pattern, and there is an effect that the upper corner rounding can be controlled very stably.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (11)

반도체기판상에 패드산화막과 패드질화막을 차례로 형성한 후 상기 패드질화막과 상기 패드산화막 일부를 선택적으로 식각하는 단계;Selectively forming a pad oxide film and a pad nitride film on a semiconductor substrate, and then selectively etching the pad nitride film and a portion of the pad oxide film; 상기 식각된 패드질화막을 마스크로 하여 상기 반도체기판을 식각하여 트렌치를 형성하는 단계; Etching the semiconductor substrate using the etched pad nitride layer as a mask to form a trench; 상기 패드 질화막을 습식 또는 건식 식각으로 리세스한 후 상기 패드 질화막을 마스크로 하여 상기 패드 산화막을 습식 식각으로 리세스하여 상기 트렌치의 상부 모서리를 노출시키는 단계;Recessing the pad nitride layer by wet or dry etching and then recessing the pad oxide layer by wet etching using the pad nitride layer as a mask to expose an upper edge of the trench; 인산 또는 초산을 사용한 습식 식각 공정으로 상기 트렌치 상부 모서리를 1차 라운딩시키는 단계;및First rounding the upper edge of the trench by a wet etching process using phosphoric or acetic acid; and 열산화공정(Rounding Oxidation)을 수행하여 상기 트렌치 상부 모서리를 2차 라운딩시키는 단계;Second rounding the upper edge of the trench by performing a thermal oxidation process; 를 포함하여 구성된 반도체소자의 트렌치 형성방법.Trench formation method of a semiconductor device comprising a. 삭제delete 삭제delete 삭제delete 제 1 항에 있어서, 상기 패드질화막은 건식식각시 CF계열을 중심으로 Cl2, O2, Ar 중 적어도 어느 하나 이상이 첨가된 가스를 사용하여 리세스하는 것을 특징으로 하는 반도체소자의 트렌치 형성방법.The method of claim 1, wherein the pad nitride layer is recessed using a gas to which at least one of Cl 2 , O 2 , and Ar is added based on the CF series during dry etching. . 제 1 항에 있어서, 상기 패드질화막의 습식식각시 습식식각제에 대한 식각속도를 이용하여 상기 패드산화막의 리세스 단계를 생략하는 것을 특징으로 하는 반도체소자의 트렌치 형성방법.The method of claim 1, wherein the recess of the pad oxide layer is omitted by using an etching rate with respect to a wet etchant during wet etching of the pad nitride layer. 제 1 항에 있어서, 상기 패드질화막을 20∼500Å의 두께로 리세스하는 것을 특징으로 하는 반도체소자의 트렌치 형성방법.The method of forming a trench in a semiconductor device according to claim 1, wherein said pad nitride film is recessed to a thickness of 20 to 500 kPa. 제 1 항에 있어서, 상기 패드산화막을 20∼500Å의 두께로 리세스하는 것을 특징으로 하는 반도체소자의 트렌치 형성방법.The method of forming a trench in a semiconductor device according to claim 1, wherein said pad oxide film is recessed to a thickness of 20 to 500 kPa. 삭제delete 삭제delete 제 1 항에 있어서, 상기 상부모서리 부분은 10∼500Å두께로 습식식각하는 것을 특징으로 하는 반도체소자의 트렌치 형성방법.The method of claim 1, wherein the upper edge portion is wet-etched to a thickness of 10 to 500 kPa.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000061225A (en) * 1999-03-24 2000-10-16 김영환 Method for fabricating trench of semiconductor device
JP2000323565A (en) * 1999-05-13 2000-11-24 Mitsubishi Electric Corp Manufacture of semiconductor device and semiconductor device
KR20010046153A (en) * 1999-11-10 2001-06-05 박종섭 Method of manufacturing trench type isolation layer in semiconductor device
KR20010068644A (en) * 2000-01-07 2001-07-23 박종섭 Method for isolating semiconductor devices
KR20010109638A (en) * 2000-05-31 2001-12-12 박종섭 Method for forming isolation layer in semiconductor device
KR20020045271A (en) * 2000-12-08 2002-06-19 박종섭 Method of forming a isolation layer in a semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000061225A (en) * 1999-03-24 2000-10-16 김영환 Method for fabricating trench of semiconductor device
JP2000323565A (en) * 1999-05-13 2000-11-24 Mitsubishi Electric Corp Manufacture of semiconductor device and semiconductor device
KR20010046153A (en) * 1999-11-10 2001-06-05 박종섭 Method of manufacturing trench type isolation layer in semiconductor device
KR20010068644A (en) * 2000-01-07 2001-07-23 박종섭 Method for isolating semiconductor devices
KR20010109638A (en) * 2000-05-31 2001-12-12 박종섭 Method for forming isolation layer in semiconductor device
KR20020045271A (en) * 2000-12-08 2002-06-19 박종섭 Method of forming a isolation layer in a semiconductor device

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