KR100916135B1 - Stacked ptc thermistor composition and its manufacturing method - Google Patents

Stacked ptc thermistor composition and its manufacturing method Download PDF

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KR100916135B1
KR100916135B1 KR1020070094878A KR20070094878A KR100916135B1 KR 100916135 B1 KR100916135 B1 KR 100916135B1 KR 1020070094878 A KR1020070094878 A KR 1020070094878A KR 20070094878 A KR20070094878 A KR 20070094878A KR 100916135 B1 KR100916135 B1 KR 100916135B1
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ptc thermistor
nitrogen
ceramic layer
laminated
atmosphere
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KR20090029550A (en
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전명표
김병익
명성재
안평래
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한국세라믹기술원
이건테크놀로지 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/008Thermistors
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    • C04B35/00Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/01Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
    • C04B35/46Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/02Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having positive temperature coefficient

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Abstract

본 발명은 환원분위기중에서 소성된 PTC 서미스터의 실온저항을 낮추고, 비저항변화율을 향상시키는 내환원성 분말과 그 제조방법 및 내부전극과 반도체 세라믹층을 교대로 적층하고 동시소성하여 얻어지는 적층형 PTC 시미스터에 있어서, 적층형 PTC 서미스터의 낮은 실온저항과 높은 비저항변화율을 갖는 적층형 PTC 서미스터를 제공한다. The present invention relates to a reduced temperature resistant powder of a PTC thermistor fired in a reducing atmosphere, a method for producing a reduced resistance powder, a method of manufacturing the same, and a laminated PTC thermistor obtained by alternately laminating and co-firing an internal electrode and a semiconductor ceramic layer. The present invention provides a laminated PTC thermistor having low room temperature resistance and high resistivity change rate of the laminated PTC thermistor.

본 발명에서 제공하는 내환원성의 분말제조방법으로는 하소공정시 혼합분말 주변의 가스분위기를 공기, 산소/질소=20/80, 질소, 수소/질소=5/95, 수소/질소=10/90으로 형성하여 각기 다른 비화학양론적 조성물을 형성한다. 또한 상기의 조성물을 반도체 세라믹층이 되도록 세라믹 그린시트를 제조, 각각의 세라믹 그린시트를 조합하여 내부전극과 교대로 적층하여 얻어지는 적층형 PTC 서미스터를 제조함으로써 종래기술로 제조된 적층형 PTC 서미스터의 PTC특성을 향상시킨다. Reduction-resistant powder production method provided by the present invention includes a gas atmosphere around the mixed powder during the calcination process, air, oxygen / nitrogen = 20/80, nitrogen, hydrogen / nitrogen = 5/95, hydrogen / nitrogen = 10/90 To form different nonstoichiometric compositions. In addition, the PTC characteristics of the laminated PTC thermistor manufactured according to the prior art can be obtained by manufacturing a ceramic green sheet in which the composition is a semiconductor ceramic layer, and manufacturing a laminated PTC thermistor obtained by alternately laminating the internal electrodes by combining the respective ceramic green sheets. Improve.

적층형 PTC 서미스터, 반도체 세라믹층, 내부전극, 하소분위기 Multilayer PTC Thermistor, Semiconductor Ceramic Layer, Internal Electrode, Calcining Atmosphere

Description

적층형 정특성 서미스터 조성물 및 제조방법{STACKED PTC THERMISTOR COMPOSITION AND ITS MANUFACTURING METHOD}Stacked static thermistor composition and manufacturing method {STACKED PTC THERMISTOR COMPOSITION AND ITS MANUFACTURING METHOD}

본 발명은 과전류 보호, 온도제어 등에 사용되는 적층형 반도체 세라믹소자용 조성물과 그것으로 구성된 적층형 PTC 서미스터 소자로서, 특히, 낮은 실온저항을 갖으며 정온도계수의 저항-온도특성을 갖는 내환원성 조성물과 그 제조방법 및 적층형 PTC 서미스터에 관한 것이다. The present invention relates to a multilayer semiconductor ceramic device composition used for overcurrent protection, temperature control, and the like, and a multilayer PTC thermistor device comprising the same, in particular, a reduction resistance composition having a low temperature resistance and a resistance-temperature characteristic of a constant temperature coefficient and A manufacturing method and a laminated PTC thermistor are related.

최근 전자기기의 소형화, 경량화 및 고기능화가 한층 요구됨에 따라 세라믹 부품에 있어서의 적층화의 필요성 및 개발이 점차 확대되어 가고 있다. 기존의 단판형 세라믹 PTC의 경우, 세라믹 고유의 실온비저항으로 10Ω㎝이하로의 제조가 어렵다고 알려졌으나, 최근 그 이하의 실온비저항을 갖는 조성개발이 보고되고 있다. 하지만, 실온에서 저저항을 갖기 위해서는 소체의 단면적이 넓어지고, 세라믹 소체의 두께가 극히 얇아져야 하므로, 부품의 소형화를 기대하기 어렵다. 따라서, 실온저항을 낮추기 위해서는 도1에서와 같이 내부전극(3)과 반도체 세라믹층(2)을 교대 로 적층한 후 양 단면에 외부전극을 형성함으로써 반도체 세라믹층의 박층화와 전 극면의 대면적화를 동시에 추구하여 실온 저저항화를 도모할 수 있다. In recent years, as miniaturization, weight reduction, and high functionality of electronic devices are required, the necessity and development of lamination in ceramic parts is gradually increasing. In the case of the conventional single-plate ceramic PTC, it is known that it is difficult to manufacture below 10 Ωcm due to the inherent room temperature resistivity of the ceramic, but recently, a composition development having a room temperature resistivity of less than that has been reported. However, in order to have low resistance at room temperature, the cross-sectional area of the body has to be widened and the thickness of the ceramic body has to be extremely thin, so it is difficult to expect miniaturization of components. Therefore, in order to lower the room temperature resistance, as shown in FIG. 1, the internal electrodes 3 and the semiconductor ceramic layer 2 are alternately stacked, and external electrodes are formed on both ends, thereby reducing the thickness of the semiconductor ceramic layer and the large electrode surface. At the same time, the room temperature can be reduced.

종래의 적층형 PTC 서미스터(1)는 반도체 세라믹층(2)이 되는 세라믹 그린시트위에 내부전극(3)인 도전성 페이스트를 인쇄하여 내부전극용 도전성 페이스트가 한 단면에 도출되도록 교대로 적층하여 동시소성하고, 양 단면에 외부전극(4)용 도전성 페이스트를 형성하여 내부전극과 연결시킨 후 전극 열처리하는 방법을 사용하고 있었다. The conventional multilayer PTC thermistor 1 prints the conductive paste, which is the internal electrode 3, on the ceramic green sheet, which becomes the semiconductor ceramic layer 2, and alternately stacks the conductive paste for the internal electrode so as to be drawn out in one section. , The conductive pastes for the external electrodes 4 were formed on both end surfaces thereof, and then connected to the internal electrodes.

그러나, 현재 주로 사용되어 지고 있는 Zn, Fe, Sn, Ni 등의 전극재들은 우수한 옴성 접촉을 보이는 반면, 대부분 융점이 낮거나 높은 산화특성으로 인해 실온저항을 급격히 증대시켜 적층형 PTC 서미스터의 특성을 저하시키고 있었다. However, electrode materials such as Zn, Fe, Sn, and Ni, which are mainly used, show excellent ohmic contact, but in most cases, due to the low melting point or high oxidation characteristics, the room temperature resistance is rapidly increased to degrade the characteristics of the laminated PTC thermistor. I was letting go.

특히, 내부전극재로 Ni을 사용할 경우, 내부전극과 반도체 세라믹층을 적층하여 동시소성을 하기 때문에 융점이 낮은 Ni전극은 쉽게 산화되기 쉽고, 이를 방지하기 위해서는 강환원성 분위기하에서 소성이 요구되고 있다. 하지만, 이는 세라믹 PTC 소자의 PTC특성을 감소시키므로, 내환원성의 반도체 세라믹층의 필요성이 대두되고 있다. In particular, when Ni is used as the internal electrode material, since the internal electrode and the semiconductor ceramic layer are laminated and co-fired, the Ni electrode having a low melting point is easily oxidized. In order to prevent this, firing is required under a strong reducing atmosphere. However, since this reduces the PTC characteristics of the ceramic PTC element, there is a need for a reduction-resistant semiconductor ceramic layer.

본 발명에서는 상기와 같은 문제점으로 인한 PTC 특성의 저하를 개선하기 위해, 종래의 방식에 비해 추가비용이 발생하고 적층공정이 복잡해지기는 하나, 내부전극재의 산화로 인한 비옴성 접촉을 방지하여 낮은 실온저항과 높은 비저항변화율을 얻음으로써 고품질의 적층형 PTC 서미스터 소자를 얻고자 한다. In the present invention, in order to improve the deterioration of the PTC characteristics due to the above problems, additional costs are incurred compared to the conventional method, and the lamination process is complicated, but the low room temperature is prevented by preventing non-ohmic contact due to oxidation of the internal electrode material. By obtaining a resistance and a high resistivity change rate, a high quality laminated PTC thermistor device is to be obtained.

본 발명은 Ce을 첨가한 티탄산바륨을 주성분으로 하고 BN과 SiO2를 함유한 것을 특징으로 하는 반도체 세라믹조성물 및 그 제조방법, 그리고 그러한 조성물로 구성된 적층형 PTC 서미스터소자이다. The present invention is a semiconductor ceramic composition comprising a barium titanate added with Ce and containing BN and SiO 2 , a method for manufacturing the same, and a laminated PTC thermistor element composed of such a composition.

제 1발명은, Ce를 첨가한 티탄산바륨을 주성분으로 하고 BN과 SiO2를 함유하는 것을 특징으로 하는 반도체 세라믹 조성물로서, 정저항 온도특성을 갖는 티탄산바륨계 반도체 세라믹층을 포함하며 Ba자리에는 희토류원소인 3가의 Sm, Ce, Ho, Y, La, Dy, Pr, Yb, E등의 치환이 효과적이고, 우수한 옴성 접촉을 갖는 Zn, Sn, Ni등을 내부전극용 도전성 페이스트의 금속분말로 사용하는 것이 효과적이나, 본 발명에서는 Ni을 함유하는 도전성 페이스트를 내부전극용으로 이용함을 바람직하게 여기고 있다. 여기서 희토류 원소인 Ce의 함유량이 0.02mol% 인 것을 주된 특징으로 하는 한편, BN은 1.0~7.5mol%를 함유하고 SiO2 는 2~3mol%를 함유하는 것을 바람직한 성 분비율로 본다. 이러한 내환원성 조성물은 티탄산바륨에 Ce를 소량 첨가하여 1차로 제조한 후, 첨가제 BaCO3, MnCO3, BN, SiO2,를 실시예1의 (1)의 조성식으로 칭량, 혼합하여 에탄올, 산화지르코늄 볼과 함께 일정시간 혼합 분쇄, 건조하여 얻을 수 있다. A first invention is a semiconductor ceramic composition comprising barium titanate containing Ce as a main component and containing BN and SiO 2 , comprising a barium titanate-based semiconductor ceramic layer having a constant resistance temperature characteristic and having a rare earth in place of Ba. Substitution of trivalent Sm, Ce, Ho, Y, La, Dy, Pr, Yb, E, etc., which is an element, is effective, and Zn, Sn, Ni, etc., which have excellent ohmic contact, are used as the metal powder of the conductive paste for internal electrodes. Although it is effective to use the present invention, it is preferable to use a conductive paste containing Ni for the internal electrodes. The main feature here is that the content of Ce, which is a rare earth element, is 0.02 mol%, while BN contains 1.0 to 7.5 mol% and SiO 2 contains 2 to 3 mol% as a preferred sex fraction. This reducing resistance composition was prepared by first adding a small amount of Ce to barium titanate, and then weighing and mixing the additive BaCO 3 , MnCO 3 , BN, SiO 2 , according to the compositional formula of Example 1 (1), and ethanol and zirconium oxide. It can be obtained by mixing, grinding and drying with a ball for a certain time.

제2발명은, 티탄산바륨에 Ce을 첨가한 조성물에 대해 하소공정시의 하소분위기를 각각 공기중, 또는 산소/질소=20/80, 또는 질소, 또는 수소/질소=5/95, 또는 수소/질소=10/90로 하여 하소 분말을 얻은 후, 상기 제1발명의 첨가제와 조성식을 이용해 소성체를 얻는 제조방법이다. 이렇게 얻은 PTC 서미스터소자는 표2에서와 같이 실온저저항과 높은 비저항변화율을 갖는다. In the second invention, the calcination atmosphere in the calcination step for the composition in which Ce is added to barium titanate is in air, or oxygen / nitrogen = 20/80, or nitrogen, or hydrogen / nitrogen = 5/95, or hydrogen / It is a manufacturing method of obtaining a calcined body using the additive and composition formula of the said 1st invention after obtaining calcining powder with nitrogen = 10/90. The PTC thermistor element thus obtained has room temperature low resistance and high resistivity change rate as shown in Table 2.

제 3발명은, 내부전극이 교대로 적층되고 좌우 양 단면을 외부전극이 감싸는 적층형 PTC 서미스터로서, 상기 제2 발명의 제1 하소분위기 하에서 생성되고, 일표면에 내부전극이 인쇄된 세라믹층(12b-1)이 제2 하소분위기 하에서 생성된 세라믹층(12a)위에 적층되고, 그 위에 제1 하소분위기 하에서 생성된 세라믹층(12b-2)이 적층된 후 다시 제2 하소분위기 하에서 생성된 세라믹층(12a)이 적층되는 구조가 반복되는 것을 특징으로 한다. 완성된 내환원성 적층형 PTC 서미스터 소자는 반도체 세라믹층(12b-1, 12b-2)과 내부전극(13)이 교대로 적층된 소성칩 양 단면에 외부전극(14)를 형성함으로써 제조할 수 있다. 여기서 제1 또는 제2 하소분위기는 공 기, 또는 산소/질소=20/80, 또는 질소, 또는 수소/질소=5/95, 또는 수소/질소=10/90으로 하는 것 중 어느 하나인 것을 특징으로 한다. 이 경우 제1 하소분위기와 제2 하소분위기는 서로 동일하거나 다를 수 있다. 이렇게 해서 얻어진 PTC 서미스터 소자는 강환원분위기하의 소성공정에도 불구하고 낮은 실온저항과 높은 비저항변화율을 갖는 고품질의 PTC 서미스터소자가 된다. A third invention is a multilayer PTC thermistor in which internal electrodes are alternately stacked and both left and right cross-sections are surrounded by external electrodes, which are produced under the first calcination atmosphere of the second invention and have an internal electrode printed on one surface thereof. -1) is laminated on the ceramic layer 12a produced under the second calcination atmosphere, and the ceramic layer 12b-2 formed under the first calcination atmosphere is laminated thereon, and then again the ceramic layer produced under the second calcination atmosphere. The structure in which 12a is laminated is repeated. The completed reduction-resistant laminated PTC thermistor element can be manufactured by forming the external electrodes 14 on both end surfaces of the firing chip in which the semiconductor ceramic layers 12b-1 and 12b-2 and the internal electrodes 13 are alternately stacked. Wherein the first or second calcination atmosphere is one of air or oxygen / nitrogen = 20/80, or nitrogen, or hydrogen / nitrogen = 5/95, or hydrogen / nitrogen = 10/90. It is done. In this case, the first calcining atmosphere and the second calcining atmosphere may be the same or different from each other. The PTC thermistor element thus obtained becomes a high-quality PTC thermistor element having a low room temperature resistance and a high resistivity change rate despite the firing process under a strong reducing atmosphere.

본 발명은 실시예를 통해 더욱 상세히 설명한다. The invention is explained in more detail by way of examples.

본 발명의 적층형 PTC 서미스터 조성물의 합성방법 및 그 제조방법으로서, 각기 다른 열처리 분위기로 합성된 분말을 내부전극이 되는 도전성 페이스트와 반도체 세라믹층이 되는 세라믹 그린시트를 조합된 이종접합으로 적층하여 적층체를 형성하는 것을 특징으로 함으로써 실온저항치를 낮추고, 비저항변화율을 높일수 있다.A method of synthesizing the laminated PTC thermistor composition of the present invention and a method of manufacturing the same, wherein a powder synthesized in a different heat treatment atmosphere is laminated by a heterogeneous combination of a conductive paste serving as an internal electrode and a ceramic green sheet serving as a semiconductor ceramic layer. Forming a can reduce the room temperature resistance and increase the resistivity change rate.

이하, 적층형 PTC 서미스터에 대한 본 발명의 실시예를 구체적으로 설명하기로 한다. Hereinafter, embodiments of the present invention for a laminated PTC thermistor will be described in detail.

[실시예 1]Example 1

우선 내환원성의 PTC 서미스터 조성물을 얻기 위해, 출발원료로서 수산법으로 제조 된 Ba site / Ti site=0.998인 티탄산바륨에 희토류원소인 Ce을 소량 첨가한 조성물을 1차로 제조하고, 첨가제 BaCO3, MnCO3, BN, SiO2를 다음 조성식으로 칭량하여 혼합하였다. First of all, in order to obtain a reducing-resistant PTC thermistor composition, a composition prepared by adding a small amount of rare earth element Ce to barium titanate, Ba site / Ti site = 0.998, prepared by the hydroxyl method as a starting material, was first prepared, and additives BaCO 3 and MnCO were added. 3 , BN and SiO 2 were weighed and mixed with the following composition formula.

(Ba0 .998Ce0 .002)TiO3 + 0.03BaCO3 + 0.0002MnCO3 + xBN + ySiO2 ------------- (1)(Ba 0 .998 Ce 0 .002 ) TiO 3 + 0.03 BaCO 3 + 0.0002MnCO 3 + xBN + ySiO 2 ------------- (1)

상기의 식(1)과 같이 칭량, 첨가한 후 에탄올, 산화지르코늄 볼과 함께 24시간 혼합 분쇄하고, 건조하였다.After weighing and adding as in Formula (1) above, the mixture was pulverized with ethanol and zirconium oxide balls for 24 hours, and dried.

혼합분말을 10Φmm x 1.5mm의 단판형으로 성형한 후, 이 성형체를 970℃~1050℃에서 2시간동안 H2/N2=5%의 환원분위기하에서 저온소성해서 소성체를 얻었다. 또한 PTC 효과를 부여하기 위해 공기중 700℃에서 2시간 재산화 열처리를 행하였다. 이하에 실시예 1에 의해 얻어진 시료로 제조된 PTC 서미스터의 특성을 평가하고, 그 결과를 표 1에 나타내었다.After the mixed powder was molded into a single plate of 10 mm x 1.5 mm, the molded body was calcined at a low temperature of H 2 / N 2 = 5% for 2 hours at 970 ° C to 1050 ° C to obtain a fired body. In addition, reoxidation heat treatment was performed for 2 hours at 700 ° C. in air to impart a PTC effect. Below, the characteristic of the PTC thermistor manufactured by the sample obtained by Example 1 was evaluated, and the result is shown in Table 1.

[표1]Table 1

시 료 sample B원소량 xB element amount x Si원소량 ySi element amount y 실온비저항, 25℃ (Ωcm)Room temperature resistivity, 25 ℃ (Ωcm) 비저항변화율 Log(ρ285/ρ25)Resistivity change rate Log (ρ285 / ρ25) 소결성 Sinterability 1One 0.0250.025 00 -- -- xx 22 0.0250.025 0.010.01 12.512.5 3.123.12 33 0.0250.025 0.020.02 8.18.1 2.822.82 44 0.0250.025 0.030.03 6.46.4 2.352.35 55 0.0250.025 0.040.04 -- -- xx 66 00 0.020.02 9.39.3 2.42.4 77 0.010.01 0.020.02 9.19.1 2.72.7 88 0.050.05 0.020.02 7.97.9 3.13.1 99 0.0750.075 0.020.02 6.96.9 2.972.97 1010 0.10.1 0.020.02 6.06.0 1.81.8

[실시예 2] Example 2

본 발명의 출발원료로서 수산법으로 제조된 Ba site / Ti site=0.998인 티탄산바륨에 희토류원소인 Ce을 소량 첨가한 후 1150℃에서 2시간 하소하여 분말을 합성하였다. 이 때의 하소분위기는 각각 공기중, O2/N2=20/80, N2, H2/N2=5/95, H2/N2=10/90의 분위기하에서 행하였다. 또한 이 하소분말에 이하의 식(2)과 같이 칭량, 첨가한 후 에탄올, 산화지르코늄 볼과 함께 24시간 혼합 분쇄하고, 건조하였다. As a starting material of the present invention, a small amount of Ce, which is a rare earth element, was added to a barium titanate having Ba site / Ti site = 0.998 prepared by the fishery method, and then calcined at 1150 ° C. for 2 hours to synthesize a powder. The calcination atmosphere at this time was performed in air, O 2 / N 2 = 20/80, N 2 , H 2 / N 2 = 5/95, and H 2 / N 2 = 10/90, respectively. The calcined powder was weighed and added in the following formula (2), mixed with ethanol and zirconium oxide balls for 24 hours, and dried.

(Ba0 .998Ce0 .002)TiO3+0.03BaCO3+0.0002MnCO3+0.05BN + 0.02SiO2----------------- (2)(Ba 0 .998 Ce 0 .002 ) TiO 3 + 0.03BaCO 3 + 0.0002MnCO 3 + 0.05BN + 0.02SiO 2 ----------------- (2)

상기 조성을 갖는 혼합분말을 10Φmm x 1.5mm의 단판형으로 성형한 후, 이 성형체를 1000℃~1150℃에서 2시간동안 H2/N2=5%의 환원분위기하에서 저온소성해서 소성체를 얻었다. 또한 PTC 효과를 부여하기 위해 공기중 700℃에서 2시간 재산화 열처리를 행하였다.After the mixed powder having the above composition was molded into a single plate of 10 mm x 1.5 mm, the molded body was calcined at a low atmosphere of H 2 / N 2 = 5% for 2 hours at 1000 ° C to 1150 ° C to obtain a fired body. In addition, reoxidation heat treatment was performed for 2 hours at 700 ° C. in air to impart a PTC effect.

이하에 실시예 2에 의해 얻어진 시료로 제조된 PTC 서미스터의 특성을 평가하고, 그 결과를 표 2에 나타내었다.Below, the characteristic of the PTC thermistor manufactured by the sample obtained by Example 2 was evaluated, and the result is shown in Table 2.

[표2][Table 2]

시 료sample 세라믹층의 하소분위기Calcination atmosphere of ceramic layer 실온비저항, 25℃ (Ωcm)Room temperature resistivity, 25 ℃ (Ωcm) 비저항변화율 Log(ρ285/ρ25)Resistivity change rate Log (ρ285 / ρ25) 1111 공기air 7.97.9 3.13.1 1212 산소/질소=20/80Oxygen / nitrogen = 20/80 7.47.4 2.92.9 1313 질소nitrogen 6.56.5 3.273.27 1414 수소/질소=5/95Hydrogen / Nitrogen = 5/95 6.96.9 3.523.52 1515 수소/질소=10/90Hydrogen / Nitrogen = 10/90 7.97.9 3.743.74

[실시예 3]Example 3

실시예 1에 의해 제조된 각각의 혼합분말에 유기바인더, 분산제, 및 비수계용매인 톨루엔:에탄올=60:40의 솔벤트와 함께 20~50시간 혼합한 후, 세라믹 슬러리를 얻었다. 이 세라믹 슬러리는 닥터 블레이드법으로 시트형상으로 후막성형하고, 건조시켜서 세라믹 그린시트를 얻었다. Each mixed powder prepared in Example 1 was mixed with an organic binder, a dispersant, and a solvent of toluene: ethanol = 60: 40, which is a non-aqueous solvent, for 20 to 50 hours to obtain a ceramic slurry. This ceramic slurry was thick-film-formed in the sheet form by the doctor blade method, and it dried, and obtained the ceramic green sheet.

다음에, 내부전극층(13)을 형성하기 위해 세라믹 그린시트(12b-1,12b-2)위에 스크린인쇄에 의해 도전성 Ni 페이스트를 도포하고, Ni 전극이 인쇄된 그린시트를 교대로 적층한 후, 절단하여 적층체 양단면에 내부전극이 도출된 그린칩을 얻는다. Next, in order to form the internal electrode layer 13, conductive Ni paste is applied by screen printing on the ceramic green sheets 12b-1 and 12b-2, and the green sheets on which the Ni electrodes are printed are alternately laminated. By cutting, green chips in which internal electrodes are drawn on both end surfaces of the laminate are obtained.

본 발명의 적층형 PTC 서미스터의 구현예를 도2 및 도3에 나타내었고, 이하 도면을 참조하여 본 발명을 보다 상세히 설명한다. An embodiment of the laminated PTC thermistor of the present invention is shown in Figs. 2 and 3, and the present invention will be described in more detail with reference to the drawings.

도2는 본 발명의 실시예에 따른 적층형 PTC 서미스터의 구조를 도시한 개략 단면도이다. 2 is a schematic cross-sectional view showing the structure of a stacked PTC thermistor according to an embodiment of the present invention.

도3은 본 발명의 실시예에 따른 그린시트의 적층순서에 따라 도시한 개략 사시도이다.Figure 3 is a schematic perspective view showing the stacking order of the green sheet according to an embodiment of the present invention.

도3에서 보는 바와 같이 12a와 12b-1 및 12b-2는 실시예2 에 의해 얻어진 각각의 시료에 의해 제조된 세라믹 그린시트이며, 이들 각 시료에 따른 그린시트를 표 3에 나타낸 바와 같이 조합하여 적층하였다. As shown in Fig. 3, 12a, 12b-1, and 12b-2 are ceramic green sheets prepared by the respective samples obtained in Example 2, and the green sheets according to each of these samples were combined as shown in Table 3. Laminated.

구체적인 예를 들면, 표3에 나타낸 시료 20의 경우 12a는 N2 가스내에서 하소한 분말에 첨가제를 넣어 혼합 후 제조된 그린시트이고 12b-1 및 12b-2는 H2/N2=5/95의 가스내에서 하소하여 제조된 그린시트이다. For example, in the case of Sample 20 shown in Table 3, 12a is N 2. Green sheet prepared by mixing the additive in the powder calcined in the gas and 12b-1 and 12b-2 is a green sheet prepared by calcining in the gas of H 2 / N 2 = 5/95.

도2의 적층칩은 H2/N2=5/95의 환원분위기하에서 950℃~1050℃, 2시간, Ni 전극 페이스트를 동시소성한 후, 이렇게 하여 얻어진 소성칩은 건식으로 바렐연마를 행함으로써, 모서리부분를 둥굴게 연마했다. 또한 도2에서와 같이 반도체 세라믹층(12a,12b-1,12b-2)과 내부전극(13)이 교대로 적층된 소성칩의 양 단면에 Ohmic 접촉특성을 갖는 Ag 전극 페이스트를 도포한 후, 전극소부와 재산화열처리를 동시에 실행하여 외부전극(14)를 형성했다. In the laminated chip of FIG. 2, the Ni electrode paste was simultaneously fired at 950 ° C. to 1050 ° C. for 2 hours under a reducing atmosphere of H 2 / N 2 = 5/95, and the resulting firing chip was subjected to barrel polishing by dry drying. The edges were rounded and polished. In addition, as shown in FIG. 2, after applying the Ag electrode paste having ohmic contact characteristics to both end surfaces of the firing chip in which the semiconductor ceramic layers 12a, 12b-1, 12b-2 and the internal electrodes 13 are alternately stacked, The external electrode 14 was formed by simultaneously performing the electrode element portion and the reoxidation heat treatment.

이때의 재산화열처리는 600℃~800℃, 1시간, 공기중에서 행하였다. At this time, the reoxidation heat treatment was performed in the air at 600 ° C to 800 ° C for 1 hour.

이하에 실시예 3에 의해 제조된 적층형 PTC 서미스터의 특성을 평가하고, 그 결과를 표 3에 나타내었다.Below, the characteristic of the laminated PTC thermistor manufactured by Example 3 was evaluated, and the result is shown in Table 3.

[표3]Table 3

시 료sample 세라믹층의 하소분위기Calcination atmosphere of ceramic layer 실온저항, 25℃ (Ω)Room Temperature Resistance, 25 ℃ (Ω) 비저항변화율 Log(ρ285/ρ25)Resistivity change rate Log (ρ285 / ρ25) 12a12a 12b-1,12b-212b-1,12b-2 1616 AirAir AirAir 1.21.2 2.222.22 1717 N2 N 2 AirAir 0.870.87 2.982.98 1818 N2 N 2 20%O2 20% O 2 0.290.29 2.802.80 1919 N2 N 2 N2 N 2 0.230.23 3.673.67 2020 N2 N 2 5%H2 5% H 2 0.270.27 3.723.72 2121 N2 N 2 10%H2 10% H 2 0.30.3 3.983.98 2222 10%H2 10% H 2 AirAir 1.011.01 3.093.09 2323 10%H2 10% H 2 20%O2 20% O 2 0.560.56 3.113.11 2424 10%H2 10% H 2 N2 N 2 0.410.41 4.034.03 2525 10%H2 10% H 2 5%H2 5% H 2 0.520.52 4.324.32 2626 10%H2 10% H 2 10%H2 10% H 2 0.570.57 4.34.3

도면 1은 종래기술로 제조된 적층형 PTC 서미스터의 개략 단면도이다.1 is a schematic cross-sectional view of a laminated PTC thermistor manufactured in the prior art.

도면 2은 본원발명의 일실시예에 따른 적층형 PTC 서미스터의 개략 단면도이다. 2 is a schematic cross-sectional view of a stacked PTC thermistor according to an embodiment of the present invention.

도면 3은 본원발명의 일실시예에 따른 적층형 PTC 서미스터의 적층 전 개략 사시도이다. 3 is a schematic perspective view before lamination of a laminated PTC thermistor according to an embodiment of the present invention.

<도면의 주요부분에 대한 간단한 설명><Brief description of the main parts of the drawing>

11: 적층형 PTC 서미스터 12a,12b-1,12b-2: 반도체 세라믹층11: Stacked PTC Thermistor 12a, 12b-1, 12b-2: Semiconductor Ceramic Layer

13: 내부전극재 14: 외부전극13: internal electrode material 14: external electrode

Claims (7)

Ce을 첨가한 티탄산바륨을 주성분으로 하고 BN과 SiO2를 함유하되, 상기 BN의 함유량은 1.0~7.5mol% 이고 SiO2 의 함유량은 2~3mol% 인 것을 특징으로 하는 내환원성 반도체 세라믹조성물.A reduced resistance semiconductor ceramic composition comprising barium titanate containing Ce as a main component and containing BN and SiO 2 , wherein the BN content is 1.0 to 7.5 mol% and the SiO 2 content is 2 to 3 mol%. 제1항에 있어서, 상기 Ce의 함유량은 0.02mol%인 것을 특징으로 하는 내환원성 반도체 세라믹조성물.The reduction resistant semiconductor ceramic composition according to claim 1, wherein the content of Ce is 0.02 mol%. 삭제delete 삭제delete 삭제delete 내부전극과 세라믹층이 교대로 적층되고 좌우 양 단면을 외부전극이 감싸는 적층형 PTC 서미스터에 있어서, 제1 하소분위기 하에서 생성되고, 일 표면에 내부전극이 인쇄된 세라믹층(12b-1)이 제2 하소분위기 하에서 생성된 세라믹층(12a) 위에 적층되고, 그 위에 제1 하소분위기 하에서 생성된 세라믹층(12b-2)이 적층된 후, 다시 제2 하소분위기 하에서 생성된 세라믹층(12a)이 적층되는 구조가 반복되되,In a multilayer PTC thermistor in which internal electrodes and ceramic layers are alternately stacked, and external electrodes are wrapped around both left and right cross sections, a ceramic layer 12b-1, which is generated under a first calcination atmosphere and has an internal electrode printed on one surface thereof, is formed in a second type. The ceramic layer 12a formed under the calcination atmosphere is stacked, and the ceramic layer 12b-2 formed under the first calcination atmosphere is stacked thereon, and then the ceramic layer 12a generated under the second calcination atmosphere is laminated. Structure is repeated, 상기 제1 하소분위기 또는 제2 하소분위기는 공기, 또는 산소/질소=20/80, 또는 질소, 또는 수소/질소=5/95, 또는 수소/질소=10/90 중 어느 하나인 것을 특징으로 하는 적층형 PTC서미스터. The first calcining atmosphere or the second calcining atmosphere is air, or oxygen / nitrogen = 20/80, or nitrogen, or hydrogen / nitrogen = 5/95, or hydrogen / nitrogen = 10/90, characterized in that Stacked PTC Thermistors. 제6항에 있어서, 제1 하소분위기와 제2 하소분위기는 각각 다른 하소분위기를 특징으로 하는 적층형 PTC 서미스터.7. The stacked PTC thermistor of claim 6, wherein the first and second calcination atmospheres have different calcination atmospheres.
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