KR100911899B1 - Synchronous memory device for enhancing data align margin - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a memory device capable of stably receiving and processing data even at high frequencies by increasing the data alignment margin in aligning and transferring data input in synchronization with a clock to an internal circuit. The present invention relates to a synchronous memory device that receives a plurality of data in synchronization with a rising edge and a falling edge of an operation clock, wherein the rising edge and falling edge of a data strobe signal clocked at a timing at which data is input are inputted to first and second data, respectively. Latch means for receiving the alignment; A multiplexer for selecting and outputting the first and second data aligned by the latching means as rising data or polling data; A signal separator for adjusting and transmitting a skew between the rising data and the falling data output from the multiplexer; And outputting the rising data and the falling data output from the signal separation unit as even data or odd data in response to an internal strobe signal for allowing the rising data and the falling data to be transmitted to the cell array in synchronization with the operation clock. To this end, a synchronous memory device having a global input / output driver is provided.

Semiconductor, memory, latch, data strobe, output buffer.

Description

SYNCHRONOUS MEMORY DEVICE FOR ENHANCING DATA ALIGN MARGIN}             

1 is a block diagram showing a data input buffer of a synchronous memory device according to the prior art;

FIG. 2 is a timing diagram showing the operation of the memory device shown in FIG.

FIG. 3 is a timing diagram showing an operation problem of the memory device shown in FIG.

4 is a block diagram showing a 4-bit prefetch data input buffer of a synchronous memory device according to a preferred embodiment of the present invention;

FIG. 5 is a timing diagram showing an operation of the memory device shown in FIG. 4; FIG.

Fig. 6 is a block diagram showing a plurality of multiplexes having paths connected to each other for testing in an input buffer section of a memory device according to the present invention.

7 is a dummy transfer gate further provided in a multiplexer for improving the margin of a data strobe signal in a memory device of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous memory device, and more particularly, to a data alignment margin of a data input buffer unit for pre-fetching data and delivering the data to an internal core portion.

The semiconductor memory device has been continuously improved for the purpose of increasing the integration speed and increasing the operation speed thereof. In order to improve the operating speed, a so-called synchronous memory device capable of operating in synchronization with a clock given from a memory chip has been introduced.

The first proposal is a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one period of the clock at one data pin in synchronization with a rising edge of the clock from the outside of the memory device.

However, an SDR synchronous memory device is also insufficient to satisfy the speed of a system requiring high-speed operation. Accordingly, a double data rate (DDR) synchronous memory device, which processes two data in one clock cycle, has been proposed.

Each data entry / exit pin of the digital synchronous memory device continuously inputs and outputs two data in synchronization with a rising edge and a falling edge of an externally input clock. At least twice as much bandwidth as the SDR synchronous memory device can realize high-speed operation.

However, since the DL memory device needs to export or receive two data in one clock period, the data access method used in the conventional synchronous memory device cannot be used to effectively perform this.

If the clock cycle is about 10 nsec, subtracting the rise and fall time (approximately 0.5 × 4 = 2) and the time to meet other specifications, etc., the two data continuously for about 6 nsec or less. Since this processing is not sufficient to be performed inside the memory device, the memory device inputs and outputs data at the rising edge and the falling edge of the clock only when the data is sent to or received from the outside. It is treated as two pieces of data synchronized to one edge of.

Therefore, a new data access method is required to receive data from the memory device and transfer the data to the internal core area or to output data transmitted from the core area to the outside.

To this end, the data input buffer of the digital memory device prefetches data synchronized with the rising edge and the falling edge, and transfers the data to the internal core area by synchronizing the rising edge of the main clock with rising data or falling data.

Meanwhile, when data is input to realize accurate timing of data input / output, a data strobe signal (DQS) is input together with a data signal from a central processing unit (CUP) or a memory controller external to the memory device. do.

1 is a block diagram showing a data input buffer portion of a synchronous memory device according to the prior art.                         

Referring to FIG. 1, a data input buffer unit of a synchronous memory device is enabled by an enable signal en_dinds generated by a write command, and a rising pulse generated at a rising edge and a falling edge of a data strobe signal DQS, respectively. The data strobe buffer 21 outputs the dsrp and the falling pulse dsfp, the data buffer 10 receives data from the outside, and the data buffer 10 outputs the rising pulse dsrp. To the rising latch unit 11 for latching the data to be converted, the falling latch unit 12 for latching the data output from the data buffer unit by the falling pulse dsfp, and the falling pulse dsfp. The data alignment unit 13 which aligns the falling data falling_data and the alignment output data align_dr output from the falling latch unit 12 by latching and outputting the data signal rising_data output from the rising latch unit. ), First and second alignment delays 14 and 15 that receive the alignment output data align_dr and the output data falling_data of the falling latch unit 12 and delay them for a predetermined time, and And a multiplexer 16 for outputting the output signals of the second alignment delays 14 and 15 as rising data rd or polling data fd depending on the test mode. A first signal separator 17 for separating and outputting the rising data rd output from the lexer 16 into the first rising data rd 'buffered and the second rising data / rd which is an inverted signal thereof; And a second signal separator for separating and outputting the polling data fd output from the far multiplexer 16 into the first polling data fd 'buffered and the second polling data / fd which is an inverted signal thereof. 18) and the first and second rising data rd ', / rd and the first and second polling data fd' and / fd output from the first and second signal separators 17 and 18. Internal strobe input In response to the response number (data_strobe_rd, data_stobe_od) comprises an even number of data (gio_ev) and odd data (gio_od) the first and second global output driver (19, 20) for outputting.

FIG. 1B illustrates the first signal separator 17 of FIG. 1.

FIG. 2 is a timing diagram illustrating an operation of the data input buffer shown in FIG. 1.

Hereinafter, an operation of a data input buffer for prefetching four data will be described with reference to FIGS. 1A and 2.

First, the data D0 to D3 are input in synchronization with the rising edge and the falling edge of the clock CLK, and the data strobe signal DQS is input in accordance with the timing at which the data is input.

The data strobe signal DQS is normally maintained in a high impedance state, and then clocked during the timing at which data is input in a preamble state in which a low level is held in advance before a clock is input, and all data is input. After that, it maintains a low level postamble for a certain period of time and then maintains a high impedance state again.

The data strobe buffer unit 21 is enabled by an enable signal (endinds) generated by a write command, and a rising pulse (dsrp) outputted in a pulse form at the rising edge of the data strobe signal (DQS) and the data strobe signal. Generate and output a falling pulse (dsfp) outputted in the form of a falling edge pulse of (DQS).

Subsequently, the rising latch unit 11 latches the first data and the third data D0 and D2 by the rising pulse dsrp and outputs the rising data as rising_data. Then, the latching latch unit 12 latches the second data and the fourth data D1 and D3 by the falling pulse dsfp to output the falling data falling_data, while the data alignment unit raises the rising data rising_data. Is latched again by the falling pulse (dsfp) and output as alignment data (align_data). The data aligning unit 13 is for data aligning between the first data D0 and the second data D1.

Subsequently, the alignment data (align_data) and the falling data (falling_data) are delayed by the first alignment delays 14 and 15 for a predetermined time and output to the multiplexer 16.

Next, the multiplexer 16 selects the alignment data (align_data) and the falling data (falling_data) as the rising data (rd) and the falling data (fd) and outputs them to the next stage. Subsequently, the first signal separator 17 generates and outputs the first rising data rd 'buffering the rising data rd and the second rising data / rd which is an inverted signal thereof, and outputs the second rising signal. 18 generates and outputs the first polling data fd 'buffering the polling data fd and the second polling data / fd which is an inverted signal thereof.

The reason why the single data is formed into the buffered data and the inverted data is because the input stages of the global input / output drivers 19 and 20 of the next stage are in the form of differential amplifiers. The differential stage of the input stage of the global I / O driver is to drive the global I / O line at higher speed. The global input / output line is provided at one side of the cell array and is connected to a bit line sense amplifier for sensing and amplifying data of a unit cell.

FIG. 3 is a timing diagram illustrating an operation problem of the memory device shown in FIG. 2. Hereinafter, the problems caused by the prior art will be described with reference to FIGS. 1A, 1B, and 3.

After the write command is input from the memory device, the data strobe signal DQS input during the data input timing is input with a margin of (WL-0.25) x tCK to (WL + 0.25) x tCK. In this case, WL means write latency, and indicates the timing from when a write command is input until data is input.

Therefore, the data strobe signal DQS input at the data input timing is input with a margin of about 0.5 tCK. That is, if WL = 1, the data strobe signal (DQS) is input after 0.75 x tCK after the write command is input at a moment when the memory device operates, and 1.75 x after the write command is input at another moment. The data strobe signal DQS may be input after the tCK. Therefore, the data D0, D2, ... latched by DQS1 and the data D0, D2, ... latched by DQS2 have an interval of 0.5 x tCK.

DQS1 shown in FIG. 3 represents a data strobe signal inputted after 0.75 x tCK after the write command is input, and DQS2 represents a data strobe signal DQS inputted after 1.75 x tCK after the write command is input. .

At this time, in order to ensure that the aligned data is correctly delivered to the global I / O line, the internal strobe signal (data_stobe) must be generated in the section shared by the data latched by DQS1 and DSQ2 and input to the global I / O line driver. do.                         

Therefore, the margin that can receive and align data from the synchronous memory device is 0.5 x tCK. In the memory device operating at 500 MHz, the period of the operation clock is tCK = 2n, and the margin at which the internal data strobe signal data_stobe can be input is 1n.

In this case, when considering the margin before and after the internal strobe signal (data_strobe), the margin of the internal strobe signal (data_strobe) is only about 0.5n, so that the aligned data cannot be properly delivered to the internal global I / O line. do.

This value is actually reduced by several process variables, temperature, and circuit errors, so the faster the memory operation, the greater the chance of malfunction.

Therefore, in order to solve this problem, the first and second alignment delays 17 and 18 are additionally provided in front of the multiplexer 16 for the margin of the internal data Stove signal data_stobe to delay the input data for a predetermined time.

On the other hand, skew between the rising data rd and the falling data fd passing through the multiplexer is mismatched in the process of latching and aligning the data, and circuitry inside the multiplexer. The difference in junction capacitance and the number of inverters through which data signals pass through the first and second signal separation units 17 and 18 are different (see FIG. 1B).

As shown in FIG. 3, in the memory device operating at a high speed, only a small amount of skew occurs between the rising data and the falling data so that the margin for aligning the data is greatly reduced.

The present invention has been proposed to solve the above problems, by aligning the data input in synchronization with the clock to increase the data alignment margin in the transfer to the internal circuit can receive and process the data stably at high frequency It is an object to provide a memory device.

In order to solve the above problems, the present invention is a synchronous memory device that receives a plurality of data in synchronization with the rising edge and the falling edge of the operation clock, the rising edge and polling of the data strobe signal clocked at the timing of input data Latch means for receiving and aligning first and second data with an edge, respectively; A multiplexer for selecting and outputting the first and second data aligned by the latching means as rising data or polling data; A signal separator for adjusting and transmitting a skew between the rising data and the falling data output from the multiplexer; And outputting the rising data and the falling data output from the signal separation unit as even data or odd data in response to an internal strobe signal for allowing the rising data and the falling data to be transmitted to the cell array in synchronization with the operation clock. To this end, a synchronous memory device having a global input / output driver is provided.

In addition, the present invention is a synchronous memory device that receives a plurality of data in synchronization with the rising edge and the falling edge of the operation clock, the rising edge of the first data strobe signal clocked at the timing of the data input through the first data input pin First latch means for receiving and aligning first and second data to the falling edge and the falling edge, respectively; A first multiplexer for selecting and outputting the first and second data aligned by the first latching means as first rising data or first falling data; Second latch means for receiving and aligning third and fourth data with the rising and falling edges of the second data strobe signal clocked at the timing of input of data through the second data input pin; A second multiplexer for selecting and outputting the third and fourth data aligned by the second latching means as second rising data or second falling data; A test data path for transferring test data input through the first data input pin to the second multiplexer in a test mode; And a signal separator for adjusting and transferring skew between the first and second rising data and the first and second falling data, wherein the second multiplexer has an input capacitance equal to the input capacitance of the first multiplexer. A memory device is characterized by having a dummy load to have.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a block diagram illustrating a data input buffer of a synchronous memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a synchronous memory device that receives a plurality of data in synchronization with a rising edge and a falling edge of an operation clock has a rising edge and a falling edge of a data strobe signal DQS clocked at a timing at which data is input. The latch unit 23 that receives and aligns the first and second data, and the first and second data aligned by the latch unit 23 are selected as rising data rd or polling data fd. A multiplexer 24 for outputting, a signal separator 25 for adjusting and passing a skew between the rising data rd and polling data fd outputted from the multiplexer 24, and synchronizing with an operation clock In response to the internal strobe signals (data_strobe_ev, data_stobe_od) for allowing the rising data (rd) and the falling data (fd) to be transferred to the cell array, the rising data and the falling data output from the signal separation unit 25 are even. A global input / output driver 26 for outputting data (gio_ev) or odd data (gio_od) is provided.

In addition, the signal separator 25a receives the rising data rd and outputs the first rising data rd 'buffered and the second rising data / rd which is an inverted signal thereof. And a second signal separator 25b that receives the polling data fd and buffers the first polling data fd 'and outputs the second polling data / fd which is an inverted signal thereof.

The global input / output driver 26 includes a first global input / output driver 26a having a first differential amplifier for receiving first rising data rd 'and second rising data (/ rd), and first falling data fd. And a second global input / output driver 26b having a second differential amplifier receiving the second polling data / fd.                     

FIG. 5 is a timing diagram illustrating an operation of the memory device shown in FIG. 4.

Hereinafter, the operation of the memory device according to the present embodiment will be described with reference to FIGS. 5 and 6.

First, data is input in synchronization with the rising edge and the falling edge of the clock CLK, and the data strobe signal DQS is clocked in accordance with the timing at which the data is input.

The data strobe buffer unit 27 is enabled by an enable signal (endinds) generated by a write command, and a rising pulse (dsrp) outputted in a pulse form at the rising edge of the data strobe signal (DQS) and the data strobe signal. Generate and output a falling pulse (dsfp) outputted in the form of a falling edge pulse of (DQS).

Subsequently, the rising latch unit 23a latches the first data and the third data by the rising pulse dsrp and outputs the rising data as rising_data. Subsequently, the falling latch unit 23b latches the second data and the fourth data by the falling pulse dsfp to output the falling data falling_data, while the data alignment unit polls the rising data rising_data falling pulse dsfp. ) And latch again to output align_data. In this case, the data alignment unit 23c is for data alignment between the first data D0 and the second data D1.

Subsequently, the align data (falling_data) and the falling data (falling_data) are input to the multiplexer 16, and then the multiplexer 24 converts the alignment data (align_data) and the falling data (falling_data) to the rising data (rd) and the falling data ( Select fd) and output to the next stage.

Subsequently, the first signal separator 25a generates and outputs the first rising data rd 'buffering the rising data and the second rising data / rd, which is an inverted signal thereof, and outputs the second rising signal 25b. Generates and outputs the first polling data fd 'buffering the polling data fd and the second polling data / fd which is an inverted signal thereof.

The signal separating unit 25 forms one data into buffered data and inverted data because the input terminal of the next global input / output driver 26 is in the form of a differential amplifier.

The differential stage of the input stage of the global input / output driver 26 is for driving the global input / output line at a higher speed. The global input / output line is connected to a bit line sense amplifier provided at one side of the cell array. Data output from the global input / output driver 26 is stored in a unit cell of a corresponding cell array via a bit line sense amplifier.

Here, the memory device of the present invention includes a signal separation unit 25 for adjusting the skew of the rising data rd and the falling data fd at the next stage of the multiplexer 24, thereby completely removing the skew. Output to the driver 26 is now possible.

The global I / O driver 26 transmits the rising data and the polling data to the internal cell array in synchronization with the operation clock. The data input to the global I / O driver 26 has the DQS signal (WL-0.25) × as described above. It is input with margin of tCK ~ (WL + 0.25) x tCK. In this case, WL means write latency, and indicates the timing from when a write command is input until data is input.

Therefore, the data strobe signal DQS input at the data input timing is input with a margin of about 0.5 tCK. That is, if WL = 1, the data strobe signal (DQS) is input after 0.75 x tCK after the write command is input at a moment when the memory device operates, and 1.75 x after the write command is input at another moment. The data strobe signal DQS may be input after the tCK.

DQS1 shown in FIG. 5 represents a data strobe signal inputted after 0.75 x tCK after the write command is input, and DQS2 represents a data strobe signal DQS inputted after 1.75 x tCK after the write command is input. . Therefore, the data D0, D2, ... latched by DQS1 and the data D0, D2, ... latched by DQS2 have an interval of 0.5 x tCK.

In order to ensure that the aligned data is correctly delivered to the global I / O line, the internal strobe signal data_stobe is necessarily generated in the section where the data latched by the DQS1 and DSQ2 are shared, and the input to the global I / O line driver 250 is performed. Should be.

However, according to the present invention, the signal separation unit 25 for adjusting the skew of the rising data rd and the falling data fd is provided at the next stage of the multiplexer 24, that is, immediately before the global input / output driver 26. The data input to the global input / output driver 26 does not have skew (see FIGS. 3 and 5).

This indicates that the margin that can be aligned by inputting data to the synchronous memory device in the prior art is increased. As the margin for data input and alignment increases, the memory device can reliably transfer data to the internal core. In addition, when developing a synchronous memory device that operates at a higher speed in the future, the margin for aligning the input data is sufficient, so that the current data input buffer can be used as it is.

On the other hand, the memory device operating in the x4, x8, x16 mode has 16 DQS signal input pins and 16 data signal input pins, and each data input buffer is formed as shown in the block diagram shown in FIG. do. However, to save test time, all 16 data input pins are not used, but test data is input through 4 or 8 input pins.

Therefore, a data transfer path between the multiplexers is provided for the test, which is illustrated in FIG. 6. This causes a difference in load capacitance between the multiplexers at the input of the multiplexer. Therefore, the transmission speed of the signal is different depending on the pin to which data is input. As a result, the margin of the internal strobe signal input to the global input / output drive is reduced.

The present invention proposes to add a dummy circuit to equalize the input load capacitance between multiplexers in order to solve the foregoing.

FIG. 6 is a block diagram showing a plurality of multiplexes connected to each other for testing in an input buffer portion of a memory device, and FIG. 7 is further provided in a multiplexer for improving the margin of a data strobe signal in a memory device of the present invention. It is a circuit diagram which shows a dummy transfer gate.

Referring to FIG. 6, according to the present embodiment, a synchronous memory device that receives a plurality of data in synchronization with a rising edge and a falling edge of an operation clock clocks at a timing at which data is input through a first data input pin DQ0. The first latch unit 23_1 and the first latch unit 23_1 that are aligned with the first and second data are respectively input to the rising and falling edges of the first data strobe signal DQS0. Data is input through the first multiplexer 24_1 and the second data input pin DQ1 to select and output the first and second data as the first rising data rd0 or the first polling data fd0. By the second latch unit 23_2 and the second latch unit 23_2 which receive and align the third and fourth data to the rising and falling edges of the second data strobe signal DQS1 clocked at timing. The third and fourth aligned data; A second multiplexer 24_2 for selecting and outputting the easing data rd1 or the second polling data fd1 and a test data input through the first data input pin DQ0 in a test mode; A test data path 40 for passing to 24_2, and a signal for adjusting and passing the skew between the first and second rising data rd0 and rd1 and the first and second polling data fd0 and fd1. The separation unit 25_1 and 25_2 may be provided, and the second multiplexer 24_2 may have a dummy load to have an input capacitance equal to the input capacitance of the first multiplexer 24_1.

7 shows dummy transmission gates 30 and 31 additionally provided in the second multiplexer as described above.                     

As shown in FIG. 7, the two signals align_dr0 and falling_data0 input to the first multiplexer 24_1 are also input to the second multiplex 24_2 through the path buffer unit 40. It is a path provided further.

The path buffer unit 40 is provided to input data to 16 data input pins at the same time in order to reduce the test time when testing a memory device having a mode such as × 4, × 8 × 16, or the like.

The multiplexers of the data input pins used in the test and the multiplexers of the unused input pins have different load capacitances at the input stages.

As a result, even if the signal separating unit is provided at the next stage of the multiplexer in the path where data is input, skew between the first rising data rd0 and the second rising data rd1 occurs.

In the memory device according to the present exemplary embodiment, a dummy circuit is appropriately added to the multiplexer so that the input load capacitances of the first multiplexer and the second multiplexer are equal to each other, so that the first rising data rd0 and the second rising data rd1 are the same. No skew was produced.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

Since the alignment margin of the data input by the present invention can be secured more than that of the conventional memory device, the data can be stably received and accessed even in a high speed memory device.

Claims (4)

In the synchronous memory device receiving a plurality of data in synchronization with the rising edge and the falling edge of the operation clock, Latch means for receiving and aligning first and second data with a rising edge and a falling edge of a data strobe signal clocked at a timing at which data is input; A multiplexer for selecting and outputting the first and second data aligned by the latching means as rising data or polling data; A signal separator for adjusting and transmitting a skew between the rising data and the falling data output from the multiplexer; And In response to an internal strobe signal for synchronizing the operation clock so that the rising data and the falling data can be transmitted to the cell array, to output the rising data and the falling data output from the signal separation unit as even data or odd data. Global I / O Driver A synchronous memory device having a. The method of claim 1, The signal separation unit A first signal separation unit which receives the rising data and outputs the first rising data buffered and the second rising data which is an inverted signal thereof; And And a second signal separator configured to receive the polled data and output the first polled data buffered and the second polled data which is an inverted signal thereof. The method of claim 2, The global input output driver A first global input / output driver having a first differential amplifier configured to receive the first rising data and the second falling data; And And a second global input / output driver having a second differential amplifier configured to receive the first polling data and the second polling data. In the synchronous memory device receiving a plurality of data in synchronization with the rising edge and the falling edge of the operation clock, First latch means for receiving and aligning first and second data to a rising edge and a falling edge of a first data strobe signal clocked at a timing at which data is input through the first data input pin; A first multiplexer for selecting and outputting the first and second data aligned by the first latching means as first rising data or first falling data; Second latch means for receiving and aligning third and fourth data with the rising and falling edges of the second data strobe signal clocked at the timing of input of data through the second data input pin; A second multiplexer for selecting and outputting the third and fourth data aligned by the second latching means as second rising data or second falling data; A test data path for transferring test data input through the first data input pin to the second multiplexer in a test mode; And A signal separator for adjusting and transferring a skew between the first and second rising data and the first and second falling data, wherein the second multiplexer has an input capacitance equal to the input capacitance of the first multiplexer. And a dummy load.

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