KR100543936B1 - Synchronous memory device for enhancing data align margin - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a memory device capable of stably receiving and processing data even at high frequencies by increasing the data alignment margin in aligning and transferring data input in synchronization with a clock to an internal circuit. The present invention provides a synchronous memory device that receives a plurality of data in synchronization with a rising edge and a falling edge of an operation clock, and receives a data strobe signal clocked at a timing at which the data is input. A first rising pulse and a first falling pulse for detecting a rising edge and a falling edge of an odd-numbered input data strobe signal, and a second rising pulse for detecting a rising edge and a falling edge of an even-numbered input data strobe signal, respectively; Data strobe buffering means for outputting a second falling pulse; First latch means for aligning first data input to a rising edge of the operation clock and second data input to the falling edge of the operation clock so as to be synchronized with the first falling pulse; Second latch means for outputting first and second aligned data realigned with the first and second data aligned to the first latching means so as to be synchronized with the second falling pulse; Third latch means for outputting third and fourth alignment data in which third data and subsequent fourth data are aligned after the second data so as to be synchronized with the second falling pulse; And a global input / output line driver for selecting and outputting the first to fourth alignment data as even data or odd data.

Semiconductor, memory, latch, prefetch, data strobe, output buffer.

Description

SYNCHRONOUS MEMORY DEVICE FOR ENHANCING DATA ALIGN MARGIN}             

1 is a block diagram showing a 2-bit prefetch data input buffer of a synchronous memory device according to the prior art;

FIG. 2 is a timing diagram showing the operation of the data input buffer shown in FIG.

Fig. 3 is a block diagram showing a 4-bit prefetch data input buffer of a synchronous memory device according to the prior art.

FIG. 4 is a timing diagram showing the operation of the data input buffer shown in FIG.

FIG. 5 is a timing diagram showing an operation problem of the data input buffer shown in FIG.

Fig. 6 is a block diagram showing a 4-bit prefetch data input buffer of a synchronous memory device in accordance with a preferred embodiment of the present invention.

FIG. 7 is a block diagram showing the data strobe buffer shown in FIG.

FIG. 8 is a circuit diagram showing an embodiment of the data strobe divider shown in FIG.

FIG. 9 is a timing diagram showing the operation of the data input buffer shown in FIG.

10 is a timing diagram showing a data alignment margin of the data input buffer shown in FIG.

* Description of the major symbols in the drawings

211-213, 221, 222, 231-233: Latch

ND1 to ND4: NAND Gate

NOR1: NORGATE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous memory device, and more particularly, to a data alignment margin of a data input buffer unit for pre-fetching data and delivering the data to an internal core portion.

The semiconductor memory device has been continuously improved for the purpose of increasing the integration speed and increasing the operation speed thereof. In order to improve the operating speed, a so-called synchronous memory device capable of operating in synchronization with a clock given from a memory chip has been introduced.

The first proposal is a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one period of the clock at one data pin in synchronization with a rising edge of the clock from the outside of the memory device.

However, an SDR synchronous memory device is also insufficient to satisfy the speed of a system requiring high-speed operation. Accordingly, a double data rate (DDR) synchronous memory device, which processes two data in one clock cycle, has been proposed.

Each data entry / exit pin of the digital synchronous memory device continuously inputs and outputs two data in synchronization with a rising edge and a falling edge of an externally input clock. At least twice as much bandwidth as the SDR synchronous memory device can realize high-speed operation.

However, since the DL memory device needs to export or receive two data in one clock cycle, the data access method used in the conventional synchronous memory device cannot be used to effectively perform this.

If the clock cycle is about 10 nsec, subtracting the rise and fall time (approximately 0.5 × 4 = 2) and the time to meet other specifications, etc., the two data continuously for about 6 nsec or less. Since this processing is not sufficient to be performed inside the memory device, the memory device inputs and outputs data at the rising edge and the falling edge of the clock only when the data is sent to or received from the outside. It is treated as two pieces of data synchronized to one edge of.

Therefore, a new data access method is required to receive data from the memory device and transfer the data to the internal core area or to output data transmitted from the core area to the outside.

To this end, the data input buffer of the digital memory device prefetches 2 bits of data synchronized with the rising and falling edges and transfers the data to the internal core area by synchronizing the rising edge of the main clock with even or odd data. Doing.

Meanwhile, when data is input to implement accurate timing of data input / output, a data strobe signal (DQS) is input together with a data signal from a CPU or a memory controller external to the memory device. do.

1 is a block diagram showing a 2-bit prefetch data input buffer of a synchronous memory device according to the prior art.

Referring to FIG. 1, a 2-bit prefetch data input buffer of a synchronous memory device is enabled by an enable signal en_dinds generated by a write command, respectively, to the rising edge and the falling edge of the data strobe signal DQS. Data strobe buffer unit for outputting rising pulse (dsrp) and polling pulse (dsfp), data buffer unit for receiving data from outside, and data output from data buffer unit by rising pulse (dsrp) Latching latch, latching latch latching data output from the data buffer unit by the falling pulse (dsfp), and latching data signal (rising_data) outputting from the rising latch by the pulse (dsfp) A data alignment unit for aligning the falling data (falling_data) and the alignment output data (align_dr) output from the falling latch by outputting A global I / O line driver is provided which receives data align_dr and output data of falling latches and outputs even or odd data into the memory device in response to an internal strobe signal data_strobe.

FIG. 2 is a timing diagram illustrating an operation of the data input buffer shown in FIG. 1.

Hereinafter, an operation of a data input buffer for prefetching 2 bits will be described with reference to FIGS. 1 and 2.

First, referring to FIG. 2, the data D0 to D3 are input in synchronization with the rising edge and the falling edge of the clock CLK, and the data strobe signal DQS is input in accordance with the timing at which the data is input.

The data strobe signal DQS is normally maintained in a high impedance state, and then clocked in accordance with the timing at which data is input in a preamble state in which a low level is maintained before a clock is input. Once input, it maintains a low level postamble for a certain period of time and then maintains a high impedance state again.

The data strobe buffer unit is enabled by an enable signal (endinds) generated by a write command, and outputs a rising pulse dsrp and a data strobe signal DQS outputted in the form of a pulse at the rising edge of the data strobe signal DQS. Generates and outputs a falling pulse (dsfp) that is output in the form of a falling edge pulse.

Subsequently, the rising latch latches the first data and the third data D0 and D2 by the rising pulse dsrp and outputs the rising data as rising_data. Next, the latching latch latches the second data and the fourth data D1 and D3 by the falling pulse dsfp to output the falling data falling data, while the data alignment unit polls the rising data rising_data. It is latched again by (dsfp) and output as alignment data (align_data). The data aligning unit is for aligning data transmitted to the global input / output line driver.

Subsequently, the global input / output line driver transmits the alignment data (align_data) and the falling data (falling_data) to the global input / output line (Global I / O) in response to the internal strobe signal data_strobe. Thereafter, the data applied to the global input / output line is sensed and amplified by the input / output sense amplifier and then transferred to the cell array.

However, as semiconductor devices such as the central processing unit become faster, there is a demand to operate the memory device at a higher speed. For this purpose, a 4-bit prefetch data input buffer that prefetches 4 bits of data and passes the data inside the memory device Was proposed.

Fig. 3 is a block diagram showing a 4-bit prefetch data input buffer of a synchronous memory device according to the prior art.

Referring to FIG. 3, the 4-bit prefetch data input buffer of the synchronous memory device is enabled by an enable signal en_dinds generated by a write command, respectively, to the rising edge and the falling edge of the data strobe signal DQS. The data buffer unit 190 outputs the generated rising pulse dsrp4 and the falling pulse dsfp4, the data buffer unit 100 which receives data from the outside, and the rising buffer dsrp4. The first rising latch 110 for latching the data output from 100 and outputting the first rising data rising_d0 and the first rising data rising_d0 by the falling pulse dsfp4 to latch the third data. The second rising latch 120 outputting the alignment data align_dr1 and the third rising latch latching the third alignment data align_dr1 by the rising pulse dsrp4 to output the second rising pulse dris_d1. 140 and the second d The fourth rising latch 140 outputs the first alignment data align_r0 by latching the gaging data rising_d1 by the falling pulse dsfp4, and outputs the data from the data buffer unit 100 by the falling pulse dsfp4. The first falling latch 130 that latches the data data and outputs the fourth alignment data align_df1 and the fourth alignment data align_df1 are latched by the rising pulse dsrp4 to fall data falling_d1. ) The second falling latch 150 for outputting the), the third falling latch 150 for latching the falling data (falling_d1) by the falling pulse (dsfp4) and outputting the second alignment data (align_df0), and the first To the fourth input data (align_dr0, align_df0, align_dr1, align_df1) in response to the internal strobe signal data_strobe to the global input / output line GIO as even data (gid_ev0, gio_ev1) or odd data (gid_od0, gio_od1). A global input / output line driver 180 for outputting is provided.

FIG. 4 is a timing diagram illustrating an operation of the data input buffer shown in FIG. 3.

Hereinafter, an operation of a data input buffer for prefetching 4 bits will be described with reference to FIGS. 3 and 4.

First, referring to FIG. 4, the data D0 to D7 are input in synchronization with the rising edge and the falling edge of the clock CLK, and the data strobe signal DQS is input in accordance with the timing at which the data is input.

The data strobe buffer unit 190 is enabled by an enable signal (endinds) generated by a write command, and a rising pulse (dsrp4) outputted in a pulse form at the rising edge of the data strobe signal (DQS), and the data strobe signal. Generate and output a falling pulse (dsfp4) output in the form of a falling edge pulse of (DQS).

Subsequently, the first rising latch 110 latches the first, third, five, and seventh data D0, D2, D4, and D6 by the rising pulse dsrp4 and outputs the first rising data rising_d0.

Subsequently, the second rising latch 120 latches the first rising data rising_d0 by the falling pulse dsfp4 to output the third alignment data align_r1, and the first falling latch 130 has the falling pulse dsfp4. ) Latches the second, fourth, sixth and eighth data D1, D3, D5, and D7 and outputs the fourth alignment data align_f1.

Subsequently, the third rising latch 140 latches the third alignment data align_r1 by the rising pulse dsrp4 to output the second rising data 160, and the second falling latch 150 may raise the rising pulse ( The fourth alignment data align_f1 is latched by the dsfp4 and output as the falling data falling_d1.

Subsequently, the fourth rising latch 160 latches the second rising data rising_d1 by the falling pulse dsfp4 and outputs the first rising data align_r0, and the third falling latch 170 is the falling pulse fsfp4. ), The polling data (align_df0) is latched and output as the second alignment data (align_f0).

Subsequently, the global input / output line driver 180 may select the first to fourth alignment data align_dr0, align_df0, align_dr1, and align_df1 in even data (gid_ev0, gio_ev1) or odd data (gid_od0, gio_od1) in response to the internal strobe signal data_strobe. ) To the global I / O.

As shown in FIG. 4, when the internal strobe signal data_strobe is input to the global input / output line driver 180, the first to fourth alignment data (align_dr0, align_df0, align_dr1, and align_df1) that are aligned and input at that time are inputted. It is delivered to the global I / O line (gio line). Therefore, in order to properly transfer 4-bit data aligned to the global input / output line to the internal core region, the internal strobe signal data_strobe must be output to the global input / output line driver in the section 'X'.

FIG. 5 is a timing diagram illustrating a problem of the data input buffer prefetching the 4 bits shown in FIG. 4. Next, the problem of the data input buffer for prefetching 4 bits according to the prior art will be described with reference to FIG. 5.

After the write command is input from the memory device, the input data strobe signal DQS is input with a margin of (WL-0.25) x tCK to (WL + 0.25) x tCK. In this case, WL means write latency, and indicates the timing from when a write command is input until data is input.

Therefore, the data strobe signal DQS input at the data input timing is input with a margin of about 0.5 tCK. That is, if WL = 1, the data strobe signal (DQS) is input after 0.75 x tCK after the write command is input at a moment when the memory device operates, and 1.75 x after the write command is input at another moment. The data strobe signal DQS may be input after the tCK.

DQS1 shown in FIG. 5 represents a data strobe signal inputted after 0.75 x tCK after the write command is input, and DQS2 represents a data strobe signal DQS inputted after 1.75 x tCK after the write command is input. .

Therefore, the data D0, D2, ... latched by DQS1 and the data D0, D2, ... latched by DQS2 have an interval of 0.5 x tCK.

In order for the aligned data to be correctly delivered to the global I / O line, the internal strobe signal data_stobe must be generated in the section shared by the data latched by the DQS1 and DSQ2 and input to the global I / O line driver.

Therefore, the margin that can receive and align data from the synchronous memory device is 0.5 x tCK. In the memory device operating at 500 MHz, the period of the operation clock is tCK = 2n, and the margin at which the internal data strobe signal data_stobe can be input is 1.0n.

In this case, when considering the margin before and after the internal strobe signal (data_strobe), the margin of the internal strobe signal (data_strobe) is only about 0.5n, so that the aligned data cannot be properly delivered to the internal global I / O line. do.

As memory devices become faster and faster, the margin of the internal strobe signal (data_strobe) becomes smaller and smaller, which makes it more difficult to align the input data in response to the write command and reliably deliver it to the internal core. .

The present invention has been proposed to solve the above problems, by increasing the data alignment margin in aligning the data input in synchronization with the clock to the internal circuit can be received and processed stably at high frequency It is an object to provide a memory device.

In order to solve the above problems, the present invention is a synchronous memory device that receives a plurality of data in synchronization with the rising edge and the falling edge of the operation clock, the data strobe signal received at the timing of the data input. A first rising pulse and a first falling pulse for detecting a rising edge and a falling edge of an odd-numbered input data strobe signal, and a second rising pulse for detecting a rising edge and a falling edge of an even-numbered input data strobe signal, respectively; Data strobe buffering means for outputting a second falling pulse; First latch means for aligning first data input to the rising edge of the operation clock and second data input to the falling edge of the operation clock so as to be synchronized with the first falling pulse; Second latch means for outputting first and second aligned data realigned with the first and second data aligned to the first latching means so as to be synchronized with the second falling pulse; Third latching means for outputting third and fourth alignment data in which third data and subsequent fourth data are aligned after the second data so as to be synchronized with the second falling pulse; And a global input / output line driver for selecting and outputting the first to fourth alignment data as even data or odd data.

The present invention also provides a synchronous memory device that receives a plurality of data in synchronization with a rising edge and a falling edge of an operation clock, the data strobe signal being clocked at the timing at which the data is input. A first rising pulse and a first falling pulse for detecting a rising edge and a falling edge of an odd-numbered input data strobe signal, and a second rising pulse for detecting a rising edge and a falling edge of an even-numbered input data strobe signal, respectively; Data strobe buffering means for outputting a second falling pulse; A first rising latch for latching the first data to be synchronized with the first rising pulse; A second rising latch for relatching the first data latched by the first rising latch to be synchronized with the first falling pulse; A first falling latch for latching the second data to be synchronized with the first falling pulse; A third rising latch for re-latching the first data latched by the second rising latch and outputting the first aligned data so as to be synchronized with the second falling pulse; A second polling latch for relatching the data latched by the first polling latch and outputting the second aligned data so as to be synchronized with the second polling pulse; A fourth rising latch for latching the third data to be synchronized with the second rising pulse; A fifth rising latch which latches data latched in the fourth rising latch again and outputs the third aligned data so as to be synchronized with the second falling pulse; And a third polling latch for latching the fourth data and outputting the fourth align data so as to be synchronized with the second polling pulse. And a global input / output line driver for selecting and outputting the first to fourth alignment data as even data or odd data.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

6 is a block diagram illustrating a 4-bit prefetch data input buffer of a synchronous memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the 4-bit prefetch data input buffer of the synchronous memory device according to the present embodiment is a data strobe signal (DQS) clocked at a timing at which a plurality of data is input in synchronization with a rising edge and a falling edge of an operation clock. ) Input. Rising edges of the first rising pulse dsrp4_1 and the first falling pulse dsfp4_1 detecting the rising edge and the falling edge of the odd-numbered input data strobe signal DQS, and the rising edge of the even-numbered input data strobe signal DQS, respectively. And a rising edge of the operation clock so as to be synchronized with the data strobe buffer unit 300 for outputting the second rising pulse dsrp4_2 and the second falling pulse dsfp4_2 to detect the falling edge and the first falling pulse dsfp4_1, respectively. A first latch 210 for aligning the first data input to the second data input to the polling edge of the operation clock and the first latch 210 to be synchronized with the second polling pulse dsfp4_2. The second latch 220 outputs the first and second alignment data (align_dr0 and align_df0) in which the first and second data (rising_d1 and falling_d1) are realigned, and synchronized with the second falling pulse (dsfp4_2). Third data and fourth data input subsequent to the second data The third latch 230 outputting the third and fourth alignment data (align_dr1 and align_f1), and the first to fourth alignment data (align_dr0, align_df0, align_dr1 and align_df1) are even data (gio_ev0). and a global input / output line driver 290 for selecting and outputting the data as gio_ev1 or odd data gio_od0 and gio_od1.

In addition, the first latch 210 may include a first rising latch 211 for latching the first data to be synchronized with the first rising pulse dsrp4_1 and a first rising latch to be synchronized with the first falling pulse dsfp4_1. And a second rising latch 212 for relatching the first data latched by 211 and a first falling latch 213 for latching the second data to be synchronized with the first falling pulse dsfp4_1.

In addition, the second latch 220 latches the first data latched by the second rising latch 212 to be synchronized with the second falling pulse dsfp4_2 and outputs the first data as the first alignment data align_dr0. A second falling latch 222 which latches the data latched by the first falling latch 213 again and outputs the second aligned data align_df0 to be synchronized with the rising latch 221 and the second falling pulse dsfp4_2. ).

In addition, the third latch 230 has a fourth rising latch 231 for latching the third data to be synchronized with the second rising pulse dsrp4_2 and a fourth rising latch to be synchronized with the second falling pulse dsfp4_2. A fourth rising latch 232 which latches the data latched by the data 231 again and outputs the third alignment data align_dr1, and latches the fourth data so as to be synchronized with the second falling pulse dsfp4_2. The third polling latch 233 outputs the alignment data align_df1.

FIG. 7 is a block diagram showing the data strobe buffer shown in FIG.

Referring to FIG. 7, the data strobe buffer unit 300 has an initial operation mode set by a command decoder 310 for outputting a light pulse wtp generated by a write command and a light pulse wtp. And a data strobe divider 340 for generating and outputting the first and second rising pulses dsrp4_1 and dsrp4_2 and the first and second falling pulses dsfp4_1 and dsfp4_2 using the data strobe signal DQS. .

In addition, the data strobe buffer unit 340 shifts the light pulse wtp by an interval (WL-1) × tCK less than the light latency WL and outputs the data to the data strobe divider 340. Latency shifter 320 is further provided.

In addition, the data strobe buffer unit 340 further includes a DQS buffer unit 330 that receives the data strobe signal DQS and buffers the data strobe divider 340.

FIG. 8 is a circuit diagram illustrating an embodiment of the data strobe divider shown in FIG. 7.

Referring to FIG. 8, the data strobe divider 340 outputs a first rising pulse dsrp4_1 by sensing an initial operation setting unit 341 and an odd number of data strobe signals DQS for initial operation setting. The first pulse generator 342, the second pulse generator 343 which detects polling of the odd-numbered data strobe signal DQS and outputs the first polling pulse dsfp4_1, and the even-numbered data strobe signal ( The third pulse generator 343 detects the rising of the DQS and outputs the second rising pulse dsrp4_2, and detects the polling of the even-numbered data strobe signal DQS to output the second falling pulse dsfp4_2. A fourth pulse generator 344 is provided.

FIG. 9 is a timing diagram illustrating an operation of the data input buffer shown in FIG. 6. Hereinafter, operations of the data input buffer of the memory device according to the present embodiment will be described with reference to FIGS. 6 to 9.

First, referring to FIG. 9, the data D0 to D7 are input in synchronization with the rising edge and the falling edge of the clock CLK, and are buffered by the data buffer unit 200 to match the timing at which the data is input. The rover signal DQS is clocked and input.

The data strobe buffer unit 300 is enabled by the enable signals (endinds) generated by the write command, receives the data strobe signal DQS, and rises the rising edge and the falling edge of the odd-numbered data strobe signal DQS. The first rising pulse (dsrp4_1) and the second falling pulse (dsfp4_1) and the rising edge of the even-numbered data strobe signal (DQS) and the second rising pulse output in the pulse form respectively Generate and output a second falling pulse.

Subsequently, the first rising latch 211 latches the first data D0 and the fifth data D4 among the data output from the data buffer unit 200 by the first rising pulse dsrp4_1 to firstly latch the first data. Output as rising data (rising_d0).

Subsequently, the second rising latch 212 latches the first rising data rising_d0 again as the second rising data rising_d1 by the first falling pulse dsfp4_1, and the first falling latch 213 outputs the data buffer. The second data D1 and the sixth data D5 are latched by the first falling pulse dsfp4_1 among the data output from the unit 200 and output as latching data falling_d1.

Subsequently, the third rising latch 221 latches the second rising data rising_d1 by the second falling pulse dsfp4_2 and outputs the first rising data align_dr0, and the second falling latch 222 receives the second falling latch 222. The falling data falling_d1 is latched by the falling pulse dsfp4_2 and output as the second alignment data align_df0.

Meanwhile, the fourth rising latch 231 latches the third data D2 and the seventh data D6 among the data output from the data buffer unit 200 by the second rising pulse dsrp4_2. 2 Output as rising data (rising_d2).

Subsequently, the fifth rising latch 232 latches the second rising data rising_d2 again by the second falling pulse dsfp4_2 to output the third alignment data align_dr1, and the third falling latch 233 receives the data. The fourth data D3 and the eighth data D7 are latched among the data data output from the buffer unit 200 and output as latched fourth alignment data align_df1.

Subsequently, the global input / output line driver 290 may select the first to fourth alignment data align_dr0, align_df0, align_dr1, and align_df1 in even data (gid_ev0, gio_ev1) or odd data (gid_od0, gio_od1) in response to the internal strobe signal data_strobe. ) To the global I / O.

As shown in FIG. 9, when the internal strobe signal data_strobe is input to the global input / output line driver 290, the first to fourth alignment data (align_dr0, align_df0, align_dr1, and align_df1) are aligned and input at that time. It is delivered to the global I / O line. Therefore, the internal strobe signal (data_strobe) must be output to the global I / O line driver in the section 'Y' in order to correctly transfer the 4-bit data aligned to the global I / O line.

FIG. 10 is a timing diagram illustrating a data alignment margin of the data input buffer shown in FIG. 6. Hereinafter, the data alignment margin of the data input buffer according to the present embodiment will be described with reference to FIG. 10.

As described above, when data is input in synchronization with the rising edge and the falling edge of the operation clock, the data strobe signal DQS to be inputted together has a margin of (WL-0.25) x tCK to (WL + 0.25) x tCK. It is input. In this case, WL means write latency, and indicates the timing from when a write command is input until data is input.

Therefore, the data strobe signal DQS input at the data input timing is input with a margin of about 0.5 tCK. That is, if WL = 1, the data strobe signal (DQS) is input after 0.75 x tCK after the write command is input at a moment when the memory device operates, and 1.75 x after the write command is input at another moment. The data strobe signal DQS may be input after the tCK.

DQS1 shown in FIG. 10 represents a data strobe signal inputted after 0.75 x tCK after a write command is input, and DQS2 represents a data strobe signal DQS inputted after 1.75 x tCK after a write command is input. . Therefore, the data D0, D2, ... latched by DQS1 and the data D0, D2, ... latched by DQS2 have an interval of 0.5 x tCK.

In order for the aligned data to be correctly delivered to the global I / O line, the internal strobe signal data_stobe must be generated in the section shared by the data latched by the DQS1 and DSQ2 and input to the global I / O line driver.

As shown, the section shared by the data latched by DQS1 and DSQ2 is 0.5xtCKx3. Therefore, the internal strobe signal (data_strobe) should be output to the global I / O line driver within 0.5 × tCK × 3 period.

If the clock cycle of a memory device operating at 500 MHz is tCK = 2n, the input margin of the internal data strobe signal (data_strobe) becomes 3.0n.

This is because the margin that can be aligned by data input to the synchronous memory device in the prior art was 0.5 x tCK, and the margin that can be aligned by data input to the synchronous memory device is increased by three times according to the present invention. To indicate.

As the margin for data input and alignment increases, the memory device can reliably transfer data to the internal core. In addition, when developing a synchronous memory device that operates at a higher speed in the future, the margin for aligning the input data is sufficient, so that the current data input buffer can be used as it is.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

Since the alignment margin of the data input by the present invention can be secured three times or more than that of a conventional memory device, data can be stably input and accessed even in a high speed memory device.

Claims (8)

In the synchronous memory device receiving a plurality of data in synchronization with the rising edge and the falling edge of the operation clock, Receive a data strobe signal clocked at the timing of the data input. A first rising pulse and a first falling pulse for detecting a rising edge and a falling edge of an odd-numbered input data strobe signal, and a second rising pulse for detecting a rising edge and a falling edge of an even-numbered input data strobe signal, respectively; Data strobe buffering means for outputting a second falling pulse; First latch means for aligning first data input to the rising edge of the operation clock and second data input to the falling edge of the operation clock so as to be synchronized with the first falling pulse; Second latch means for outputting first and second aligned data realigned with the first and second data aligned to the first latching means so as to be synchronized with the second falling pulse; Third latching means for outputting third and fourth alignment data in which third data and subsequent fourth data are aligned after the second data so as to be synchronized with the second falling pulse; And Global I / O line driver for selecting and outputting the first to fourth alignment data as even data or odd data A synchronous memory device having a. The method of claim 1, The first latch means A first rising latch for latching the first data to be synchronized with the first rising pulse; A second rising latch for relatching the first data latched by the first rising latch to be synchronized with the first falling pulse; And And a first falling latch for latching the second data so as to be synchronized with the first falling pulse. The method of claim 2, The second latch means A third rising latch for re-latching the first data latched by the second rising latch and outputting the first aligned data so as to be synchronized with the second falling pulse; And And a second polling latch for re-latching the data latched by the first polling latch and outputting the second aligned data so as to be synchronized with the second polling pulse. The method of claim 1, The third latch means A first rising latch for latching the third data to be synchronized with the second rising pulse; A second rising latch which latches data latched in the first rising latch again and outputs the third aligned data to be synchronized with the second falling pulse; And And a polling latch for latching the fourth data and outputting the fourth align data so as to be synchronized with the second polling pulse. The method of claim 1, The data strobe buffering means An instruction decoder for outputting a light pulse generated by the write command; And An initial operation mode is set by the light pulse, and includes a data strobe divider for generating and outputting the first and second rising pulses and the first and second falling pulses using the data strobe signal. Synchronous memory device. The method of claim 5, The data strobe buffering means And a latency shifter for shifting the light pulses by one clock less than the light latency to output the data strobe divider to the data strobe divider. The method of claim 6, The data strobe buffering means And a data strobe buffer for receiving the data strobe signal and buffering the data strobe signal to output the data strobe divider. In the synchronous memory device receiving a plurality of data in synchronization with the rising edge and the falling edge of the operation clock, Receive a data strobe signal clocked at the timing of the data input. A first rising pulse and a first falling pulse for detecting a rising edge and a falling edge of an odd-numbered input data strobe signal, and a second rising pulse for detecting a rising edge and a falling edge of an even-numbered input data strobe signal, respectively; Data strobe buffering means for outputting a second falling pulse; A first rising latch for latching the first data to be synchronized with the first rising pulse; A second rising latch for relatching the first data latched by the first rising latch to be synchronized with the first falling pulse; A first falling latch for latching the second data to be synchronized with the first falling pulse; A third rising latch for relatching the first data latched by the second rising latch and outputting the first aligned data to be synchronized with the second falling pulse; A second polling latch for relatching the data latched by the first polling latch and outputting the second aligned data to be synchronized with the second polling pulse; A fourth rising latch for latching the third data to be synchronized with the second rising pulse; A fifth rising latch for relatching the data latched to the fourth rising latch and outputting the third aligned data to be synchronized with the second falling pulse; A third polling latch for latching the fourth data and outputting the fourth align data so as to be synchronized with the second polling pulse; And Global I / O line driver for selecting and outputting the first to fourth alignment data as even data or odd data A synchronous memory device having a.

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