KR20090103497A - Data Input Buffer - Google Patents

Abstract

PURPOSE: A data input buffer is provided to prevent generation of a data fail although overshoot or undershoot is generated in a data strobe signal after postamble. CONSTITUTION: A data input buffer includes a divider(100), a first data align part(300), and a second data align part(400). The divider receives a data strobe signal, and outputs a first pulse and a second pulse having a clock cycle. The first data align part latches and aligns an input data by the first pulse. The second data align part latches and aligns an input data by the second pulse.

Description

Data Input Buffer}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to an apparatus for preventing a reduction in data align margin during a write operation.

The semiconductor memory device has been continuously improved for the purpose of increasing the integration speed and increasing the operation speed thereof. In order to improve the operating speed, a so-called synchronous memory device capable of operating in synchronization with a clock given from a memory chip has been introduced.

The first proposal is a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one period of the clock at one data pin in synchronization with a rising edge of the clock from the outside of the memory device. However, an SDR synchronous memory device is also insufficient to satisfy the speed of a system requiring high-speed operation. Accordingly, a double data rate (DDR) synchronous memory device, which processes two data in one clock cycle, has been proposed. Each data entry / exit pin of the digital synchronous memory device continuously inputs and outputs two data in synchronization with a rising edge and a falling edge of an externally input clock. At least twice as much bandwidth as the SDR synchronous memory device can realize high-speed operation.

In such a digital memory device, since two data must be sent or received in one clock period, a prefetch method has been introduced instead of using a conventional data access method.

1 is a block diagram illustrating a data input buffer of a synchronous memory device according to the prior art.

Referring to FIG. 1, a data strobe buffer unit 10 for outputting a rising pulse dsrp and a falling pulse dsfp generated in synchronization with a rising edge and a falling edge of a data strobe signal DQS, and a data buffer unit for receiving data from the outside ( 20), a latch unit 30 for latching data data output from the data buffer unit by the rising pulse dsrp, a latch unit 40 for latching data data output from the data buffer unit by the falling pulse dsfp, and a polling pulse. and a latch unit 50 for latching and outputting the data signal latch output from the latch unit 30 by dsfp.

The latch unit 30 latches and outputs odd-numbered data, and the latch unit 40 latches and outputs even-numbered burnt data. The latch unit 50 aligns the odd-numbered data with the even-numbered data by latching and outputting the data signal latch output from the latch unit 30 by the falling pulse dsfp.

The data align_r and align_f aligned by the latch units 40 and 50 are transferred to a memory cell through a global input / output line in response to a strobe pulse (not shown).

FIG. 2 is a timing diagram illustrating an operation of the data input buffer shown in FIG. 1.

Referring to FIG. 2, the data D0 to D3 are input in synchronization with the rising edge and the falling edge of the clock CLK, and the data strobe signal DQS is input in accordance with the timing at which the data is input.

The data strobe signal DQS is normally maintained in a high impedance state and then clocked in accordance with a timing at which data is input in a preamble state in which a low level is held in advance before a clock is input. After that, the low level postamble is maintained again for a certain period of time, and then the high impedance state is maintained again.

The data strobe buffer unit 10 is enabled by an enable signal (endinds) generated by a write command, and outputs a rising pulse dsrp and a data strobe signal DQS outputted in the form of a pulse at the rising edge of the data strobe signal DQS. Generates and outputs a falling pulse dsfp that is output in the form of a falling edge pulse.

The latch unit 30 latches the first data and the third data D0 and D2 by the rising pulse dsrp and outputs the data to the data latch_r. Subsequently, the latch unit 40 latches the second data and the fourth data D1 and D3 by the falling pulse dsfp and outputs the data as the data align_f. The latch unit 50 latches the data latch_r again by the falling pulse dsfp and outputs the data latch_r as data align_r.

In the normal case, the sorted data all have a margin of 1 tCK (clock period). However, if overshoot or undershoot occurs in the data strobe signal DQS in the postamble section as shown, the margin of the third data D2 and the fourth data D3 is not sufficiently secured by this section. Bad data will be loaded on the global I / O line. As a result, data failure occurs.

The present invention provides an apparatus capable of ensuring sufficient data margin even if overshooting occurs in the data strobe signal during the postamble period by widening the period of the rising pulse and the falling pulse generated in synchronization with the pulse synchronized with the data strobe signal. For the purpose of

The data input buffer according to the present invention comprises: a divider which receives a data strobe signal and outputs a first pulse and a second pulse having two clock periods; A first data alignment unit for latching and aligning input data by the first pulse; And a second data alignment unit configured to latch and align the input data by the second pulse.

The first pulse includes a first rising pulse synchronized to the rising edge of the first pulse of the data strobe signal and a first falling pulse synchronized to the falling edge of the first pulse, wherein the second pulse is the data strobe. It is preferred to include a second rising pulse synchronized to the rising edge of the second pulse of the signal and a second falling pulse synchronized to the falling edge of the second pulse.

The first data alignment unit includes: a first latch unit configured to latch the input data by the first rising pulse; A second latch unit configured to latch the input data by the first falling pulse; And a third latch unit configured to latch the output signal of the first latch unit by the first falling pulse to align the output signal with the output data of the second latch unit.

The second data alignment unit may include a fourth latch unit configured to latch the input data by the second rising pulse; A fifth latch unit configured to latch the input data by the second falling pulse; And a sixth latch unit configured to latch the output signal of the fourth latch unit by the second falling pulse to align the output signal with the output data of the fifth latch unit.

According to the present invention, the period of the rising pulse and the falling pulse generated in synchronization with the pulse synchronized with the data strobe signal can be extended to ensure sufficient data margin even if overshooting occurs in the data strobe signal during the postamble period.

Therefore, even if an overshoot or undershoot occurs in the data strobe signal after the postamble, data failing can be prevented.

1 is a block diagram of a data input buffer according to the prior art.

2 is an operational waveform diagram of FIG.

3 is a block diagram of a data input buffer in accordance with the present invention.

4 is an operational waveform diagram of FIG.

According to the present invention, there is provided a method for ensuring sufficient data margin even if overshooting occurs during the postamble period by allowing the period of the rising pulse and the falling pulse generated in synchronization with the pulse synchronized with the data strobe signal to be two clock cycles. It starts.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of a data input buffer according to the present invention, and FIG. 4 is an operation timing diagram of the block diagram.

Referring to FIG. 3, the data input buffer includes a divider 100, a data buffer 200, a first data aligner 300, and a second data aligner.

The divider 100 is enabled by the enable signals (endinds) generated by the write command, and the falling edges and the first and second rising pulses dsrp0 and dsrp1 generated in synchronization with the rising edge of the data strobe signal DQS. The first and second polling pulses dsfp0 and dsfp1 are generated in synchronization with each other.

The data buffer 200 receives the data DQ from the outside and buffers the data DQ to output the buffered data data.

The first data aligner 300 aligns the data data in synchronization with first pulses dsrp0 and dsfp0, and the second data aligner 400 synchronizes the data with second pulses dsrp1 and dsfp1. Sort the data.

In more detail, the first data alignment unit 300 latches the data data by the first rising pulse dsrp0 and outputs the data latch_r0, and the data data by the first falling pulse dsfp0. A latch unit 320 for latching and outputting data align_f0 and a latch unit 330 for latching the data latch_r0 by the first falling pulse dsfp0 to align the data align_f0 and output the data align_r0. Similarly, the second data alignment unit 400 includes latch units 410, 420, and 430 which latch and align data data by the second rising pulse dsrp1 and the second falling pulse dsfp1.

4, the data strobe signal DQS is divided into first pulses dsrp0 and dsfp0 and second pulses dsrp1 and dsfp1 through the divider 100. At this time, the first pulse and the second pulse has a clock cycle twice that of the prior art, that is, 2 tCK.

The first data D0 is latched by the latch unit 310 by the first rising pulse dsrp0 of the first pulse, and the second data D1 is latched by the latch unit 320 by the first falling pulse dsfp0 of the first pulse. . The first data D0 is again latched by the latch unit 330 by the first polling pulse dsfp0 and aligned with the second data D1. At this time, even if overshoot and undershoot occur in the postamble period of the data strobe signal DQS, the data D0 and D1 have a 1.5tCK + tOS margin, thereby preventing data from being distorted. Even if the data strobe signal DQS has a minimum tDQSS (the time from when the write command is input until the first rising edge of DQS occurs) (tDQSSmin), it has enough time margin of 1tCK + tOS.

Similarly, the third data D2 is latched in the latch unit 410 by the second rising pulse dsrp1 of the second pulse and the fourth data D3 latched in the latch unit 420 by the second falling pulse dsfp1 of the second pulse. . The third data D2 is again latched by the latch unit 430 by the second falling pulse to align with the fourth data D3. At this time, since the data D2 and D3 aligned by the second pulse are not affected by the overshoot and undershoot of the data strobe signal DQS, a timing margin of 2tCK is secured.

Claims (4)

A divider which receives a data strobe signal and outputs a first pulse and a second pulse having two clock periods; A first data alignment unit for latching and aligning input data by the first pulse; And And a second data alignment unit configured to latch and align the input data by the second pulse. The method of claim 1, The first pulse comprises a first rising pulse synchronized to the rising edge of the first pulse of the data strobe signal and a first falling pulse synchronized to the falling edge of the first pulse, The second pulse comprises a second rising pulse synchronized to the rising edge of a second pulse of the data strobe signal and a second falling pulse synchronized to the falling edge of the second pulse. The method of claim 2, The first data alignment unit includes: a first latch unit configured to latch the input data by the first rising pulse; A second latch unit configured to latch the input data by the first falling pulse; And And a third latch unit configured to latch the output signal of the first latch unit by the first falling pulse to align the output signal with the output data of the second latch unit. The method of claim 2, The second data alignment unit may include a fourth latch unit configured to latch the input data by the second rising pulse; A fifth latch unit configured to latch the input data by the second falling pulse; And And a sixth latch unit configured to latch the output signal of the fourth latch unit by the second falling pulse to align the output signal with the output data of the fifth latch unit.