KR100911898B1 - Method of forming plug for semiconductor device - Google Patents
Method of forming plug for semiconductor device Download PDFInfo
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- KR100911898B1 KR100911898B1 KR1020020084315A KR20020084315A KR100911898B1 KR 100911898 B1 KR100911898 B1 KR 100911898B1 KR 1020020084315 A KR1020020084315 A KR 1020020084315A KR 20020084315 A KR20020084315 A KR 20020084315A KR 100911898 B1 KR100911898 B1 KR 100911898B1
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000011229 interlayer Substances 0.000 claims abstract description 38
- 238000005468 ion implantation Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 13
- -1 silicon ions Chemical class 0.000 claims abstract description 11
- 239000000126 substance Substances 0.000 claims abstract description 9
- 238000007517 polishing process Methods 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 2
- 238000005498 polishing Methods 0.000 abstract description 19
- 239000013077 target material Substances 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Abstract
본 발명은 CMP 공정시 CMP 타겟인 폴리실리콘막과 피 CMP 구성물질인 층간절연막 및 하드 마스크 사이의 연마율 차이를 최소화하여 디싱발생을 방지할 수 있는 반도체 소자의 플러그 형성방법을 제공한다.The present invention provides a method of forming a plug of a semiconductor device which can prevent dishing by minimizing a difference in polishing rate between a polysilicon film, which is a CMP target, an interlayer insulating film, and a hard mask, which are CMP target materials, during a CMP process.
본 발명은 상부에 게이트 및 하드 마스크가 순차적으로 적층된 게이트 적층구조가 형성되고 상기 게이트 적층구조 측벽에 스페이서가 형성된 반도체 기판을 준비하는 단계; 상기 반도체기판의 전면 상에 층간절연막을 형성하는 단계; 상기 반도체기판의 일부가 노출되도록 층간절연막을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀에 매립되도록 상기 층간절연막 상에 폴리실리콘막을 형성하는 단계; 상기 하드 마스크 및 층간절연막까지 주입되도록 상기 반도체기판의 전면에 실리콘이온을 이온주입하는 단계; 및 상기 폴리실리콘막, 층간절연막 및 하드마스크를 화학기계연마 공정으로 전면식각하여 서로 분리된 플러그를 형성하는 단계를 포함하는 반도체 소자의 플러그 형성방법에 의해 달성될 수 있다.The present invention provides a method of manufacturing a semiconductor substrate, the method comprising: preparing a semiconductor substrate having a gate stacked structure in which gates and hard masks are sequentially stacked on top of each other, and spacers formed on sidewalls of the gate stacked structure; Forming an interlayer insulating film on an entire surface of the semiconductor substrate; Etching the interlayer insulating layer to expose a portion of the semiconductor substrate to form a contact hole; Forming a polysilicon film on the interlayer insulating film so as to fill the contact hole; Implanting silicon ions into the entire surface of the semiconductor substrate so as to inject the hard mask and the interlayer insulating film; And etching the entire surface of the polysilicon layer, the interlayer insulating layer, and the hard mask by a chemical mechanical polishing process to form plugs separated from each other.
LP, 셀프-실리콘 이온주입, 하드 마스크, BPSG막, CMPLP, self-silicon ion implantation, hard mask, BPSG film, CMP
Description
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 랜딩 플러그 형성방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a method of forming a landing plug of a semiconductor device in accordance with an embodiment of the present invention.
도 2는 셀프-실리콘 이온주입공정을 실시하지 않은 종래의 피 CMP 구성물질의 연마율 및 연마선택비 차이를 나타낸 그래프.Figure 2 is a graph showing the difference in polishing rate and polishing selectivity of the conventional CMP constituent material without the self-silicon ion implantation process.
도 3은 셀프-실리콘 이온주입공정을 실시한 본 발명의 피 CMP 구성물질의 연마율 및 선택비 차이를 나타낸 그래프.Figure 3 is a graph showing the difference in polishing rate and selectivity of the CMP component of the present invention subjected to a self-silicon ion implantation process.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11 : 소자분리막10 semiconductor substrate 11 device isolation film
12A : 폴리실리콘막 12B : 금속막12A:
12 : 게이트 13 : 하드 마스크12
14 : 스페이서 15 : 층간절연막14
16 : 랜딩플러그 폴리실리콘막16: landing plug polysilicon film
16A : 랜딩 플러그 17 : 실리콘이온16A: landing plug 17: silicon ion
100 : 게이트 적층구조100: gate laminated structure
본 발명은 반도체 소자의 플러그 형성방법에 관한 것으로, 특히 화학기계연마 공정을 적용한 반도체 소자의 랜딩 플러그 형성방법에 관한 것이다.The present invention relates to a method for forming a plug of a semiconductor device, and more particularly to a method for forming a landing plug of a semiconductor device using a chemical mechanical polishing process.
반도체 소자의 고집적화에 따른 패턴의 미세화로 인하여 비트라인 또는 캐패시터의 소토리지 노드 전극 등의 콘택을 질화막과 산화막의 식각선택비를 이용하는 자기정렬콘택(self-aligned contact; SAC) 공정을 적용하여 형성하는 것이 필수적이다. 또한, 최근에는 콘택공정시 공정마진을 더욱 증가시키기 위하여 콘택영역에 일종의 콘택 패드인 랜딩플러그(Landing Plug; LP)를 동시에 적용하고 있다.Due to the miniaturization of the pattern due to the high integration of the semiconductor device, a contact such as a storage node electrode of a bit line or a capacitor is formed by applying a self-aligned contact (SAC) process using an etching selectivity of a nitride film and an oxide film. It is essential. In recent years, a landing plug (LP), which is a kind of contact pad, is simultaneously applied to the contact region in order to further increase the process margin during the contact process.
이러한 랜딩 플러그는 일반적으로 SAC 공정에 의해 형성된 콘택홀에 랜딩플러그폴리실리콘(Landing Plug Polysilicon; LPP)막을 매립한 후, 화학기계연마 (Chemical Mechancial Polishing; CMP) 공정에 의해 LPP막을 전면식각하여 서로 분리시켜 형성한다.Such landing plugs are generally embedded with a Landing Plug Polysilicon (LPP) film in a contact hole formed by a SAC process, and then separated from each other by full etching of the LPP film by a chemical mechanical polishing (CMP) process. To form.
한편, CMP 공정시에는 LP의 완전한 분리를 위하여 CMP 타겟인 LPP막 뿐만 아니라 LP와 게이트 사이를 절연하는 BPSG막과 게이트 하드 마스크 및 게이트 실링(sealing) 등의 질화막과 같은 피 CMP 구성물질을 동시에 연마하여야 한다. 이에 따라, LPP막과 피 CMP 구성물질 사이의 심한 연마율 차이로 인하여 LPP막과 BPSG막에 결함(defect)이 유발된다. 즉, 질화막에 비해 매우 빠른 LPP막과 BPSG막의 연마율로 인하여 디싱(dishing)이 유발되고 이 디싱에 연마 잔유물 등이 잔류함 으로써 결함을 유발하게 된다. 이러한 결함은 결국 후속 비트라인간 브리지 및 셀 간 브리지를 유발하여 소자의 신뢰성을 저하시키게 된다. 이를 해결하기 위하여 CMP 공정에 의한 LP 형성 후 세정공정을 실시하고 있으나, 이 경우 결함은 다소 감소되지만 디싱이 더욱 심화되어 후속 비트라인과의 절연을 위한 절연물질 증착시 갭매립(gap-fill) 문제를 야기시키기 때문에 효과적이지 못하다.
On the other hand, in the CMP process, for the complete separation of LP, the CMP target material is polished at the same time as the CMP target LPP film, as well as the BPSG film which insulates the LP and the gate, and the nitride CMP material such as gate hard mask and gate sealing. shall. This causes defects in the LPP film and the BPSG film due to the severe difference in polishing rate between the LPP film and the CMP component. That is, dishing is caused by the polishing rate of the LPP film and the BPSG film which is much faster than that of the nitride film, and polishing residues remain in the dish, causing defects. These defects eventually lead to subsequent inter-bit-line and inter-cell bridges, which degrades device reliability. To solve this problem, cleaning process is performed after LP formation by CMP process. In this case, defects are somewhat reduced, but dishing is intensified, so gap-fill problem occurs when depositing insulation material for insulation from subsequent bit lines. It is not effective because it causes.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, CMP 공정시 CMP 타겟인 폴리실리콘막과 피 CMP 구성물질인 층간절연막 및 하드 마스크 사이의 연마율 차이를 최소화하여 디싱발생을 방지할 수 있는 반도체 소자의 플러그 형성방법을 제공하는데 그 목적이 있다.
The present invention is proposed to solve the problems of the prior art as described above, and prevents dishing by minimizing the difference in polishing rate between the polysilicon film, which is a CMP target, the interlayer insulating film, and the hard mask, which are CMP target materials, during the CMP process. It is an object of the present invention to provide a method for forming a plug of a semiconductor device.
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 상부에 게이트 및 하드 마스크가 순차적으로 적층된 게이트 적층구조가 형성되고 상기 게이트 적층구조 측벽에 스페이서가 형성된 반도체 기판을 준비하는 단계; 상기 반도체기판의 전면 상에 층간절연막을 형성하는 단계; 상기 반도체기판의 일부가 노출되도록 층간절연막을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀에 매립되도록 상기 층간절연막 상에 폴리실리콘막을 형성하는 단계; 상기 하드 마스크 및 층간절연막까지 주입되도록 상기 반도체기판의 전면에 실리콘이온을 이온주입하는 단계; 및 상기 폴리실리콘막, 층간절연막 및 하드마스크를 화학기계연마 공정으로 전면식각하여 서로 분리된 플러그를 형성하는 단계를 포함하는 반도체 소자의 플러그 형성방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is a semiconductor semiconductor layer formed with a gate stacked structure in which a gate and a hard mask is sequentially stacked on top and a spacer formed on the side wall of the gate stacked structure Preparing a substrate; Forming an interlayer insulating film on an entire surface of the semiconductor substrate; Etching the interlayer insulating layer to expose a portion of the semiconductor substrate to form a contact hole; Forming a polysilicon film on the interlayer insulating film so as to fill the contact hole; Implanting silicon ions into the entire surface of the semiconductor substrate so as to inject the hard mask and the interlayer insulating film; And etching the entire surface of the polysilicon layer, the interlayer insulating layer, and the hard mask by a chemical mechanical polishing process to form plugs separated from each other.
바람직하게, 상기 실리콘이온을 이온주입하는 단계는, 블랭킷 방식에 의한 실리콘-셀프 이온주입공정으로 수행하는 것을 실시하는데, 이때 이온주입공정은 30 내지 150KeV의 에너지와 1E10 내지 1E16의 도우즈로 0 내지 45도의 경사, 0 내지 180도의 꼬임 및 0 내지 4회의 회전을 부가하여 실시한다. 또한, 하드 마스크는 질화막으로 이루어지고, 층간절연막은 BPSG막으로 이루어진다.Preferably, the ion implantation of the silicon ions is carried out by a silicon-self ion implantation process by a blanket method, wherein the ion implantation process is 0 to a energy of 30 to 150 KeV and a dose of 1E10 to 1E16. It is carried out by adding a 45 degree inclination, a twist of 0 to 180 degrees and 0 to 4 rotations. The hard mask is made of a nitride film, and the interlayer insulating film is made of a BPSG film.
또한, 상기의 기술적 과제를 달성하기 위한 본 발명의 다른 측면에 따르면, 상기의 본 발명의 목적은 상부에 게이트 및 하드 마스크가 순차적으로 적층된 게이트 적층구조가 형성되고 상기 게이트 적층구조 측벽에 스페이서가 형성된 반도체 기판을 준비하는 단계; 상기 반도체기판의 전면 상에 층간절연막을 형성하는 단계; 상기 반도체기판의 일부가 노출되도록 층간절연막을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀에 매립되도록 상기 층간절연막 상에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막을 제 1 화학기계연마 공정으로 전면식각하는 단계; 상기 층간절연막과 하드 마스크까지 주입되도록 상기 반도체기판의 전면에 실리콘이온을 이온주입하는 단계; 및 상기 폴리실리콘막, 층간절연막 및 하드마스크를 제 2 화학기계연마 공정으로 전면식각하여 서로 분리된 플러그를 형성하는 단계를 포함하는 반도체 소자의 플러그 형성방법에 의해 달성될 수 있다.In addition, according to another aspect of the present invention for achieving the above technical problem, an object of the present invention is a gate stacked structure in which a gate and a hard mask is sequentially stacked on the top and a spacer is formed on the sidewall of the gate stacked structure Preparing a formed semiconductor substrate; Forming an interlayer insulating film on an entire surface of the semiconductor substrate; Etching the interlayer insulating layer to expose a portion of the semiconductor substrate to form a contact hole; Forming a polysilicon film on the interlayer insulating film so as to fill the contact hole; Etching the polysilicon film over the first chemical mechanical polishing process; Implanting ions of silicon into the entire surface of the semiconductor substrate to implant the interlayer insulating layer and the hard mask; And forming a plug separated from each other by etching the polysilicon layer, the interlayer insulating layer, and the hard mask by a second chemical mechanical polishing process, to form plugs separated from each other.
바람직하게, 상기 실리콘이온을 이온주입하는 단계는 블랭킷 방식에 의한 실리콘-셀프 이온주입공정으로 수행하는데, 이때 이온주입공정은 0.5 내지 50KeV의 에너지와 1E13 내지 1E16의 도우즈로 0 내지 45도의 경사, 0 내지 180도의 꼬임 및 0 내지 4회의 회전을 부가하여 실시한다. 또한, 하드 마스크는 질화막으로 이루어지고, 층간절연막은 BPSG막으로 이루어진다.Preferably, the ion implantation of the silicon ion is carried out by a silicon-self ion implantation process by a blanket method, wherein the ion implantation process is inclined at 0 to 45 degrees with an energy of 0.5 to 50 KeV and a dose of 1E13 to 1E16, This is done by adding a twist of 0 to 180 degrees and 0 to 4 rotations. The hard mask is made of a nitride film, and the interlayer insulating film is made of a BPSG film.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 랜딩 플러그 형성방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a landing plug of a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 소자분리막(11)이 형성된 반도체 기판(10) 상에 게이트 절연막(미도시)을 형성하고, 게이트 절연막 상에 폴리실리콘막(12A)과 금속막(12B)의 이중막으로 이루어진 게이트(12)와, 질화막으로 이루어진 하드 마스크(13)가 순차적으로 적층된 게이트 적층구조(100)를 형성한다. 그 다음, 게이트 적층구조(100) 측벽에 질화막으로 이루어진 스페이서(14)를 형성하고, 기판 전면 상에 BPSG막으로 이루어진 층간절연막(15)을 형성한다. 그 후, 기판(10)의 일부가 노출되도록 SAC 공정으로 층간절연막(15)을 식각하여 LP용 콘택홀을 형성한 다음, 콘택홀에 매립되도록 층간절연막(15) 상에 LPP막(16)을 형성한다.Referring to FIG. 1A, a gate insulating film (not shown) is formed on the
도 1b를 참조하면, 실리콘-셀프(Si-Self) 이온주입공정으로 하드 마스크(13)까지 주입되도록 LPP막(16)이 형성된 기판 전면으로 실리콘 이온(17)을 마스크 없이 블랭킷(blanket) 방식으로 이온주입하여 각 막들의 실리콘 함량을 증가시킨다. 바람직하게, 이온주입공정은 30 내지 150KeV의 에너지와 1E10 내지 1E16의 도우즈(dose)로 실시하며, 더욱 바람직하게는 0 내지 45도의 경사(tilt), 0 내지 180도의 꼬임(twist) 및 0 내지 4회의 회전(rotation)을 부가하여 실시한다.
Referring to FIG. 1B, the
도 1c를 참조하면, LPP막(16)이 분리되도록 LPP막(16)을 타겟으로 하여 CMP 공정으로 LPP막(16), 층간절연막(15) 및 하드 마스크(13)을 전면식각하여 서로 분리된 LP(16A)를 형성한다. 이때, 상기 실리콘-셀프 이온주입공정에 의해 증가된 실리콘 함량에 의해, 층간절연막(15)의 연마율은 감소하고 하드 마스크(13)의 연마율을 증가게 되어 CMP 타겟인 LPP막과 피 CMP 구성물 사이의 연마율이 감소됨으로써, CMP 공정 후 종래와 같은 디싱이 발생되지 않게 된다.Referring to FIG. 1C, the
도 2 및 도 3은 실리콘-셀프 이온주입공정을 실시하지 않은 종래의 경우와 실리콘-셀프 이온주입공정을 실시한 본 발명의 경우에 대하여 각각 피 CMP 구성물질의 연마율 및 선택비 차이를 나타낸 그래프로서, 도 2 및 도 3에 나타낸 바와 같이, 종래에는 피 CMP 구성물질인 BPSG막 및 질화막 사이에 약 800% 정도의 연마율 차이가 발생되고 연마선택비도 BPSG막은 1.5로 높은 반면 질화막은 0.2로 매우 낮았으나, 본 발명의 경우 BPSG막 및 질화막의 증가된 실리콘 함량에 의해 이들 사이의 연마율이 현저하게 감소되고 연마선택비도 BPSG막은 1.14 정도이고 질화막은 0.92정도로서 큰 차이가 발생되지 않음을 알 수 있다.2 and 3 are graphs showing differences in polishing rate and selectivity of the CMP constituents, respectively, in the case of the conventional case in which the silicon-self ion implantation process is not performed and the case of the present invention in which the silicon-self ion implantation process is performed. As shown in FIGS. 2 and 3, a difference in polishing rate of about 800% occurs between the BPSG film and the nitride film, which is a CMP component, and the polishing selectivity is very low at 0.2 while the BPSG film is high at 1.5. However, in the case of the present invention, the increased silicon content of the BPSG film and the nitride film significantly reduced the polishing rate therebetween, and the polishing selectivity was about 1.14 for the BPSG film and 0.92 for the nitride film.
그 후, 도시되지는 않았지만, 소정의 열처리 공정을 수행하여 주입된 실리콘이온을 복구(recovery)시킨다. 여기서, 열처리 공정은 별도의 노 어닐링(furnace annealing)이나 급속열처리(Rapid Thermal Process; RTP)로 수행하거나, CMP 공정 후에 소오스/드레인 열처리를 수행하여 별도의 열처리 공정 추가를 배제할 수도 있다. 여기서, 별도의 열처리를 부가하는 경우에, 노 어닐링은 400 내지 1000℃의 온도에서 NH3, Ar, N2, N2O 등을 사용하여 승온 및 냉각속도를 5℃/분 내지 25℃/분으로 조절하면서 5분 내지 6시간 동안 수행하고, RTP는 500 내지 1100℃의 온도에서 NH3, Ar, N2, N2O 등을 사용하여 승온 및 냉각속도를 15℃/분 내지 100℃/분으로 조절하면서 5 내지 1000초 동안 수행한다.Thereafter, although not shown, a predetermined heat treatment process is performed to recover the implanted silicon ions. In this case, the heat treatment process may be performed by a separate furnace annealing or rapid thermal process (RTP), or by performing a source / drain heat treatment after the CMP process, thereby eliminating the additional heat treatment process. Here, in the case of adding a separate heat treatment, the furnace annealing is performed using NH 3 , Ar, N 2 , N 2 O or the like at a temperature of 400 to 1000 ° C. to increase the temperature and the cooling rate from 5 ° C./min to 25 ° C./min. 5 minutes to 6 hours while adjusting to, RTP using NH 3 , Ar, N 2 , N 2 O and the like at a temperature of 500 to 1100 ℃ temperature and
상기 실시예에 의하면, CMP에 의한 LP 형성을 수행하기 전에 실리콘-셀프 이온주입공정으로 실리콘 이온을 블랭킷 이온주입하여 피 CMP 구성물질인 층간절연막과 질화막의 실리콘 함량을 높여 CMP 공정시 CMP 타겟과의 연마율 및 연마선택비 차이를 최소화함으로써, CMP 공정후 디싱 발생을 효과적으로 방지할 수 있게 된다. 이에 따라, 디싱으로 인한 결함발생을 방지할 수 있고, 그 결과 후속 비트라인간 브리지 및 셀간 브리지도 방지할 수 있게 됨으로써 소자의 신뢰성을 향상시킬 수 있게 된다.According to the above embodiment, a blanket ion is implanted by a silicon-self ion implantation process before the formation of LP by CMP, thereby increasing the silicon content of the interlayer insulating layer and the nitride film, which is the CMP material, to be combined with the CMP target during the CMP process. By minimizing the difference in polishing rate and polishing selection ratio, dishing after the CMP process can be effectively prevented. As a result, defects due to dishing can be prevented, and as a result, subsequent inter-bitline bridges and inter-cell bridges can be prevented, thereby improving device reliability.
한편, 상기 실시예에서는 실리콘-셀프 이온주입공정 후에만 CMP 공정을 수행하여 LP를 형성하였지만, 이와 달리 실리콘-셀프 이온주입공정 전에 CMP 공정을 더 적용하여 LPP막(16)을 소정 두께만큼 감소시킨 후 실리콘-셀프 이온주입공정을 수행할 수도 있는데, 이 경우에는 이온주입공정을 0.5 내지 50KeV의 에너지와 1E13 내지 1E16의 도우즈(dose)로 실시하며, 바람직하게는 0 내지 45도의 경사(tilt), 0 내지 180도의 꼬임(twist) 및 0 내지 4회의 회전(rotation)을 부가하여 실시한다.On the other hand, in the above embodiment, the LP was formed by performing the CMP process only after the silicon-self ion implantation process. Alternatively, the CMP process was further applied before the silicon-self ion implantation process to reduce the
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치 환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.
전술한 본 발명은 CMP에 의한 LP 형성을 수행하기 전에 실리콘-셀프 이온주입공정으로 실리콘 이온을 블랭킷 이온주입하는 것에 의해 CMP 공정후 디싱 발생을 효과적으로 방지하여 디싱으로 인한 결함발생을 방지함으로써 소자의 신뢰성을 향상시킬 수 있다.The present invention described above effectively prevents dishing after the CMP process by blanketing the silicon ions by the silicon-self ion implantation process before performing the LP formation by the CMP, thereby preventing defects due to dishing. Can improve.
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| US5885899A (en) * | 1995-11-14 | 1999-03-23 | International Business Machines Corporation | Method of chemically mechanically polishing an electronic component using a non-selective ammonium hydroxide slurry |
| KR20010008623A (en) * | 1999-07-02 | 2001-02-05 | 김영환 | Method for forming bit-line of a semiconductor device |
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| US5885899A (en) * | 1995-11-14 | 1999-03-23 | International Business Machines Corporation | Method of chemically mechanically polishing an electronic component using a non-selective ammonium hydroxide slurry |
| KR20010008623A (en) * | 1999-07-02 | 2001-02-05 | 김영환 | Method for forming bit-line of a semiconductor device |
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