KR100904828B1 - Image Sensor and Method for Manufacturing thereof - Google Patents

Abstract

The image sensor according to the embodiment includes a circuit (circuitry) formed on the substrate; First and second plugs having different heights formed on the substrate; First and second lower electrodes respectively formed on the first plug and the second plug; And a photodiode formed on the first lower electrode and the second lower electrode.

Image sensor, photodiode, crosstalk

Description

Image sensor and method for manufacturing

Embodiments relate to an image sensor and a manufacturing method thereof.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is mainly a charge coupled device (CCD) image sensor and a CMOS (Complementary Metal Oxide Silicon) It is divided into an image sensor (CIS).

On the other hand, the CCD image sensor has a complex driving method, a large power consumption, and requires a multi-stage photo process, so that the manufacturing process is complicated. CMOS image sensors are getting attention.

The CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor according to the related art may be divided into a photo diode region (not shown) for receiving a light signal and converting the light signal into an electrical signal, and a transistor region (not shown) for processing the electrical signal.

However, the CMOS image sensor according to the related art has a structure in which a photodiode is horizontally disposed with a transistor.

Of course, although the disadvantages of the CCD image sensor are solved by the horizontal CMOS image sensor according to the prior art, there are still problems in the horizontal CMOS image sensor according to the prior art.

That is, according to the horizontal CMOS image sensor of the prior art, a photodiode and a transistor are manufactured to be adjacent to each other horizontally on a substrate. Accordingly, an additional area for the photodiode is required, thereby reducing the fill factor area and limiting the possibility of resolution.

In addition, according to the related art, there is a problem in that crosstalk occurs in which electrons generated in one pixel enter another pixel.

In addition, according to the horizontal CMOS image sensor according to the prior art there is a problem that it is very difficult to achieve optimization for the process of manufacturing the photodiode and the transistor at the same time. That is, in a fast transistor process, a shallow junction is required for low sheet resistance, but such shallow junction may not be appropriate for a photodiode.

In addition, according to the horizontal CMOS image sensor according to the prior art, the size of the unit pixel is increased to maintain the sensor sensitivity of the image sensor as additional on-chip functions are added to the image sensor. The area for the photodiode must be reduced to maintain the pixel size. However, when the pixel size is increased, the resolution of the image sensor is reduced, and when the area of the photodiode is reduced, the sensor sensitivity of the image sensor is reduced.

Embodiments provide an image sensor and a method of manufacturing the same that can provide a new integration of a circuit and a photodiode.

In addition, the embodiment is to provide an image sensor and a method of manufacturing the same that can be improved with the resolution (Resolution) and sensor sensitivity (sensitivity).

In addition, an embodiment is to provide an image sensor and a method of manufacturing the same that can prevent crosstalk while employing a vertical photodiode.

In addition, the embodiment is to provide an image sensor and a manufacturing method thereof that can prevent the defect in the photodiode while employing a vertical photodiode.

The image sensor according to the embodiment includes a circuit (circuitry) formed on the substrate; First and second plugs having different heights formed on the substrate; First and second lower electrodes respectively formed on the first plug and the second plug; And a photodiode formed on the first lower electrode and the second lower electrode.

In addition, the manufacturing method of the image sensor according to the embodiment comprises the steps of forming a circuit (circuitry) on the substrate; Forming a first plug and a second plug having different heights on the substrate; Forming a first lower electrode and a second lower electrode on the first plug and the second plug, respectively; And forming a photodiode on the first lower electrode and the second lower electrode.

According to the image sensor and the manufacturing method thereof according to the embodiment, it is possible to provide a vertical integration of the circuit (circuitry) and the photodiode.

In addition, according to the embodiment, the fill factor may be approached to 100% by vertical integration of the circuit and the photodiode.

In addition, according to the embodiment, it is possible to prevent crosstalk by changing the height of the photodiode according to the pixel.

Further, according to the embodiment, it is possible to provide higher sensitivity at the same pixel size by vertical integration than in the prior art.

In addition, according to the embodiment it is possible to reduce the process cost for the same resolution (Resolution) than the prior art.

In addition, according to the exemplary embodiment, each unit pixel may implement a more complicated circuit without reducing the sensitivity.

In addition, the additional on-chip circuitry that can be integrated by the embodiment can increase the performance of the image sensor and further reduce the size and manufacturing cost of the device.

Further, according to the embodiment, it is possible to prevent defects in the photodiode while employing a vertical photodiode.

Hereinafter, an image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

In the description of the embodiment will be described with reference to the structure of the CMOS image sensor (CIS), the present invention is not limited to the CMOS image sensor, it is applicable to all image sensors, such as CCD image sensor.

(Example)

1 is a cross-sectional view of an image sensor according to an embodiment.

The image sensor according to the embodiment includes a circuit (circuitry) formed on the substrate 110; First and second plugs 151 and 152 having different heights formed on the substrate 110; A first lower electrode 161 and a second lower electrode 162 formed on the first plug 151 and the second plug 152, respectively; And a photodiode 170 formed on the first lower electrode 161 and the second lower electrode 162.

The circuit may include a transistor 120, a first ion implantation region 131, and a second ion implantation region 133.

The first plug 151 is formed on the first interlayer insulating layer 141, and the second plug 152 is formed on the second interlayer insulating layer 142 to have different heights. Accordingly, the heights of the first lower electrode 161 and the second lower electrode 162 are changed.

In addition, the heights of the photodiode formed on the first lower electrode 161 and the photodiode formed on the second lower electrode 162 are different. Accordingly, according to the exemplary embodiment, crosstalk can be prevented by lowering the probability that electrons generated in the first pixel move to the lower electrode of the second pixel that is the adjacent pixel by changing the height of the photodiode according to the pixel.

The photodiode 170 in the embodiment may include a first conductivity type conductive layer 171, an intrinsic layer 173, and a second conductivity type conductive layer 175.

An embodiment may further include a planarization layer 180 formed on the photodiode 170, and may include a color filter layer 190.

In addition, the embodiment may form an upper electrode (not shown) on the photodiode 170, the upper electrode may be formed by a transparent electrode.

Hereinafter, a manufacturing method of an image sensor according to an embodiment will be described with reference to FIGS. 2 to 7.

First, as shown in FIG. 2, a circuit is formed on the substrate 110. For example, the transistor 120 may be formed on the substrate 110, and the first ion implantation region 131 and the second ion implantation region 133 may be formed on both sides of the transistor 120 by ion implantation. have. The first ion implantation region 131 may serve to store and transfer electrons generated by the photodiode as a high concentration N-type ion implantation region (N +). The second ion implantation region 133 may serve as a floating diffusion region FD as the high concentration N type ion implantation region N +, but is not limited thereto.

Thereafter, a first interlayer insulating layer 141 is formed on the substrate 110 on which the circuit is formed, and the first interlayer insulating layer 141 is selectively etched to form a first plug 151. Before forming the first plug 151, the first metal M1, the second metal M2, and the like may be formed.

Thereafter, a second interlayer insulating layer 142 is formed on the first interlayer insulating layer 141 on which the first plug 151 is formed.

Thereafter, the second interlayer insulating layer 142 corresponding to the second pixel is selectively etched to form a second plug 152 connected to the first plug 151 after the trench (not shown). A third metal M3 may be further formed between the first plug 151 and the second plug 152.

Thereafter, a photosensitive film pattern 210 exposing the second interlayer insulating layer 142 corresponding to the first pixel is formed on the second interlayer insulating layer 142.

Next, as shown in FIG. 3, the second interlayer insulating layer 142 is selectively etched using the photoresist pattern 210 as an etching mask to expose the first plug 151 corresponding to the first pixel. The first pixel may be a pixel corresponding to the green color, but is not limited thereto.

Next, as shown in FIG. 4, the photoresist layer pattern 210 is removed, and the first lower electrode 161 and the second lower electrode 162 are respectively disposed on the first plug 151 and the second plug 152. Form. For example, the lower electrode metal (not shown) may be formed on the entire surface, and then selectively etched to form the first lower electrode 161 and the second lower electrode 162. The first and second lower electrodes 161 and 162 may be formed of various conductive materials including metals, alloys, or silicides. For example, it can form with aluminum, copper, cobalt, titanium.

Next, as shown in FIG. 5, a photodiode 170 is formed on the first lower electrode 161 and the second lower electrode 162.

The photodiode 170 may include a first conductivity type conductive layer 171, an intrinsic layer 173, and a second conductivity type conductive layer 175.

First, a first conductive type conductive layer 171 is formed on the first and second lower electrodes 161 and 162. In some cases, the first conductive type conductive layer 171 may not be formed, and subsequent processes may be performed. The first conductivity type conductive layer 171 may serve as the N layer of the PIN diode employed in the embodiment. That is, the first conductivity type conductive layer 171 may be an N type conductivity type conductive layer, but is not limited thereto.

The first conductivity type conductive layer 171 may be formed using N-doped amorphous silicon, but is not limited thereto. That is, the first conductivity type conductive layer 171 is a-Si: H, a-SiGe: H, a-SiC, a-SiN: H a-SiO by adding germanium, carbon, nitrogen or oxygen to amorphous silicon. : H may be formed.

The first conductivity type conductive layer 171 may be formed by chemical vapor deposition (CVD), in particular, PECVD. For example, the first conductivity type conductive layer 171 may be formed of amorphous silicon by PECVD by mixing PH ₃ , P ₂ H _5, and the like with silane gas (SiH ₄ ).

Next, an intrinsic layer 173 is formed on the first conductivity type conductive layer 171. The intrinsic layer 173 may serve as the I layer of the PIN diode employed in the embodiment. The intrinsic layer 173 may be formed using n-doped amorphous silicon. The intrinsic layer 173 may be formed by chemical vapor deposition (CVD), in particular, PECVD. For example, the intrinsic layer 173 may be formed of amorphous silicon by PECVD using silane gas (SiH ₄ ).

Thereafter, a second conductivity type conductive layer 175 is formed on the intrinsic layer 173. The second conductivity type conductive layer 175 may be formed in a continuous process with the formation of the intrinsic layer 173. The second conductivity type conductive layer 175 may serve as the P layer of the PIN diode employed in the embodiment. That is, the second conductivity type conductive layer 175 may be a P type conductivity type conductive layer, but is not limited thereto.

The second conductivity type conductive layer 175 may be formed using P-doped amorphous silicon, but is not limited thereto. The second conductivity type conductive layer 175 may be formed by chemical vapor deposition (CVD), in particular, PECVD. For example, the second conductivity type conductive layer 175 may be formed of amorphous silicon by PECVD by mixing boron or the like with silane gas (SiH ₄ ).

Next, as shown in FIG. 6, the method may further include forming the planarization layer 180 on the photodiode 170. For example, the planarization layer 180 may be formed of an insulating layer or the like to serve as the planarization layer PL for the color filter layer 190 formed thereafter.

In an embodiment, an upper electrode (not shown) may be further formed on the photodiode 170. The upper electrode may be formed of a transparent electrode having high light transmittance and high conductivity. For example, the transparent electrode may be formed of indium tin oxide (ITO) or cardium tin oxide (CTO).

Next, as shown in FIG. 7, the color filter layer 190 may be further formed on the planarization layer 180.

According to the image sensor and the method of manufacturing the same according to the embodiment, the fill factor can be approximated to 100% by vertical integration of the circuit and the photodiode.

In addition, according to the embodiment, it is possible to prevent crosstalk by changing the height of the photodiode according to the pixel.

Further, according to the embodiment, it is possible to provide higher sensitivity at the same pixel size by vertical integration than in the prior art.

In addition, according to the embodiment it is possible to reduce the process cost for the same resolution (Resolution) than the prior art.

In addition, according to the exemplary embodiment, each unit pixel may implement a more complicated circuit without reducing the sensitivity.

In addition, the additional on-chip circuitry that can be integrated by the embodiment can increase the performance of the image sensor and further reduce the size and manufacturing cost of the device.

Further, according to the embodiment, it is possible to prevent defects in the photodiode while employing a vertical photodiode.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a cross-sectional view of an image sensor according to an embodiment.

2 to 7 is a process cross-sectional view of the manufacturing method of the image sensor according to the embodiment.

Claims (10)

A circuit formed on the substrate, including the transistor; A first plug and a second plug formed on the substrate to have different heights and electrically connected to the circuit; First and second lower electrodes formed on the first plug and the second plug, respectively; And And a photodiode formed on the first lower electrode and the second lower electrode, The photodiode formed on the first lower electrode and the photodiode formed on the second lower electrode have different heights, but are connected to each other. According to claim 1, And a planarization layer formed on the photodiode. According to claim 1, The first lower electrode and the second lower electrode Image sensors, characterized in that formed in different heights. delete According to claim 1, The photodiode A first conductivity type conductive layer formed on the first lower electrode and the second lower electrode; An intrinsic layer formed on the first conductivity type conductive layer; And And a second conductivity type conductive layer formed on the intrinsic layer. Forming a circuit including a transistor in the substrate; Forming a first plug and a second plug having different heights on the substrate to be electrically connected to the circuit; Forming a first lower electrode and a second lower electrode on the first plug and the second plug, respectively; And Forming a photodiode on the first lower electrode and the second lower electrode; The photodiode formed on the first lower electrode and the photodiode formed on the second lower electrode have different heights, but are connected to each other. The method of claim 6, After forming the photodiode, And forming a planarization layer on the photodiode. The method of claim 6, Forming the first plug and the second plug having a different height on the substrate, Forming a first interlayer dielectric layer on the substrate; Forming a first plug on the first interlayer insulating layer so as to correspond to each pixel; Forming a second interlayer dielectric layer on the first interlayer dielectric layer; Forming a trench in a second interlayer insulating layer corresponding to a second pixel, and then forming a second plug connected to the first plug in the trench; Forming a photoresist pattern on the second interlayer insulating layer, the photosensitive film pattern exposing a second interlayer insulating layer corresponding to a first pixel; And Selectively etching the second interlayer insulating layer using the photoresist pattern as an etch mask to expose a first plug corresponding to a first pixel; In the second pixel, the first plug and the second plug form a stacked structure, and in the first pixel, only the first plug is formed so that the total height from the substrate is different from each other. Manufacturing method. The method according to any one of claims 6 to 8, The first lower electrode and the second lower electrode Method of manufacturing an image sensor, characterized in that the height is formed different from each other. The method of claim 9, Forming the photodiode, Forming a first conductive type conductive layer on the first lower electrode and the second lower electrode; Forming an intrinsic layer on the first conductivity type conductive layer; And And forming a second conductive type conductive layer on the intrinsic layer.

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