KR100889816B1 - A phase calibration apparatus and method - Google Patents

Abstract

The present invention relates to a phase alignment device and method, and more particularly, further comprising a logic gate and a deskew phase alignment device that can be quickly and accurately synchronized by removing the phase difference between the test signals output in the test device; It is about a method.

The present invention provides a plurality of drivers for outputting a test signal; A logic gate configured to receive and synthesize each test signal of the driver; A deskew for delaying the signal synthesized at the logic gate by a predetermined delay value; And a comparator receiving the plurality of test signals and a delay signal, comparing two corresponding signals, measuring a phase delay value, and aligning the remaining signals with a signal having the largest phase delay value among the phase delay values. do.

Description

Phase alignment apparatus and method

1a and 1b is a configuration diagram of a phase alignment device according to the prior art,

2a and 2b is a phase difference measurement graph of the phase alignment device according to the prior art,

3 is a configuration diagram of a phase alignment device according to an embodiment of the present invention,

4 is a flowchart of a phase alignment method according to an embodiment of the present invention,

5 is a graph of a test signal, a synthesized signal and a delay signal according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

110, DR1 to DRn: Driver 120: Logic Gate

130: deskew 140, CP1 to CPn: comparator

The present invention relates to a phase alignment device and method, and more particularly, further comprising a logic gate and a deskew phase alignment device that can be quickly and accurately synchronized by removing the phase difference between the test signals output in the test device; It is about a method.

In general, a computer stores temporary instructions or data necessary to perform a series of tasks in a memory, and a central processing unit (CPU) quickly accesses instructions and data stored in a memory to process a task.

Therefore, as the capacity of the memory increases, the performance of the computer is improved. To this end, various types of memory modules have been developed.

These memory modules are tested using a special specialized equipment to check the characteristics or reliability of the internal circuit after the assembly process.

The phase alignment device, which is a high-speed signal device for testing a conventional memory module, is described with six channels as an example. The first alignment jig for aligning the phase difference between the signals of the drivers DR1 to DR6 and the comparators CP1 to CP6, 2nd alignment jig for aligning the phase difference between driver DR1 and driver DR2, driver DR2 and driver DR3, driver DR3 and driver DR4, driver DR4 and driver DR5, driver DR5 and driver DR6, driver DR6 and driver DR1, output to each drive The first alignment jig and the second alignment jig are drivers DR1 to DR6 for driving signals and comparators CP1 to CP6 for comparing the driven signals. Consists of.

In the test method of the memory module configured as described above, first, after the first alignment jig is mounted on the test device, the phases of the drivers DR1 to DR6 are adjusted by the test device to match the phase of the drive signal and the comparator signal as shown in FIG. 2A. Next, after the second alignment jig is mounted on the test apparatus, the phase difference of the comparator is measured by the test apparatus to match the signal phase between the comparators CP1 to CP6 as shown in FIG. 2B.

Here, the phase difference measurement method between the channels is connected from the driver DR1 to the driver CP6 according to the configuration of the first alignment jig of FIG. 1A, and thus, the phase difference between the channel 1 and the channel 6 is measured, and the driver DR2 is connected to the comparator CP1. Measure the phase difference of channel 1, and measure the phase of the remaining channels in the same way.

When the memory module is tested in this manner, the number of channels must be repeated and the test device adjusts the phase difference between the drivers DR1 to DR6 of the second alignment jig and the comparator by the measured phase difference of each channel.

As a result, an error of several picoseconds (ps) occurs when measuring the phase difference between channels, and this error is transmitted and accumulated when comparing the next channel, and the accuracy decreases toward the next channel. In addition, there is a problem in that it takes more time than the method of adjusting all channels at the same time because the phase is adjusted for each channel.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to eliminate a cumulative error during phase alignment by using a logic gate and deskew, and greatly shorten the phase alignment time. To provide a phase alignment device and method.

Another object of the present invention is to provide an economical and easy-to-use phase alignment device and method because it is possible to reduce the number of phase alignment devices by using a logic gate and deskew.

Technical means according to the present invention for achieving the above object comprises a plurality of drivers for outputting a test signal; A logic gate configured to receive and synthesize each test signal of the driver; A deskew for delaying the signal synthesized at the logic gate by a predetermined delay value; And a comparator receiving the plurality of test signals and a delay signal, comparing two corresponding signals, measuring a phase delay value, and aligning the remaining signals with a signal having the largest phase delay value among the phase delay values. do.

In order to achieve the above object, the technical method according to the present invention initializes a deskew allocated to each channel, outputs a test signal of each driver to a logic gate, and synthesizes a test signal through the logic gate. And delaying the synthesized signal by a predetermined delay value to generate a delay signal, comparing a plurality of delay signals with corresponding test signals, measuring a phase delay value, and a signal having the largest phase delay value among the phase delay values. After adjusting each driver signal at, it outputs normal signal.

According to the present invention, by accumulating signals of all channels by using deskew, cumulative errors can be eliminated.

In addition, the phase difference for all channels can be measured and aligned at the same time, greatly reducing work time.

In addition, it is very economical and easy to use because only one phase alignment device needs to be used.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram of a phase alignment device according to an exemplary embodiment of the present invention, and includes a driver 110, a logic gate 120, a deskew 130, and a comparator 140.

The driver 110 is a component that outputs a test signal among high-speed signal devices mounted inside the memory test device.

The driver 110 is configured in plural numbers according to the number of channels of the output signal, and currently uses about 50 to 60 channels. In this embodiment, n channels are described by way of example.

That is, the drivers 110 (DR1 to DRn) are configured with n to output signals of n channels, and output test signals to the logic gate 120 and the comparator 140 through each driver.

The logic gate 120 has a plurality of drivers connected to each input terminal, respectively, synthesizes a test signal input through the plurality of drivers 110, detects a signal having the earliest phase among the synthesized signals, and sets a reference signal. At this time, the detected signal is transmitted to the deskew 130.

Here, the logic gate 120 is an OR (logical sum) gate capable of synthesizing a plurality of drive signals, and outputs a high signal to the deskew when at least one signal is high, and a deskew low signal when all signals are low. Outputs

The deskew 130 delays 2/3 periods of the synthesized signal input from the logic gate 120 around the reference signal. In this case, the reason for delaying the 2/3 period is to delay the period within one period in order to stably process the next signal. However, in the present embodiment, 2/2 which can process the next signal most stably obtained according to the experiment is performed. Use 3 cycles.

In addition, the deskew 130 delays the synthesized signal delayed by 2/3 cycles by 2.5ps, which is the minimum unit that can be delayed from the time of delaying the synthesized signal by 2/3 cycles, and transmits the delayed synthesized signal to the comparator 140.

In the comparators 140 (CP1 to CPn), a plurality of drivers are connected to each input terminal, respectively, and a test signal input through the plurality of drivers 110 is input.

In addition, the comparator 140 compares the delayed signal inputted through the deskew 130 with the delayed signal and the signal transmitted from the corresponding driver, and the logic value of the corresponding signal is different from each other. Record the value of. The value at this time becomes the phase delay measurement value of the corresponding channel.

In addition, when the measurement of the phase delay measurement value of each channel is completed, the comparator 140 adjusts the driver signal to the channel having the largest phase delay value and then aligns the signal of the comparator 140.

In addition, the driver 110 adjusts the driver signal to the channel having the largest phase delay value when the measurement of the phase delay measurement value of each channel is completed.

As described above, the skew between the plurality of signals is compensated for and eliminated through the configuration including the deskew, thereby improving the set-up, holding time, cumulative error and operating speed characteristics of the internal signal, and performing synchronously stable operation. . In addition, the phase difference for all channels can be measured and aligned at the same time, greatly reducing work time.

4 is a flowchart of a phase alignment method according to an exemplary embodiment of the present invention with reference to FIGS. 3 and 5.

First, the deskew 130 allocated to all channels is initialized to 0 (S1).

Next, the driver 110 (DR1 to DRn) outputs a test signal of each channel to the logic gate 120 and the comparator 140 (CP1 to CPn) (S2).

The waveform at this time is as shown in FIG. In FIG. 5, three drivers will be described as an example. That is, the signal a is a waveform of the test signal output through the driver, and the signal b is a waveform generated when the test signal is output to the comparator through the driver.

The logic gate synthesizes a test signal of each channel input from the driver 110 (S3), and then detects a signal whose phase is most advanced. The phase is set based on the signal with the fastest phase (S4) and the remaining signals are aligned accordingly.

Here, the synthesized signal becomes a synthesized waveform as shown in FIG. 5 according to the characteristics of the logic sum which is a logic gate. In this case, the synthesized signal is slightly lower than the fastest signal according to the proportional derivative (PD) control, which is used in parallel to the proportional control by using the derivative control in which the error signal is differentiated to produce the control signal.

Next, when the synthesized signal is input to the deskew 130, the deskew generates a delay signal by delaying the input synthesized signal by a 2/3 cycle S5 as illustrated in FIG. 5.

In this case, the delay period is delayed by a period smaller than one for signal processing, that is, a 2/3 period which is a delay period that is most stably processed.

At this time, the phase comparison is started from the part delayed by 2/3 periods. For more precise phase alignment, the next 2/3 period delayed signal is re-started from the point where 2/3 periods are delayed by 2.5ps, the minimum unit of the delay period. It is preferable to delay (S5).

At this time, the delayed delay signal is compared with each test signal in the comparator 140 (S6) and the value of the generation point of the high signal where the logic values of the two signals coincide. The recorded value at this time is the phase delay measurement value of the corresponding channel.

When the phase delay values for all the channels are measured by the above method, the driver signal is matched to the channel having the largest phase delay value and the signals of the comparator are also aligned (S7).

Thereafter, each channel is simultaneously compensated and a normal signal, which is a data transmission signal such as a memory, is output.

By aligning the phases in this way, the phase difference for all channels can be measured and aligned at the same time, thereby greatly reducing the work time.

In addition, it is very economical and easy to use because only one phase alignment device needs to be used.

The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.

As described in detail above, the present invention can eliminate the accumulated error by aligning the signals of all channels using deskew.

In addition, the phase difference for all channels can be measured and aligned at the same time, greatly reducing work time.

In addition, it is very economical and easy to use because only one phase alignment device needs to be used.

Claims (7)

A plurality of drivers for outputting a test signal; A logic gate configured to receive and synthesize each test signal of the driver; A deskew for delaying the signal synthesized at the logic gate by a predetermined delay value; And And a comparator for receiving the plurality of test signals and delay signals, comparing two corresponding signals, measuring a phase delay value, and aligning the remaining signals with a signal having the largest phase delay value among the phase delay values. Characterized in phase alignment device. The method of claim 1, wherein the logic gate And a logical sum gate. The method of claim 1, wherein the driver And outputting a normal signal according to the signal having the largest phase delay value among the phase delay values. After initializing deskew assigned to each channel, output test signal of each driver to logic gate, After synthesizing a test signal through the logic gate, a delayed signal is generated by delaying the synthesized signal by a predetermined delay value, The phase delay value is measured by comparing the test signals corresponding to the plurality of delay signals. And aligning each driver signal with a signal having the largest phase delay value among the phase delay values and outputting a normal signal. The method of claim 4, wherein synthesizing a test signal through the logic gate And detecting the earliest of the plurality of test signals and setting the reference signal. The method of claim 5, wherein the preset delay value is And a period value within one period of the reference signal. The method of claim 6, The delay signal is And delaying 2.5 picoseconds, which is the minimum value of the delay value, with respect to the reference signal.

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