KR100887672B1 - Array substrate for in plane switching mode liquid crystal display device - Google Patents

Abstract

The present invention relates to an array substrate for a horizontal electric field drive type liquid crystal display device.

In general, the common wiring of the horizontal electric field driving type liquid crystal display device is formed to be parallel to the gate wiring. In the case of the large screen, the panel has a larger size than the effective processing area of the exposure machine. At this time, since the signal value of the common wiring is changed in the region in which the stitching occurs due to the deviation between the exposure shots and the divided exposure, a difference in image quality occurs in each region.

In the array substrate of the horizontal electric field drive type liquid crystal display device according to the present invention, when a large screen panel is manufactured by divided exposure, the common wiring is formed in parallel with the data wiring, and the signals of the common wiring are formed by the divided exposure. Apply differently in the domain. Therefore, uniform image quality can be displayed by individually controlling the signals of the common wiring for each of the divided exposure regions. In addition, when the common wiring overlaps with the data wiring, the aperture ratio can be increased.

Horizontal electric field, IPS, split exposure, large screen, aperture ratio

Description

Array substrate for in plane switching mode liquid crystal display device             

1 is a circuit diagram of a general horizontal electric field drive type liquid crystal display device.

2 is a plan view of an array substrate for a conventional horizontal electric field drive type liquid crystal display device;

3 is a cross-sectional view taken along line III-III of FIG. 2.

4 is a cross-sectional view of an array substrate for a horizontal electric field drive type liquid crystal display device having a conventional high opening ratio.

5 is a circuit diagram of a conventional horizontal electric field drive type liquid crystal display device having a high opening ratio.

6 is a schematic view of an array substrate for a conventional horizontal electric field drive type liquid crystal display device.

FIG. 7 schematically illustrates an array substrate for a conventional large-screen horizontal electric field drive type liquid crystal display device. FIG.

FIG. 8 schematically illustrates an array substrate for a horizontal electric field drive type liquid crystal display device according to an exemplary embodiment of the present invention. FIG.

9 is a plan view of an array substrate for a horizontal electric field drive type liquid crystal display device according to a first embodiment of the present invention.

FIG. 10 is a cross-sectional view taken along the line VII-VII of FIG. 9. FIG.

11 is a plan view of an array substrate for a horizontal electric field drive type liquid crystal display device according to a second exemplary embodiment of the present invention.

FIG. 12 is a cross-sectional view taken along the line II-II of FIG. 11. FIG.

<Description of Symbols for Main Parts of Drawings>

110: substrate 151a, 151b: common wiring

152a, 152b: common electrode 130: insulating film

131: data wiring 162: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a horizontal electric field drive type liquid crystal display device in which first and second electrodes for driving liquid crystal molecules are formed on the same substrate.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. It is a device that expresses an image by the transmittance of light that changes according to the movement of liquid crystal molecules by an electric field.

Liquid crystal displays may be formed in various forms. Currently, an active matrix LCD (AM-LCD) having a thin film transistor and pixel electrodes connected to the thin film transistors arranged in a matrix manner has excellent resolution and video performance. It is most noticed.

The liquid crystal display device has a structure in which a pixel electrode is formed on a lower substrate and a common electrode is formed on an upper substrate, and the liquid crystal molecules are driven by an electric field in a direction perpendicular to the substrate between the two electrodes. This is excellent in characteristics such as transmittance and aperture ratio, and the common electrode of the upper plate serves as a ground, thereby preventing the destruction of the liquid crystal cell due to static electricity.

However, such a liquid crystal display has a disadvantage that the viewing angle characteristics are not excellent. Accordingly, various methods have been proposed to overcome these disadvantages, and one example thereof is a horizontal electric field driving method, that is, a liquid crystal display device in an in-plane switching (IPS) mode.

Hereinafter, a general IPS mode liquid crystal display will be described with reference to the accompanying drawings.

1 is a circuit diagram of a general IPS mode liquid crystal display device. As shown in the drawing, the gate wiring 1 and the data wiring 2 cross each other, and the thin film transistor T is formed at the intersection of the gate wiring 1 and the data wiring 2 to form the gate wiring 1 and the data. It is connected to the wiring 2. Subsequently, the liquid crystal capacitor C _{LC is} connected to the thin film transistor T, and the same voltage Vcom is applied to one electrode of the neighboring liquid crystal capacitor C _LC . In addition, the storage capacitor C _{ST is} connected to each liquid crystal capacitor C _LC .

2 is a plan view of the array substrate for the IPS mode liquid crystal display device. As shown in the drawing, a pixel region is defined by the orthogonal crosswise of the gate wiring 21 in the horizontal direction and the data wiring 31 in the vertical direction, and the thin film transistor is positioned at the intersection of the gate wiring 21 and the data wiring 31. T) is formed. The thin film transistor T includes a gate electrode 22 connected to the gate line 21, a source electrode 32 connected to the data line 31, and a source electrode 32 around the gate electrode 22. It consists of the drain electrode 33 which faces the surface. The thin film transistor T further includes an active layer 41 made of amorphous silicon.

Next, the common wiring 51 is formed in a direction parallel to the gate wiring 21, and the first and second common electrodes 52 and 53 which have a vertical direction and are connected to the common wiring 51 are formed in the pixel area. Formed.

In addition, a pixel electrode 62 having a vertical direction and being alternately spaced apart from the common electrodes 52 and 53 by a predetermined interval is formed, and the pixel electrode 62 is connected to the drain electrode 33. .

A cross section of the array substrate for an IPS mode liquid crystal display is illustrated in FIG. 3, which corresponds to a cross section taken along line III-III of FIG. 2.                         

As shown, the common electrodes 52 and 53 are formed on the board | substrate 10, and the insulating film 30 is formed on it. Subsequently, a data line 31 and a pixel electrode 62 are formed on the insulating film 30, but the pixel electrodes 62 are alternately arranged with the common electrodes 52 and 53. Here, the common electrodes 52 and 53 are connected to the common electrodes 52 and 53 of pixels that are adjacent to the left and right by a common wiring (not shown) parallel to the gate wiring (not shown) to form the same voltage Vcom. Licensed.

Accordingly, when a voltage is applied, an electric field is formed between the pixel electrode 62 and the common electrodes 52 and 53. In the IPS mode liquid crystal display, the pixel electrode 62 and the common electrodes 52 and 53 have a single electric field. Since it is formed in the substrate, an electric field horizontal to the substrate is generated.

However, since the pixel electrode and the common electrode are made of a material such as metal, the IPS mode liquid crystal display has a low aperture ratio.

Therefore, recently, an IPS mode liquid crystal display device having a high opening ratio has been proposed, and a cross section of a conventional array substrate for an IPS mode liquid crystal display apparatus having such a high opening ratio is shown in FIG. 4. As shown, the common electrode 72 is formed on the substrate 70, and the insulating film 74 is formed thereon. The data line 76 and the pixel electrode 78 are formed on the insulating layer 74. The data line 76 overlaps the common electrode 72, and the pixel electrode 78 is formed on the common electrode 72. Staggered, ie, located between the common electrodes 72. Here, the common electrode 72 is connected to the common electrode 72 of the neighboring pixel to apply the same voltage Vcom. As described above, since the common electrode 72 and the data line 76 overlap each other, the area where light is blocked by the common electrode 72 is reduced, so that the aperture ratio of the liquid crystal display device can be improved.

5 is a circuit diagram of an IPS mode liquid crystal display having a high opening ratio. As illustrated, in the IPS mode liquid crystal display having such a high opening ratio, one end of the liquid crystal capacitor C _LC and the storage capacitor C _ST is connected to the common voltage Vcom applied through the common electrode.

An array substrate for an IPS mode liquid crystal display device is schematically illustrated in FIG. 6, but as shown, the substrate 80 has a display area A in which an image is represented. In the display area A on the substrate 80, a plurality of common wires 82 extend in the horizontal direction. Although not shown, the display area A includes a plurality of gate wirings having a horizontal direction, a plurality of data wirings having a vertical direction, and a thin film transistor and a pixel electrode connected to the gate lines and the data wirings. Outside the display area A, a gate driving circuit 84 and a data driving circuit 86 for applying signals to the gate wiring and the data wiring are formed, respectively. On the other hand, the plurality of common wires 82 are all connected to receive the same signal from the gate driving circuit 84.

In general, in the case of a small sized or medium sized liquid crystal display device having a panel size of about 30 inches or less, since the panel exposure machine is within the effective processing area, it is possible to form a batch exposure.

However, in the case of a large liquid crystal display device having a panel size of about 30 inches or more as shown in Fig. 7, the size of the panel is larger than the effective treatment area of the exposure machine, so that the divided exposure should be performed. In FIG. 7, the first to third display regions B, C, and D show regions formed by respective exposures. At this time, the stitching occurs due to the deviation between the exposure shots, and thus the common wiring 92 signal value varies in each of the regions B, C, and D. FIG. Therefore, a difference in image quality occurs in each of the regions B, C, and D.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an array substrate for an IPS mode liquid crystal display device having a wide viewing angle and uniform image quality.

In order to achieve the above object, an array substrate for a horizontal field drive liquid crystal display device according to the present invention includes a substrate including at least two regions, a plurality of gate wirings formed on the substrate and having a first direction, and a second substrate. A plurality of data lines defining a pixel area intersecting the gate line with a direction, a thin film transistor connected to the gate line and the data line, and connected to a pixel adjacent in the second direction with a direction parallel to the data line; And a plurality of first and second common wires formed in the first and second regions, respectively, and connected to the thin film transistor in the second direction, and spaced apart from the first and second common wires by a predetermined distance. And a pixel electrode, wherein a first signal is applied to the first common wiring of the first region, A second signal different from the first signal is applied to the second common wiring of the second region, and the first and second common wiring overlap the data wiring.

Here, the substrate has a size of 30 inches or more, and the first and second regions may be formed by split exposure.

On the other hand, it is preferable that the first and second common wirings of the first and second regions adjacent to each other overlap one data wiring.

In the present invention, the first and second common wirings may be made of the same material as the gate wiring, and the pixel electrode may be made of the same material as the data wiring.

Meanwhile, the array substrate according to the present invention may further include first and second common electrodes positioned in the second direction between the pixel electrode and the data line and connected to the first and second common lines, respectively.

As described above, in the array substrate of the horizontal electric field drive type liquid crystal display device according to the present invention, when the large screen panel is manufactured by the divided exposure, the common wiring is formed in parallel with the data wiring, and the signal of the common wiring is divided by the exposure. Apply differently in each area to be formed. Therefore, by controlling the signals in the divided-exposed areas individually, it is possible to display uniform image quality. In addition, when the common wiring overlaps with the data wiring, the aperture ratio can be increased.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

FIG. 8 schematically illustrates an array substrate for an IPS mode liquid crystal display according to an embodiment of the present invention, wherein the IPS mode liquid crystal display according to the present invention has a large screen of about 30 inches or more. As shown, the substrate 110 includes first to third display regions E, F, and G in which an image is represented. The first to third display areas E, F, and G are areas formed by respective divided exposures, and the first to third display areas E, F, and G each have a plurality of first to third common areas. The wirings 112a, 112b, 112c extend in the vertical direction. Although not shown, the first to third display regions E, F, and G have a plurality of gate wires having a horizontal direction, a plurality of data wires having a vertical direction, and a thin film connected to the gator wires and the data wires. Transistors and pixel electrodes are formed. Next, a gate driving circuit 114 and a data driving circuit 116 are provided outside the display areas E, F, and G for applying signals to the gate wiring and the data wiring, respectively.

Here, the first to third common wires 112a, 112b, and 112c are connected to the data driver circuit 116 on the side facing each other, and receive a signal from the gate driver circuit 114. That is, the first common line 112a of the first region E receives the first signal Vcom1, and the second common line 112b of the second region F applies the second signal Vcom2. The third common line 112c of the third region C receives the third signal Vcom3.

An array substrate for an IPS mode liquid crystal display according to a first embodiment of the present invention having such a structure is shown in FIG. 9, which is disposed in the pixels of the first region E and the second region F of FIG. 8. For the top view.

As shown in the drawing, the horizontal gate line 121 and the vertical data line 131 are orthogonal to each other to define a pixel area, and the thin film transistor is positioned at the intersection of the gate line 121 and the data line 131. (T) is formed. The thin film transistor T includes a gate electrode 122 connected to the gate line 121, a source electrode 132 connected to the data line 131, and a source electrode 132 around the gate electrode 122. It consists of a drain electrode 134 facing the surface. Meanwhile, the thin film transistor T further includes an active layer 141 made of amorphous silicon.

Next, the common wirings 151a and 151b and the common electrodes 152a and 152b are formed in a direction parallel to the data wirings 131 in the pixel area, and the common electrodes 152a and 152b are connected to the common wirings 151a and 151b. The common wires 151a and 151b are connected to each other in vertically adjacent pixels. In addition, pixel electrodes 162 having a vertical direction and staggered with the common wirings 151a and 151b and the common electrodes 152a and 152b are spaced apart from each other, and the pixel electrodes 162 are drained. It is connected to the electrode 134.

As described above, the common wiring 151a is formed in the vertical direction in the first and second regions E and F, respectively, but the common wiring 151a and the second region F of the first region E are common. Different signals are applied to the wiring 151b.

This will be described in detail with reference to FIG. 10. FIG. 10 is a cross-sectional view taken along the line VII-VII of FIG. 9.

As illustrated, the substrate 110 is divided into first and second regions E and F, and common wirings 151a and 151b and common electrodes 152a and 152b are formed on the substrate 110. In this case, although omitted in the drawing, as an example, the common wires 151a and 151b and the common electrodes 152a and 152b are more precisely in contact with an insulating layer (not shown) and are formed on the insulating layer (not shown). Gate wiring (not shown) and gate electrode (not shown) are formed between the insulating layer (not shown) and the substrate 110. The common wirings 151a and 151b and the common electrodes 152a and 152b may be formed of the same material as the gate wiring (not shown). Next, an insulating film 130 is formed thereon, and a data line 131 and a pixel electrode 162 are formed on the insulating film 130. The pixel electrode 162 may be formed of the same material as the data line 131, and the pixel electrode 162 may be alternately disposed with the common lines 151a and 151b and the common electrodes 152a and 152b. Here, the first signal Vcom1 is applied to the common wiring 151a and the common electrode 152a of the first region E, and to the common wiring 151b and the common electrode 152b of the second region F. The second signal Vcom2 is applied.

As described above, in the present invention, when the large screen panel is manufactured by the divisional exposure, the common wiring is formed in parallel with the data wiring, and the signal of the common wiring is applied differently in each area formed by the divisional exposure, so that the signals are individually To control. Therefore, a uniform picture quality can be displayed on the large screen.

On the other hand, as described above, the IPS mode liquid crystal display device has a low aperture ratio, and in order to increase the aperture ratio, the common wiring may overlap the data wiring.

11 is a plan view of an array substrate for an IPS mode liquid crystal display device according to a second exemplary embodiment of the present invention. FIG. 11 corresponds to a pixel of the first region E and the second region F of FIG. 8. do.

As shown in the drawing, the horizontal gate line 221 and the vertical data line 231 are orthogonal to each other to define a pixel area, and the gate electrode 221 is positioned at the intersection of the gate line 221 and the data line 231. The thin film transistor T including the 222, the source electrode 232, and the drain electrode 234 is formed. The thin film transistor T is connected to the gate line 221 and the data line 231, and further includes an active layer 241 made of amorphous silicon.

Next, the common wires 251a, 251b, 252a, and 252b are formed in parallel with the data wires 231 and are connected to each other in vertically adjacent pixels. The common wires 251a, 251b, 252a, and 252b are connected to the data wires ( 231). At this time, the common wirings 252a and 252b which are positioned adjacent to the first and second regions E and F are separated. Meanwhile, a pixel electrode 262 is formed in the pixel area and positioned between the common lines 251a, 251b, 252a, and 252b, and the pixel electrode 262 is connected to the drain electrode 234.

Here, different signals are applied to the common wirings 251a and 252a of the first region E and the common wirings 251b and 252b of the second region F. FIG.

This will be described in detail with reference to FIG. 12. FIG. 12 is a cross-sectional view taken along the line II-II of FIG. 11.

As illustrated, the substrate 210 is divided into first and second regions E and F, and common wirings 251a, 251b, 252a, and 252b are formed on the substrate 210. In this case, although omitted in the drawing, as an example, the common wires 251a, 251b, 252a, and 252b are more precisely in contact with an insulating layer (not shown) and are formed on the insulating layer (not shown). A gate wiring (not shown) and a gate electrode (not shown) are formed between the layer (not shown) and the substrate 210. The common wires 251a, 251b, 252a, and 252b may be formed of a material such as a gate wire (not shown). Next, an insulating film 230 is formed on the common wirings 251a, 251b, 252a, and 252b, and a data wiring 231 and a pixel electrode 262 are formed thereon. The data line 231 overlaps the common lines 251a, 251b, 252a, and 252b, and the pixel electrode 262 is positioned between the common lines 251a, 251b, 252a, and 252b. Here, the pixel electrode 262 may be formed of the same material as the data line 231.

In this case, the common lines 252a and 252b are adjacent to the first and second regions E and F, so that different signals are applied to the pixels of the two regions, and thus are separated from each other. Therefore, the first signal Vcom1 is applied to the common wirings 251a and 252a of the first region E, and the second signal Vcom2 is applied to the common wirings 251b and 252b of the second region F. do.

As described above, in the second embodiment of the present invention, when the large screen panel is manufactured by the divided exposure, the common wiring is formed in parallel with the data wiring, and the signal of the common wiring is applied differently in each region formed by the divided exposure. do. In addition, by overlapping the common wiring with the data wiring, a uniform image quality can be displayed on a large screen, and the aperture ratio can be increased.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

In the IPS mode liquid crystal display device according to the present invention, when the large screen panel is manufactured by the divided exposure, the common wiring is formed in parallel with the data wiring, and the signal of the common wiring is applied differently in each region formed by the divided exposure. . Therefore, by controlling the signals in the divided-exposed areas individually, it is possible to display uniform image quality. In addition, when the common wiring overlaps with the data wiring, the aperture ratio can be increased.

Claims (8)

A plurality of gate wirings formed on the substrate with a first direction; A plurality of data lines having a second direction and defining at least a first region and a second region crossing the gate lines; A thin film transistor connected to the gate line and the data line; First and second common wires having the second direction and formed in the first area and the second area, respectively; And A pixel electrode connected to the thin film transistor and formed with a predetermined distance from the first and second common lines; A first signal is applied to the first common wiring of the first region, a second signal different from the first signal is applied to the second common wiring of the second region, and the first and second And a common wiring overlapping with the data wiring. The method of claim 1, And the substrate has a size of 30 inches or more. The method of claim 1, And the first and second regions are formed by split exposure. delete The method of claim 1, An array substrate for a horizontal electric field drive type liquid crystal display device, wherein the first and second common wirings of the first and second regions adjacent to each other overlap one data wiring. The method of claim 1, And the first and second common wirings are made of the same material as the gate wirings. The method of claim 1, And the pixel electrode is formed of the same material as the data line. The method of claim 1, And a first common electrode and a second common electrode disposed between the pixel electrode and the data line in the second direction and connected to the first and second common lines, respectively. Board.

Images