KR100883778B1 - Display and method for transmitting clock signal in blank period - Google Patents

Abstract

A display apparatus and a transmitting method thereof are provided to require no additional clock line by transmitting a clock signal during a blank period through a data line, and to remove electromagnetic wave interference at an addition clock line by transmitting a clock signal through a data line. A timing control unit(100) applies transmission signals to data lines during an active period and the transmission signals correspond to data bits. The timing control unit a transmission clock signal to the data lines during a black period. During the active period the data bits are transmitted, but the data bits are not transmitted during the blank period. A data driving unit(200) decodes the data bits by sampling the transmission signal transmitted through the data lines, and drives a display panel(400) in accordance with the decoded data bits.

Description

Display and method for transmitting clock signal in blank period

The present invention relates to a display and a method for transmitting a clock signal in a blank period, and in particular, the present invention is applied to an interface between a timing controller and a data driver of a display, whereby electromagnetic interference (Hereinafter, simply referred to as EMI) has the advantage of reducing the number of components and lines.

As a conventional technology of an interface between a timing controller of a display and a data driver, there is a point-to-point differential signaling (PPDS) scheme announced by National Semiconductor.

1 is a diagram for explaining a PPDS scheme. Referring to FIG. 1, the PPDS scheme is characterized in that an independent data line 3 is connected between the timing controller 1 and each data driver 2. The PPDS scheme has an advantage of reducing EMI and reducing the total number of signal lines compared to conventional reduced swing differential signaling (RSDS) and low voltage differential sibling (mini-LVDS). The clock line 4 and the load line 5 are connected between the timing controller 1 and the data drivers 2. The clock line 4 and the load line 5 are commonly connected to the data drivers 2. Since differential signaling is used for the transmission of the data signal and the clock signal, the data line 3 and the clock line 4 each consist of a differential pair.

The above described PPDS scheme has some room for improvement.

First, in the PPDS scheme, a clock line is required separately from the data line. More specifically, since the clock signal is transmitted from the timing controller 1 to the data driver 2 through a separate line different from the data signal, a clock line for transmitting the clock signal is required, which increases the complexity of the wiring and , Increase display manufacturing costs.

Second, in the PPDS scheme, the high frequency clock signal transmitted through the clock line increases the EMI component.

Accordingly, a technical problem to be solved by the present invention is to provide a display and a method in which a separate clock line is not required by transmitting a clock signal through a data line in a blank period.

In addition, the technical problem to be solved by the present invention is to provide a method and apparatus that can remove the EMI component generated from a separate clock line by transmitting a clock signal through the data line.

As a technical means for achieving the above object, a first aspect of the present invention is a data line; A timing controller for applying a transmission signal corresponding to the data bits to the data line in an active period for transmitting data bits, and applying a transmission clock signal to the data line in a blank period for not transmitting the data bits; And a data driver configured to sample the transmission signal transmitted through the data line (hereinafter referred to as a reception signal) to restore the data bits and to drive a display panel according to the restored data bits. .

A second aspect of the invention provides a serialization unit for generating serialized transmission bits corresponding to data bits; A clock generator for generating a transmission clock signal; And a multiplexing unit outputting the transmission bits in an active period for transmitting the data bits, and outputting the transmission clock signal in a blank period in which the data bits are not transmitted.

A third aspect of the invention provides a clock generator for generating a sampling clock signal in accordance with a received clock signal, the received clock signal being transmitted through a data line in a blank period in which data bits are not transmitted. And a sampler configured to sample a reception signal according to the sampling clock signal, wherein the reception signal is transmitted through the data line in an active period in which data bits are transmitted, and restore a data bit included in the reception signal. to provide.

A fourth aspect of the present invention provides a method of transmitting data bits from a timing controller to a data driver via a data line, the method comprising: (a) transmitting a transmission clock signal through the data line in a blank period in which the data bits are not transmitted; Transmitting; And (b) transmitting a transmission signal corresponding to the data bits over the data line in an active period during which the data bits are transmitted.

The display and the method for transmitting the clock signal in the blank period according to the present invention have the advantage that the clock signal can be transmitted without a separate clock line separate from the data line.

In addition, the display and method for transmitting the clock signal in the blank period according to the present invention has the advantage that the EMI component generated from a separate clock line is removed.

2 is a view schematically illustrating a structure of a display according to a first embodiment of the present invention. Referring to FIG. 2, the display includes a timing controller 100, data drivers 200, scan drivers 300, and a display panel 400.

The timing controller 100 applies a transmission signal corresponding to the data bits to each data line 500 in the active period for transmitting the data bits, and applies the transmission signal corresponding to the data bits to each data line 500 in the blank period during which the data bits are not transmitted. Apply the transmit clock signal. Preferably, the transmission clock signal has a period corresponding to an integer multiple of a period corresponding to one bit of the transmission signal. In addition, the timing controller 100 provides the data driver 200 with an active signal ACT indicating whether it is a blank period or an active period. In addition, the timing controller 100 provides the clock driver CLK_S and the start pulse SP to the scan driver 300.

The data driver 200 restores data bits from the received signal by sampling a transmission signal (hereinafter referred to as a reception signal) transmitted through the data line 500 in an active period, and displays the display panel 400 according to the restored data bits. Are applied to the data signals. In addition, the data driver 200 generates a sampling clock signal according to a transmission clock signal (hereinafter referred to as a reception clock signal) transmitted through the data line 500 in the blank period. The data driver 200 restores the data bits by sampling the received signal according to the generated sampling clock signal. Also, the data driver 200 determines whether the data driver 200 is an active period or a blank period according to the active signal ACT.

The scan driver 300 applies scan signals to the display panel 400 according to the clock signal CLK_S and the start pulse SP provided from the timing controller 100.

The display panel 400 is a portion that displays an image according to the scan signals S1 to Sn provided from the scan drivers 300 and the data signals D1 to Dm provided from the data drivers 200. 400 may be, for example, various types of display panels, such as an LCD panel, a PDP panel, or an OELD panel, but is not limited thereto.

As a method of transferring the transmission signal and the transmission clock signal from the timing controller 100 to each data driver 200, a single-ended signaling using one wire may be used, and two wires such as LVDS may be used. Differential signaling may be used.

FIG. 3A illustrates an example of a signal, an active signal ACT, and data bits DATA_BIT transmitted to the data line 500 in a blank period, and FIG. 3B illustrates data in an active period. FIG. 4 is a diagram illustrating an example of a signal, an active signal ACT, and data bits DATA_BIT transmitted through the line 500.

Referring to FIG. 3A, a periodic transmission clock signal is transmitted through the data line 500 in the blank period. If the data line 500 is a differential pair, the signal indicated by the solid line and the dashed line in the figure are transmitted through the differential line. If the data line 500 is a single line, the signal indicated by the solid line in the figure. And a signal indicated by a dotted line is transmitted through a single line. Whether it is a blank period or not is determined from the active signal ACT. In the example shown in the drawing, the low level active signal ACT means a blank period, and the high level active signal ACT means an active period. Unlike the example represented in the figure, the information on whether it is a blank period may be transmitted in various ways. For example, the period from the pulse type active signal is applied until the predetermined period corresponds to the active period, and other periods may correspond to the blank period.

Referring to FIG. 3B, data bits DATA_BIT are transmitted through the data line 500 in the active period. In the figure, an example is shown in which the transmission clock signal has a period T2 corresponding to eight times the period T1 corresponding to one bit of the transmission signal.

4 is a diagram illustrating an example of the timing controller 100 illustrated in FIG. 2. Referring to FIG. 4, the timing controller 100 includes a receiver 110, a buffer memory 120, a clock generator 130, and a transmitter 140.

The receiver 110 performs a function of converting an image data signal or the like input into the timing controller 100 into a transistor-transistor logic (TTL) signal. The received signal input to the timing controller 100 is not limited to the LVDS type signal as shown in the figure, and may be a TMDS (transition minimized differential signaling) type signal, or any other type of signal. The TTL signal generally means a digitally converted signal, and unlike LVDS having a small voltage width of 0.35V, the TTL signal has a large voltage width at the power supply voltage level.

The buffer memory 120 temporarily stores and outputs image data converted into a TTL signal.

The clock generator 130 generates a start pulse SP and a clock signal CLK_S to be transmitted to the scan driver 300. In addition, the clock generator 130 generates an active signal ACT to be transmitted to the data driver 200 and the transmitter 140. In addition, the clock generator 130 generates a transmission clock signal CLK_TX to be transmitted to the transmitter 140.

The transmitter 140 receives the image data output from the buffer memory 120 and the signals CLK_TX and ACT transmitted from the clock generator 130, and transmits a transmission signal or a transmission clock signal to be transmitted to each data driver 200. Is output to the data line 500. To this end, the transmitter 140 includes a distributor 150, serial converters 160, multiplexers 170, and drivers 180. In the drawing, K refers to the number of data drivers 200 connected to the timing controller 100.

The distribution unit 150 distributes the digital bits corresponding to the image data output from the buffer memory 120 to the serial converters 160. The serial converter 160 outputs serialized transmission bits corresponding to the digital bits transmitted from the distribution unit 150. The multiplexer 170 outputs the transmission bits transmitted from the serial converter 160 in the active period, and outputs the transmission clock signal CLK_TX transmitted from the clock generator 130 in the blank period. The driver 180 drives the data line 500 according to the signal output from the multiplexer 170. For example, the driver 180 may output an LVDS signal, which is a differential signal, or may output a single signal as another example.

FIG. 5 is a diagram illustrating an example of the data driver 200 illustrated in FIG. 2. Referring to FIG. 5, the data driver 200 includes a receiver 210, a data latch 220, and a digital-analog converter 230.

The receiver 210 generates a sampling clock signal CLK_SAM according to a transmission clock signal (hereinafter referred to as a reception clock signal) transmitted through the data line 500 in the blank period. In addition, the receiving unit 210 restores data bits from the received signal by sampling the transmission signal (hereinafter referred to as a received signal) transmitted through the data line 500 in the active period according to the sampling clock signal CLK_SAM. To this end, the receiver 210 includes a clock generator 240 and a sampler 250.

The clock generator 240 generates a sampling clock signal CLK_SAM according to the received clock signal. More specifically, the clock generator 240 changes the phase of the sampling clock signal according to the received clock signal in the blank period, and maintains the phase of the sampling clock signal in the same period as the blank period. The clock generator 240 may generate various clock signals and load signals necessary for the operation of the data latch 220 and the DAC 230 from the received clock signal and the active signal ACT. Various clock signals, load signals, and the like necessary for the operation of the data latch 220 and the DAC 230 are known, and the end of the blank period (that is, the start of the active period) and the start of the blank period from the active signal ACT are known. Since the timing (i.e., the end of the active period) can be known and the method of generating the sampling clock signal CLK_SAM from the received clock signal is described in detail herein, one of ordinary skill in the art to which the present invention belongs. In this case, various clock signals and load signals necessary for the operation of the data latch 220 and the DAC 230 may be easily generated from the received clock signal and the active signal ACT, and thus a detailed description thereof will be omitted. .

The sampler 250 samples the received signal according to the sampling clock signal CLK_SAM to recover data bits. The recovered data bits are passed to the data latch 220. The sampler 250 does not operate during the blank period.

The data latch 220 sequentially stores data bits output from the receiver 210 and outputs the data bits in parallel.

The DAC 230 converts the digital signal output from the data latch 220 into an analog signal and outputs the analog signal.

FIG. 6 is a diagram illustrating an example of the clock generator 250 illustrated in FIG. 5. Referring to FIG. 6, the clock generator 250 includes a phase detector 251, a low pass filter 252, a delay line 253, a feedback line 254, and a switch 255.

The phase detector 251 detects a phase difference between the received clock signal and the feedback clock signal FC. Preferably, the phase detector 251 outputs signals UP and DN corresponding to the phase difference between the received clock signal and the feedback clock signal FC in the blank period, and a signal corresponding to no phase difference in the active period. UP and DN are both 0).

The low pass filter 252 removes high frequency components of the signals UP and DN corresponding to the phase difference output from the phase detector 251. The low pass filter 252 may be, for example, a charge pump.

The delay line 253 has a delay corresponding to the phase difference signal DIFF from which the high frequency component output from the low pass filter 252 is removed. The delay line 253 receives a receive clock signal in a blank period and a feedback clock FC in an active period. Delay line 253 outputs a feedback clock FC. Delay line 253 includes a plurality of inverters I1 to I16. The delay of each of the plurality of inverters I1 to I16 is adjusted according to the signal DIFF output from the low pass filter 252. Each of the plurality of inverters I1 to I16 has a delay corresponding to half (T1 / 2) of a period corresponding to approximately one bit of the transmission signal. First, third, and fifth outputs from the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteen inverters I1, I3, I5, I7, I9, I11, I13, and I15, respectively. The fifth, seventh, ninth, eleventh, thirteenth, and fifteenth delayed clocks DC1, DC3, DC5, DC7, DC9, DC11, DC13, and DC15 are output to the sampler 240 as sampling clock signals. The sampler 240 uses the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth delayed clocks DC1, DC3, DC5, DC7, DC9, DC11, DC13, and DC15. By sampling the received signal, 8 bits of data bits are recovered from the received signal for a period corresponding to one period of the received clock signal.

The feedback line 254 is input to the switch 255 to feed back the feedback clock signal FC output from the delay line 253 to the delay line 254.

The switch 255 inputs the receive clock signal to the delay line 253 in the blank period and the feedback clock signal FC to the delay line 253 in the active period.

FIG. 7 is a diagram illustrating an example of the phase detector 251 employed in FIG. 6. Referring to FIG. 7, the phase detector 251 includes a first flip-flop FF1, a second flip-flop FF2, an AND logic operator AND, and an OR logic OR.

Each of the first flip-flop FF1 and the second flip-flop FF2 is a positive edgge triggered D flip-flop. The data line 500 is connected to the clock terminal CLK of the first flip-flop FF1. Therefore, when the reception clock signal applied to the data line 500 rises in the blank period, 1 is outputted. When the output of the logical sum operator OR applied to the reset terminal RS becomes 1, 0 is outputted. The second flip-flop FF2 outputs 1 when the feedback clock signal FC applied to the clock terminal CLK rises, and when the output of the logical sum operator OR applied to the reset terminal RS becomes 1. Output 0. The AND operator AND performs an AND operation on the outputs of the first and second flip-flops FF1 and FF2, and the OR operator OR outputs and an active signal ACT of the AND operator AND. ) Is performed on the OR operation.

The phase detector 251 shown in FIG. 7 is configured in this manner, and when the active signal becomes zero (a blank period), the phase difference between the signal (receive clock signal) transmitted through the data line 500 and the feedback clock signal Outputs a signal corresponding to In addition, when the active signal becomes 1 (active period), the phase detector 251 has no phase difference regardless of the phase difference between the signal (received signal) transmitted through the data line 500 and the feedback clock signal FC. Outputs a signal (UP = 0, DN = 0).

In the above-described embodiment of the present invention, the clock information is not transmitted from the timing controller 100 to the data driver 200 in the active period. Therefore, there is a risk that the sampling clock signal CLK_SAM is shifted from the received signal in this period so that accurate sampling is not performed. In order to prevent such a risk, clock information may be transmitted through the data line 500 even during an active period. For example, a transmission signal having a periodic transition may be transmitted.

8 is a diagram for explaining a transmission clock signal and a transmission signal when the transmission signal has a periodic transition. FIG. 8A illustrates an example of a signal, an active signal ACT, and data bits DATA_BIT transmitted to the data line 500 in a blank period, and FIG. 8B illustrates data in an active period. FIG. 4 is a diagram illustrating an example of a signal, an active signal ACT, and data bits DATA_BIT transmitted through the line 500.

Referring to FIG. 8A, a periodic transmission clock signal is transmitted through the data line 500 in the blank period.

Referring to FIG. 8B, a transmission signal is transmitted through the data line 500 in the active period. The transmission signal has a periodic transition. The period of the periodic transition may be the same as the period of the transmit clock signal, for example, as represented in the figure. Unlike the figure, the period of the periodic transition may be an integer multiple of the period of the transmission clock signal, and the period of the transmission clock signal may also be an integer multiple of the period of the periodic transition. Periodic transitions are caused by dummy bits inserted periodically. For example, the dummy bit may have a value different from that of the data bit immediately before the dummy bit as shown in the figure. Unlike the figure, the dummy bit may have a value different from the data bit immediately after the dummy bit. In addition, the periodic transition may be caused by two bits of dummy bits inserted periodically. In this case, the dummy bits have a fixed value (ie 01 or 10).

In order for the timing controller 100 to output a transmission signal having a periodic transition, the serial converter 160 of FIG. 4 may output dummy bits first, and then sequentially output data bits input in parallel. In this case, the dummy bit has a value corresponding to the inversion of the last bit among the data bits output immediately before.

In order for the data driver 200 to generate the sampling clock according to the reception clock signal and the periodic transition of the reception signal, the data driver 200 may include the clock generator 250 illustrated in FIG. 6 and the phase detector illustrated in FIG. 7. Instead of 251, the clock generator 250 shown in FIG. 9 and the transition detector 251A shown in FIG. 10 may be used.

9, the clock generator 250 includes a transition detector 251A, a low pass filter 252, a delay line 253, a feedback line 254, a switch 255, and an enable signal generator ( 256).

The transition detector 251A outputs signals UP and DN corresponding to the phase difference between the reception clock signal and the feedback clock signal FC in the blank period, and the periodic transition and feedback clock signal FC of the reception signal in the active period. Signal (UP, DN) corresponding to the time difference between transitions As the transition detector 251A calculates a time difference between the transition of the received signal and the transition of the feedback clock signal FC, the transition and the feedback of the period during which the enable signal EN is applied among the various transitions of the received signal. The transition of the period in which the enable signal EN is applied is used among the various transitions of the clock signal FC.

The enable signal generator 256 generates the enable signal EN to enable the transition detector 251A to operate according to a periodic transition caused by a dummy bit among several transitions of the received signal. Accordingly, the transition detector 251A is a time between the transition of the received signal input in the period when the enable signal EN is applied and the transition of the feedback clock signal FC input in the period during which the enable signal EN is applied. Get a car. In addition, the transition detector considers the transition of the received signal input in the period when the enable signal EN is not applied and the transition of the feedback clock signal FC input in the period when the enable signal EN is not applied. Not.

Assuming a time point at which the periodic transition is performed is T3, and a period corresponding to a data bit or a dummy bit of 1 bit of the received signal is T1, preferably, T_START, which is a start point of the enable signal, and an end point of the enable signal, T_END satisfies Equation 1 below.

T3-T1 <T3_START <T

T3 <T_END <T3 + T1

If the start time T_START is less than or equal to [T3-T1] or the end time T_END is more than or equal to [T3 + T1], within a period during which the enable signal EN is applied, the reception signal other than the periodic transition There are unwanted transitions. In addition, when the start time T_START is greater than T3 or the end time T_END is less than T3, there is no periodic transition in the period during which the enable signal EN is applied.

The enable signal generator 256 generates the enable signal EN according to at least one of various delay clocks that can be obtained from the delay line 253. In the drawing, an example in which the enable signal generator 256 receives the first delayed clock DC1 output from the first inverter I1 and the seventeenth delayed clock DC17 output from the seventeenth inverter I17 is represented. have. The first delayed clock DC1 is a signal in which the inversion of the feedback clock signal FC is delayed by (T1 / 2), and the 17th delayed clock DC17 is an inversion of the feedback clock signal FC-(T1 / 2). As long as the signal is delayed. The enable signal generator 42 includes an inverter INV and an AND operator AND to generate the enable signal EN from the first delay clock DC1 and the seventeenth delay clock DC17.

The delay of the delay line 253 is changed according to the signal DIFF output from the low pass filter 252. Delay line 253 includes a plurality of inverters I1-I18. The delay of each of the plurality of inverters I1-I18 is adjusted according to the signal DIFF output from the low pass filter 252. Each of the plurality of inverters I1 to I18 has a delay corresponding to approximately (T1 / 2). Third, fifth, fifth, seventh, ninth, eleventh, thirteenth, fifteenth, and seventeenth inverters I3, I5, I7, I9, I11, I13, I15, and I17 respectively outputted from the third and fifth. The seventh, ninth, eleventh, thirteenth, fifteenth, and seventeenth delayed clocks DC3, DC5, DC7, DC9, DC11, DC13, DC15, and DC17 are output to the sampler 240 as sampling clock signals.

Since the operations of the low pass filter 252, delay line 254 and switch 255 are the same as those of FIG. 6, detailed description thereof will be omitted for convenience of description.

Referring to FIG. 10, the transition detector 251A includes first to third flip-flops FF1, FF2, and FF3, first and second switches SW1 and SW2, and first and second logical sum operators OR1 and OR2. ), A logical AND (AND) and an inverter (INV).

The first flip-flop FF1 is a positive edgge triggered D flip-flop. The input terminal D, the clock terminal CLK, and the reset terminal RS of the first flip-flop FF1 have a signal corresponding to bit '1' (for example, a power supply voltage VDD) and a data line 500. Signals (received clock signals or received signals) applied through and the outputs of the second OR gate OR2 are respectively input. Therefore, the first flip-flop FF1 outputs '0' after the output of the second logical OR operator OR2 becomes '1'. The first flip-flop FF1 outputs '1' after the rising edge of the received signal occurs in the state where the output of the second logical OR operator OR is '0'.

The second flip-flop FF2 is a negative edgge triggered D flip-flop. A signal corresponding to bit '1' and a signal applied through the data line 500 to the input terminal D, the clock terminal CLK, and the reset terminal RS of the second flip-flop FF2 (a received clock signal). Or a received signal) and the outputs of the second AND operator OR2 are respectively input. Therefore, the second flip-flop FF2 outputs '0' after the output of the second logical OR operator OR2 becomes '1'. The second flip-flop FF2 outputs a '1' after a falling edge of the received signal occurs while the output of the second logical OR operator OR is '0'.

The third flip-flop FF3 is a positive edgge triggered D flip-flop. The input terminal D, the clock terminal CLK, and the reset terminal RS of the third flip-flop FF3 have a signal corresponding to bit '1', a feedback clock signal FC, and a second logical OR operator OR2. Are respectively inputted. Therefore, the third flip-flop FF3 outputs '0' after the output of the second logical OR operator OR2 becomes '1'. The third flip-flop FF3 outputs '1' after the rising edge of the feedback clock signal FC occurs in the state where the output of the second OR gate is '0'.

The first switch SW1 outputs 0 in the blank period and outputs the output of the second flip-flop FF2 in the active period. The second switch outputs 1 in the blank period and outputs the enable signal EN in the active period. The first logical sum operator OR receives an output of the first flip-flop FF1 and an output of the first switch SW1. The second OR operation OR2 receives an output of the inverter INV and an output of the AND product AND. The AND product AND receives the output of the first AND operator OR1 and the output of the third flip-flop FF3. The inverter INV receives the output of the second switch SW2.

1 is a view for explaining the prior art PPDS method.

2 is a view schematically illustrating a structure of a display according to a first embodiment of the present invention.

FIG. 3A illustrates an example of a signal, an active signal ACT, and data bits DATA_BIT transmitted to the data line 500 in a blank period, and FIG. 3B illustrates data in an active period. FIG. 4 is a diagram illustrating an example of a signal, an active signal ACT, and data bits DATA_BIT transmitted through the line 500.

4 is a diagram illustrating an example of the timing controller 100 illustrated in FIG. 2.

FIG. 5 is a diagram illustrating an example of the data driver 200 illustrated in FIG. 2.

FIG. 6 is a diagram illustrating an example of the clock generator 250 illustrated in FIG. 5.

FIG. 7 is a diagram illustrating an example of the phase detector 251 employed in FIG. 6.

8 is a diagram for explaining a transmission clock signal and a transmission signal when the transmission signal has a periodic transition.

9 is a diagram illustrating an example of a clock generator 250 used in the data driver 200 when the transmission signal has a periodic transition.

FIG. 10 is a diagram showing an example of the transition detector 251A used in the clock generator 250 when the transmission signal has a periodic transition.

Claims (19)

Data line; A timing controller for applying a transmission signal corresponding to the data bits to the data line in an active period for transmitting data bits, and applying a transmission clock signal to the data line in a blank period for not transmitting the data bits; And A data driver configured to recover the data bits by sampling the transmission signal (hereinafter referred to as a reception signal) transmitted through the data line, and to drive a display panel according to the restored data bits. Display with. delete According to claim 1, And the transmission signal has a periodic transition. According to claim 1, And the data driver is configured to sample the data bits according to a sampling clock signal, the sampling clock signal being generated in accordance with the transmit clock signal transmitted to the data driver through the data line. According to claim 1, And the timing controller transmits an active signal to the data driver indicating whether the timing period is the active period or the blank period. A serializer for generating serialized transmission bits corresponding to the data bits; A clock generator for generating a transmission clock signal; And A multiplexer which outputs the transmission bits in an active period for transmitting the data bits and outputs the transmission clock signal in a blank period in which the data bits are not transmitted Timing control unit having a. delete The method of claim 6, And said transmit bit has a periodic transition. A clock generator for generating a sampling clock signal according to a received clock signal, the received clock signal being transmitted through the data line in a blank period in which no data bits are transmitted; And A sampler for reconstructing data bits included in the received signal by sampling a received signal according to the sampling clock signal, the received signal being transmitted through the data line in an active period in which data bits are transmitted. Data driver comprising a. delete The method of claim 9, And the clock generator changes a phase of the sampling clock signal in the blank period and maintains a phase of the sampling clock signal in the active period. The method of claim 9, The clock generator may include: a phase detector configured to detect a phase difference between the received clock signal and a feedback clock signal in a blank period; And a delay is changed according to a signal corresponding to the detected phase difference, and outputs the feedback clock signal and the sampling clock signal, and receives the received clock signal in the blank period and receives the feedback clock signal in the active period. A data driver having a delay line receiving an input. The method of claim 9, The data driver has a periodic transition. The method of claim 13, And the clock generator changes a phase of the sampling clock signal according to the received clock signal during the blank period, and changes the phase of the sampling clock signal according to the periodic transition during the active period. The method of claim 9, And a data driver receiving an active signal indicating whether the blank period is active or the active period. A method of transmitting data bits from a timing controller to a data driver via a data line, the method comprising: (a) transmitting a transmit clock signal over the data line in a blank period during which the data bits are not transmitted; And (b) transmitting a transmission signal corresponding to the data bits through the data line in an active period during which the data bits are transmitted; Method of providing. delete The method of claim 16, The transmission signal has a periodic transition. The method of claim 16, Wherein the transmit signal and the transmit clock signal are transmitted in single-ended signaling or differential signaling.

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