JP2006215087A - Serial data transmitting and receiving apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a serial data transmitting and receiving apparatus reducing power consumption. <P>SOLUTION: The serial data transmitting and receiving apparatus is equipped with: a parallel/serial converter 1; an LDVS (low voltage differential signaling) signal transmitter 2; an LDVS signal receiver 3; a transmission line 4; a non-display detector 5 as a non-display period detector; and an output controller 6. The non-display detector 5 outputs an output control signal as a non-display period detecting signal to the output controller 6 by detecting a non-display period T1 of an input data signal RGB on the basis of inputted control signals (a data enable signal DE, a vertical synchronous signal VSYNC, and a horizontal synchronous signal HSYNC). Thereafter, the output controller 6 controls the transmitter 2 on the basis of the output control signal to reduce the transmission output level of the transmitter 2 in the non-display period T1 as compared with a display period T2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transmission / reception device. As an example, an FPD (flat panel display) panel interface represented by a large LCD (liquid crystal display) panel that requires high speed operation and low power consumption, an LCD timing controller, and an LCD The present invention relates to a serial data transmission / reception device that is useful for reducing power consumption of an LCD module and for power management when used for an interface with a drive element.

  Conventionally, LVDS (Low Voltage Differential Signaling) for high-speed transmission of small amplitude signals is used as an interface between LCD panels or between a display timing controller LSI and an LCD driving LSI in an LCD module. Many are used.

  FIG. 11 shows an LVDS transmission / reception apparatus. In this LVDS transmission / reception apparatus, a signal voltage generated at the transmission unit 101 is passed through a loop formed by the balanced transmission line 102 and the termination resistor 104 of the reception unit 103, thereby generating a signal voltage at both ends of the termination resistor 104. To transmit the signal. This is a feature of the LVDS transmission / reception apparatus.

  FIG. 12 shows a circuit configuration of the transmission unit 101 of the LVDS transmission / reception apparatus. In FIG. 12, N11 and N12 are NMOS transistors as current switching elements on the + potential side of LVDS, and N13 and 14 are NMOS transistors as current switching elements on the −potential side of LVDS.

  The source of the NMOS transistor N11 and the drain of the NMOS transistor N13 are connected, and the NMOS transistors N11 and N13 are connected in series. Similarly, the source of the NMOS transistor N12 and the drain of the NMOS transistor N14 are connected, and the NMOS transistors N12 and N14 are connected in series. The drains of the NMOS transistors N11 and N12 are connected to the current source I11, and the sources of the NMOS transistors N13 and N14 are both connected to the current sink I12.

  On the other hand, the CMOS inverters INV11 and INV12 generate a signal S for driving the NMOS transistor N11 on the + potential side of the LVDS and the NMOS transistor N14 on the −potential side of the LVDS, and the NMOS transistors N12 and LVDS on the + potential side of the LVDS. -The inversion signal SB of the signal S for driving the NMOS transistor N13 on the potential side is generated.

  That is, the CMOS inverters INV11 and 12 output the CMOS input signal as the normal phase control signal S and input it to the gates of the NMOS transistors N11 and N14, while the CMOS inverter INV11 outputs the reverse phase control signal SB of the CMOS input signal. And input to the gates of the NMOS transistors N12 and N14.

  Therefore, if the CMOS input signal is “H”, the normal phase control signal S is “H” and the negative phase control signal SB is “L”. In this case, the NMOS transistors N11 and N14 are turned on, while the NMOS transistors N12 and N13 are turned off. Then, the current flows from the current source I11 through the NMOS transistor N11, the wiring 102A, the termination resistor 104, and the wiring 102B, through the NMOS transistor N14, and to the current sink I12. At this time, the LVDS output from the transmission unit 101 to the balanced transmission path 102 is “H”.

  On the other hand, if the CMOS input signal is “L”, the positive phase control signal S is “L”, the negative phase control signal SB is “H”, and the NMOS transistors N12 and N13 are turned on, while the NMOS transistors N11 and N14 are turned on. Turns off. The current flows from the current source I11 through the NMOS transistor N12, the wiring 102B, the termination resistor 104, and the wiring 102A, through the NMOS transistor N13 to the current sink I12. At this time, the LVDS output signal from the transmission unit 101 to the balanced transmission path 102 is “L”.

  Normally, in LVDS, the current value is set to about 3.5 mA, and the termination resistor 104 is set to 100Ω, so the LVDS amplitude is 350 mV at 3.5 mA × 100Ω.

  As described above, the transmission unit 101 has a configuration as shown in FIG. 12. Therefore, regardless of whether the input CMOS signal is “H” or “L”, the transmission unit 101 is connected between the power supply and GND during normal operation. Constant current is flowing. For this reason, if the number of pairs of the transmission unit 101 and the reception unit 103 in the LVDS transmission / reception apparatus increases and the number of balanced transmission path 102 pairs increases, the current consumption increases by that number.

  Next, referring to FIG. 14, a transmission method in a liquid crystal display device will be described as an example of an LVDS transmission method. FIG. 14 shows a display system in a transmission system in this liquid crystal display device. In FIG. 14, 207 is a liquid crystal panel as an FPD (flat panel display) panel, 208 is an RSDS transmission / reception unit, and 209 is an FPD panel module.

  In this display system, image data is transferred from the transmission unit 201 to the reception unit 203 via the balanced transmission path 202 by the LVDS method, and is input to the timing controller 205.

  The timing circuit for LCD display is generated by the logic circuit of the timing controller 205, and this timing signal and the image data (display data) are supplied to a driving LSI (not shown) of the liquid crystal panel 207 constituting the FPD panel. Is done. As for the signal supply to the driving LSI, it is mainly transmitted by the LVDS method.

  Here, an LVDS (RSDS) transmission method between the timing controller 205 in the liquid crystal display device described above and the driving LSI of the liquid crystal panel will be described.

  In this transmission method, transmission between the timing controller 205 and the source driver of the liquid crystal panel 207 shown in FIG. 14 is performed as RSDS (Reduced Swing Differential Signaling). This RSDS transmission method can be expected to have a high speed and low EMI (electromagnetic interference) effect as compared with conventional CMOS signal transmission. “RSDS” is a method devised by National Semiconductor Corporation of the United States and is a registered trademark of the company.

  This RSDS transmission method is a technique for converting 2 bits of a parallel CMOS signal into serial data and further transmitting it as an RSDS signal.

  In this RSDS transmission method, the RSDS transmission / reception unit 208 shown in FIG. 14 transmits a parallel 2-bit signal received from the timing controller 205 to the transmission path 210 as serial data. The transmission is transmitted at the timing of taking in the serial data at both rising and falling edges of the clock signal.

  As a configuration of this transmission system, the transmission / reception unit 208 on the timing controller side is a transmission unit, and the liquid crystal driving LSI of the liquid crystal panel 207 connected to the transmission unit is a reception unit.

  Further, the wiring on the printed board between the timing controller 205 and the liquid crystal driving LSI corresponds to the transmission path 210. In the RSDS transmission method, the signal level and the transmission method are the same as those in the LVDS method, and the circuit configuration of the transmission unit is shown in FIG. As shown in FIG. 13, a CMOS signal is supplied to the input of the transmitter, the transmitter and the receiver are connected in a differential pair, and a 100Ω termination resistor 104 is connected between the differential pair. Is done. Thus, by connecting the termination resistor 104, a current loop is formed, and a voltage is generated across the termination resistor 104.

  In the RSDS transmission method, the constant current value of the transmission unit is set to 2 mA, and a current of 2 mA flows on the formed current loop. Voltages of +200 mV and −200 mV are respectively applied to both ends of the termination resistor 104. Will occur.

  If the data is fixed to “H” and “L”, the current is almost “0” in the CMOS method, but the input data is fixed to “H” and “L” in the transmitter in this LVDS method. Even if it is done, current will continue to flow constantly.

  On the actual liquid crystal panel, assuming that the image data RGB is 8 bits each, RSDS pairs of 12 data pairs and 1 clock pair are formed in total 13 RSDS transmission pairs.

  The current that flows in one pair of RSDS is 2 mA, and when 13 pairs are formed, a current of 26 mA is simply consumed. Now, the constant current setting is 2 mA. However, when the load on the transmission line connecting the receiving unit and the transmitting unit is increased and the RSDS signal amplitude is attenuated, the transmitting unit is further set to increase the amplitude. It is necessary to adjust so as to increase the current value and increase the amplitude. This can lead to a further increase in current consumption.

By the way, as described above, when the CMOS data input to the transmission unit is fixed to “H” and “L”, the current is almost “0” in the case of the CMOS method. Then, even if the input data is fixed to “H” and “L”, the current continues to flow constantly. This is because even when the input data input to the transmission unit is not display data, that is, when the input data is data that is not necessary to be irrelevant to the display, the current continues to flow through the transmission unit. Means. At the present time when there is a further demand for lower power consumption, it is important and important to reduce unnecessary power in the system configuration.
“RSDSTM“ Intra-panel ”Interface Specification Revision 1.0, May 2003, published by National Semiconductor Corporation”

  Accordingly, an object of the present invention is to provide a serial data transmitting / receiving apparatus capable of reducing power consumption.

In order to solve the above problems, a serial data transmitting / receiving device of the present invention includes a transmission line,
A parallel data signal is input and the parallel data signal is converted into a plurality of differential serial data signals and transmitted to the transmission path;
A receiver that receives the differential serial data signal from the transmitter via the transmission path;
A termination resistor inserted into the transmission path for transmitting the differential serial data and forming a current loop with the transmitter;
The amplitude of the differential serial data signal is determined by the current value flowing through the current loop,
The parallel data signal includes a display data signal mapped to the differential serial data signal, a synchronization signal, and a data enable signal.
At least one of the synchronization signal and the data enable signal is input and, based on the state of at least one of the synchronization signal and the data enable signal, detects a non-display period in the display data signal and outputs a non-display period detection signal A non-display period detection unit to perform,
A non-display period detection signal output from the non-display period detection unit, and an output control unit that controls a transmission output level of the transmission unit based on the non-display period detection signal. .

  According to the serial data transmission / reception device of the present invention, the non-display period detection unit detects the display data signal included in the parallel data signal based on at least one state of the synchronization signal or the data enable signal included in the parallel data signal. A non-display period is detected and a non-display period detection signal is output. And an output control part controls the transmission output level of the said transmission part based on the said non-display period detection signal.

  Therefore, according to the present invention, during the non-display period of the display data signal input to the transmission unit, the output control unit reduces the transmission output level of the transmission unit based on the non-display period detection signal. Therefore, it is possible to avoid unnecessary power consumption by the transmitter, and to reduce power consumption.

  The serial data transmission / reception apparatus according to an embodiment receives the non-display period detection signal and controls the transmission unit based on the non-display period detection signal, so that a differential serial data signal to the transmission path is obtained. A transmission stop unit for stopping the transmission of.

  According to the serial data transmitting / receiving apparatus of this embodiment, the transmission stop unit controls the transmission unit based on the non-display period detection signal to stop transmission of the differential serial data signal to the transmission path. Therefore, since the transmission stopping unit stops transmission by the transmitting unit during a non-display period of the display data signal input to the transmitting unit, the power consumption can be further reduced.

In the serial data transmission / reception apparatus according to one embodiment, the data enable signal is
A signal that becomes active or inactive in response to whether the display data signal is a signal corresponding to a display period or a signal corresponding to a non-display period;
The non-display period detection unit
A non-display period in the display data signal is detected based on the data enable signal.

  According to the serial data transmitting / receiving apparatus of this embodiment, the non-display period detection unit is configured to display the non-display data signal by the data enable signal that becomes active or inactive corresponding to the display period and the non-display period of the display data signal. The display period can be reliably detected. Therefore, according to this embodiment, the non-display period detection unit can reliably reduce the output level of the transmission unit and can reliably reduce power consumption during the non-display period of the display data signal.

Further, in the serial data transmitting / receiving device of one embodiment, the synchronization signal includes a horizontal synchronization signal,
The non-display period detection unit
A counter that counts the number of clocks of the clock signal from when the horizontal synchronization signal becomes active to when the data enable signal becomes active while a predetermined clock signal is input;
The count period by the counter is detected as a non-display period in the display data signal.

  According to the serial data transmitting / receiving apparatus of this embodiment, the non-display period detection unit can detect the non-display period of the display data signal by the horizontal synchronization signal included in the synchronization signal, and the output of the transmission unit in the non-display period The level can be reliably reduced, and the power consumption can be reliably reduced.

Further, in the serial data transmitting / receiving apparatus according to an embodiment, the synchronization signal includes a vertical synchronization signal, and the non-display period detection unit includes:
A counter that counts the number of clocks of the clock signal from when the vertical synchronization signal becomes active to when the data enable signal becomes active while a predetermined clock signal is input;
The count period by the counter is detected as a non-display period in the display data signal.

  According to the serial data transmitting / receiving apparatus of this embodiment, the non-display period detection unit can detect the non-display period of the display data signal by the vertical synchronization signal included in the synchronization signal, and the output of the transmission unit in the non-display period The level can be reliably reduced, and the power consumption can be reliably reduced.

  In one embodiment, the semiconductor integrated circuit includes a differential small amplitude signal interface system including the non-display period detection unit and the output control unit included in the serial data transmission / reception device.

  According to the semiconductor integrated circuit of this embodiment, the non-display period detection unit detects the non-display period of the display data signal based on at least one of the synchronization signal or the data enable signal included in the parallel data signal and does not display it. A period detection signal is output. Then, the said output control part can control the transmission output level of the transmission part of a serial data transmitter / receiver based on the said non-display period detection signal. Therefore, it can be avoided that the transmission unit consumes unnecessary power during the non-display period, and power consumption can be reduced.

  According to the serial data transmission / reception device of the present invention, the non-display period detection unit detects the display data signal included in the parallel data signal based on at least one state of the synchronization signal or the data enable signal included in the parallel data signal. A non-display period is detected and a non-display period detection signal is output. And an output control part controls the transmission output level of the said transmission part based on the said non-display period detection signal.

  Therefore, according to the present invention, during the non-display period of the display data signal input to the transmission unit, the output control unit reduces the transmission output level of the transmission unit based on the non-display period detection signal. Therefore, it is possible to avoid unnecessary power consumption by the transmitter, and to reduce power consumption.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 shows an LVDS (differential small amplitude signal transmission system) transmitter / receiver as a first embodiment of a serial data transmitter / receiver of the present invention. This embodiment includes a parallel / serial converter 1, an LVDS signal transmitter 2, an LVDS signal receiver 3, a transmission path 4, a non-display detector 5 as a non-display period detector, and an output controller 6. The parallel / serial converter 1 and the LVDS signal transmitter 2 form a transmission unit.

  The transmission line 4 has a pair of wires LVDS + and LVDS−. The wires LVDS + and LVDS− are connected by a terminating resistor R10 at the end on the receiver 3 side.

  The circuit configuration of the LVDS signal transmitter 2 is shown next to the output controller 6 in FIG. The circuit configuration of the transmitter 2 is the same as that of the conventional transmitter 101 shown in FIG. 12, except that the output controller 6 is interposed between the CMOS inverters INV11 and INV12 and the NMOS transistors N1 and N3. Is the same.

  That is, the transmitter 2 has NMOS transistors N1 to N4. The source of the NMOS transistor N1 and the drain of the NMOS transistor N3 are connected. The drain of the NMOS transistor N1 is connected to the current source I1, and the source of the NMOS transistor N3 is connected to the current sink I2. Further, the source of the NMOS transistor N2 and the drain of the NMOS transistor N4 are connected. The drain of the NMOS transistor N2 is connected to the current source I1, and the source of the NMOS transistor N4 is connected to the current sink I2.

  The gate of the NMOS transistor N1 is connected to the gate of the NMOS transistor N4, and the gate of the NMOS transistor N2 is connected to the gate of the NMOS transistor N3. The connection point between the source of the NMOS transistor N1 and the drain of the NMOS transistor N3 is connected to the wire LVDS + of the transmission line 4, and the connection point between the source of the NMOS transistor N2 and the drain of the NMOS transistor N4 is a wire of the transmission line 4. Connected to LVDS-.

  Further, the gate of the NMOS transistor N1 is connected to the output side of the inverter Inv12 via the output controller 6, and the gate of the NMOS transistor N3 is connected to the connection point between the inverter Inv11 and the inverter Inv12 via the output controller 6. Has been. A differential serial data signal (CMOS input data) from the parallel / serial converter 1 is input to the input side of the inverter Inv11.

  The transmitter 2 converts the CMOS input signal into a current signal and transmits it to the transmission line 4. A current loop is formed by the 100Ω termination resistor R10 connected between the pair of wires LVDS + and LVDS− of the transmission line 4, and a voltage signal is obtained at both ends of the termination resistor R10.

  As shown in FIG. 6, the output controller 6 includes an inverter Inv13, an NMOS transistor N41, a PMOS transistor P41, a PMOS transistor P42, an NMOS transistor N42, an NMOS transistor N43, and an NMOS transistor N44.

  The input side of the Inv 13 is connected to an input terminal to which an output control signal from the non-display detector 5 is input. The drain of the NMOS transistor N41 and the source of the PMOS transistor P41 are connected, and the source of the NMOS transistor N41 and the drain of the PMOS transistor P41 are connected. The connection point between the drain of the NMOS transistor N41 and the source of the PMOS transistor P41 is connected to the output side of the inverter Inv12, and the connection point between the source of the NMOS transistor N41 and the drain of the PMOS transistor P41 is connected to the transmitter 2 via the connection line L31. Is connected to the gate of the NMOS transistor N1. The gate of the PMOS transistor P41 is connected to the input side of the inverter Inv13, and the gate of the NMOS transistor N41 is connected to a connection line L32 connected to the input terminal.

  The source of the PMOS transistor P42 is connected to the drain of the NMOS transistor N42, and the drain of the PMOS transistor P42 is connected to the source of the NMOS transistor N42. A connection point between the source of the PMOS transistor P42 and the drain of the NMOS transistor N42 is connected to a connection point between the inverter Inv11 and the inverter Inv12. The connection point between the drain of the PMOS transistor P42 and the source of the NMOS transistor N42 is connected to the gate of the NMOS transistor N3 of the transmitter 2 by a connection line L33. The gate of the PMOS transistor P42 is connected to the output side of the inverter Inv13, and the gate of the NMOS transistor N42 is connected to the connection line L32.

  The NMOS transistor N43 has a gate connected to the connection line L34, a drain connected to the connection line L31, and a source connected to the ground. The NMOS transistor N44 has a gate connected to the connection line L34, a drain connected to the connection line L33, and a source connected to the ground.

  An output control signal as a non-display detection signal output from the non-display detector 5 is input to the output controller 6, and the output controller 6 transmits the transmission output level of the transmitter 2 based on the output control signal. To control.

  The parallel-serial converter 1 receives an input data signal RGB as a display data signal, a data enable signal DE, a horizontal synchronization signal HSYNC, and a vertical synchronization signal VSYNC as parallel data signals. The parallel-serial converter 1 converts the input data signal RGB, the data enable signal DE, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC that have been input into a plurality of differential serial data signals, and outputs them to the transmitter 2. To do. The transmitter 2 transmits the differential serial data signal input from the parallel / serial converter 1 to the transmission path 4. The differential serial data signal is transmitted through the transmission path 4 and received by the receiver 3.

  The non-display detector 5 receives the data enable signal DE, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC. The non-display detector 5 detects a non-display period of the input data signal RGB as the display data signal based on at least one of the signal DE, the signal HSYNC, and the signal VSYNC. The output control signal is output. This non-display period detection signal is input to the output controller 6. The output controller 6 controls the transmission output level of the transmitter 2 based on the output control signal as the non-display period detection signal.

  That is, the non-display detector 5 detects the non-display period T1 of the input data signal RGB based on the input control signals (data enable signal DE, vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC) and An output control signal as a display period detection signal is output to the output controller 6. Then, the output controller 6 controls the transmitter 2 based on the output control signal as the non-display period detection signal, and the transmission output of the transmitter 2 is compared with the display period T2 in the non-display period T1. Reduce the level. Thereby, it can avoid that the transmitter 2 consumes useless electric power in the non-display period T1, and power consumption can be reduced.

  Here, the operation of the output controller 6 will be described in more detail with reference to FIG. First, when the non-display detector 5 sets the output control signal to “H” during the display period T2 of the input data signal RGB, the PMOS transistor P41, NMOS transistor N41, PMOS transistor P42 and NMOS transistor N42 of the output controller 6 are displayed. Is turned on, and NMOS transistors N43 and N44 are turned off. As a result, the inverters Inv11 and Inv12 are electrically connected to the NMOS transistor N3 and the NMOS transistor N1 of the transmitter 2, respectively, so that the transmitter 2 is in a normal operation state.

  On the other hand, when the non-display detector 5 sets the output control signal to “L” during the non-display period T1 of the input data signal RGB, the PMOS transistor P41, the NMOS transistor N41, the PMOS transistor P42, and the NMOS transistor of the output controller 6 While N42 is turned off, NMOS transistors N43 and P44 are turned on. As a result, the inverters Inv11 and Inv12 become non-conductive to the NMOS transistor N3 and the NMOS transistor N1 of the transmitter 2, and the NMOS transistors N1 to N4 of the transmitter 2 are turned off. Thereby, it can avoid that the transmitter 2 consumes useless electric power in the non-display period T1, and power consumption can be reduced.

(Second embodiment)
Next, FIG. 2 shows an LVDS interface system as a second embodiment of the serial data transmitting / receiving apparatus of the present invention.

  The second embodiment includes a transmission unit T and a reception unit R, and four pairs of transmission paths 24-1 to 24-4 that connect the transmission unit T and the reception unit R. Each of the four pairs of transmission lines 24-1 to 24-4 has a termination resistor R10.

  The transmitter T includes a parallel / serial converter 21, a PLL (phase locked loop) circuit 22, a non-display detector 25, an output controller 26, and four LVDS transmitters 27-1 to 27-4. The input sides of the three LVDS transmitters 27-1 to 27-3 are connected to the parallel / serial converter 21, and the output sides of the three LVDS transmitters 27-1 to 27-3 are respectively three transmission lines. 24-1 to 24-3. On the other hand, the input side of the LVDS transmitter 27-4 is connected to the PLL circuit 22, and the output side is connected to the transmission line 24-4.

  The input side of the non-display detector 25 is connected to the input line L1, and the output side of the non-display detector 25 is connected to the output controller 26. The output side of the output controller 26 is connected to the input side of the LVDS transmitters 27-1 and 27-2. The input line L1 and the input line L2 are connected to the input side of the parallel / serial converter 21, and the output side of the converter 21 is connected to the input side of the LVDS transmitters 27-1 to 27-3. Has been. A 3-bit control signal is input to the input line L1, and a 6-bit input data signal RGB is input to the input line L2 as a display data signal. The 3-bit control signal includes a data enable signal DE, a horizontal synchronization signal HSYNC, and a vertical synchronization signal VSYNC.

  The PLL circuit 22 has an input side connected to the input line L3 and an output side connected to the LVDS transmitter 27-4. The PLL circuit 22 is also connected to the parallel / serial converter 21. A 1-bit clock signal CLK is input to the input line L3.

  Further, the transmission unit T includes a non-display detector 25 as a non-display period detection unit and an output controller 26 as an output control unit. The non-display detector 25 has an input terminal connected to the input line L 1 and an output terminal connected to the input terminal of the output controller 26. The output terminal of the output controller 26 is connected to the input side of the LVDS transmitters 27-1 and 27-2.

  On the other hand, the receiving unit R includes four LVDS signal receivers 30-1 to 30-4, a serial / parallel converter 31, and a PLL circuit 32. The four LVDS signal receivers 30-1 to 30-4 are connected to the four transmission lines 24-1 to 24-4, respectively. The receivers 30-1 to 30-3 are connected to the serial / parallel converter 31, and the receiver 30-4 is connected to the PLL circuit 32.

  The output of the PLL circuit 32 is connected to the output line L03, and the clock signal CLK is output to the output line L03. The serial / parallel converter 31 is connected to output lines L01 and L02. The serial / parallel converter 31 outputs a 3-bit control signal including the data enable signal DE, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC to the output line L01, and outputs the input data signal RGB to the output line L02.

  Next, the operation of the second embodiment will be described with reference to the timing charts of FIGS. 5A to 5C. FIG. 5B is an enlarged view showing in detail the input data R0 to R5, G0 to G5, and B0 to B5 forming the input data signal RGB shown in FIG. 5A. 5C shows the horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC, and the data enable signal DE shown in FIG. 5A in an enlarged manner, and the input data signal RGB, the horizontal synchronization signal HSYNC, and the vertical synchronization signal that are parallel data signals. LVDS data signals CH1 to CH3, which are serial data signals obtained by parallel-serial conversion of VSYNC and data enable signal DE, are shown.

  The horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC, the data enable signal DE, the input data signal RGB, and the clock signal CLKIN are input lines L1, L2, and L3 connected to the transmission unit T at the timing shown in FIG. 5A, respectively. Is input.

  In the parallel / serial converter 21 of the transmission unit T, a total of 21 comprising an RBG signal (6 bits (bit) × 3 = 18 bits (bit)), a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, and a data enable signal DE. The bit parallel data signal is serialized in one rate of the clock signal CLKIN by 7 bits and output to the transmitters 27-1 to 27-3.

  In the transmitters 27-1 to 27-3, the serialized CMOS level signal input from the parallel / serial converter 21 is converted into LVDS data signals CH 1 to CH 3 which are differential serial data signals of LVDS level, and The data is transmitted to the receiving unit R via the transmission lines 24-1 to 24-3.

  At this time, the transmitters 27-1 to 27-3 transmit the three-channel LVDS data signals CH1 to CH3 to the receiving unit R, and the transmitter 27-4 transmits the one-channel LVDS clock signal LVCLK through the transmission line 24-4. To the receiving unit R. Therefore, the signal transmitted from the transmission unit T to the reception unit R has a total of four channels.

  Here, the data mapping when serializing parallel data signals is generally as shown in FIG. 5C. The transmission unit T of the LVDS interface system according to the second embodiment serializes the input parallel data signal by 7 bits, converts the 7-bit serialized serial data signal to the LVDS level, and transmits the serial data signal to the reception unit R. To do.

  On the other hand, the receiving unit R receives the LVDS data signals CH1 to CH3 and the LVDS clock signal LVCLK transmitted from the transmitting unit T, and parallelizes the received signals. That is, the receiving unit R performs an operation of returning the serial signal received from the transmitting unit T to a parallel signal such as an input signal to the transmitting unit T again.

  The transmitters 27-1 to 27-3 of the transmission unit T convert the signals P / S (parallel / serial) converted by the parallel / serial converter 21 into LVDS levels, and transmit the transmission lines 24-1 to 24-. Continue to send to 4. Accordingly, the transmitters 27-1 to 27-3 are in a transmission state even in a state where there is no data necessary for display in the input data signal RGB which is a display data signal, that is, in the non-display period T 1 of FIG. 5A.

  Since the transmitters 27-1 to 27-3 have a constant current driver configuration like the transmitter 2 of the first embodiment described above, the input data signal RGB is effective data for display. The current is consumed not only in the display period T2 having, but also in the non-display period T1.

  In this embodiment, in order to reduce current consumption during the non-display period T1, the non-display detector 25 applies control signals (data enable signal DE, vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC) input from the input line L1. Based on this, the non-display period T1 of the input data signal RGB is detected, and the non-display period detection signal is output to the output controller 26. Then, the output controller 26 controls the transmitters 27-1 and 27-2 based on the non-display period detection signal. In the non-display period T1, the transmitter 27-1 is compared with the display period T2. And the transmission power level of 27-2 is reduced. Thereby, it is possible to avoid the transmitters 27-1 and 27-2 consuming unnecessary power during the non-display period T1, and power consumption can be reduced.

  Hereinafter, this operation will be described in more detail. Usually, the image data, that is, the input data signal RGB has a timing as shown by the input data R0-5, the input data G0-5, and the input data B0-5 in FIG. 5A. The vertical synchronization signal VSYNC becomes active “L”, and display of one frame (screen) starts. Next, the horizontal synchronization signal HSYNC becomes active “L”, and horizontal scanning starts. At this time, the period in which the data enable signal DE is active is the display period T2, and the input data R0 to 5, G0 to 5, and B0 to 5 in the display period T2 are actual display data.

  The length (number of displays) of the active period of the data enable signal DE is determined by the horizontal resolution H of the display panel. If the horizontal resolution of the display panel is XGA, the horizontal resolution is 1024 clocks. By repeating such an operation for the number of times of the vertical resolution V (768H in XGA), one screen display is achieved. Here, the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC have been described as “L” active, and the data enable signal DE has been described as “H” active. It is determined by the LSI to be used and the like, but is not limited thereto.

  As described above, the transmitters 27-1 to 27-3 of the transmission unit T always operate and have a constant current source and a constant current sink, so that the data enable signal DE is in an inactive state (not displayed). In the period T1), current is consumed. In order to reduce this current consumption, in this embodiment, as described above, the non-display detector 25 is connected to the display period T2 and the non-display period based on the control signal (for example, the data enable signal DE) input to the transmitter T. T1 is detected, and in the non-display period T1, the output control unit 6 reduces the transmission output level of the transmitters 27-1 and 27-2. As a result, it is possible to efficiently suppress current consumption during the non-display period as compared with a state where the transmitters 27-1 and 27-2 always consume current.

  Next, the operation in which the non-display detector 25 detects the non-display period T1 and the display period T2, and the operation in which the output controller 26 controls the transmission output levels of the transmitters 27-1 and 27-2 are further described. This will be described in detail. FIG. 4 shows the non-display detector 25 and the output controller 26 of FIG.

  As shown in FIG. 5A, the input data signal RGB becomes valid data during the active period (“H” period) of the data enable signal DE, and becomes the display period T2. Further, the input data signal RGB becomes data that is not necessary for display during a period in which the data enable signal DE is inactive ("L" period), and becomes a non-display period T1.

  First, when the non-display detector 25 detects the display period T2 and the non-display period T1 depending on whether the data enable signal DE is active or inactive, the non-display detector 25 is a circuit shown in FIG. Make the configuration.

  That is, the non-display detector 25 has D flip-flops 41 and 42 and an AND circuit 43 as shown in FIG. An input clock signal CLKIN is input to the clock input terminals of the D flip-flops 41 and 42, and a reset signal RESET is input to the clear input (CLR) terminal. The reset signal RESET is also input to the AND circuit 43. The D input terminal of the D flip-flop 41 is connected to the input line L1, and the data enable signal DE is input thereto. The Q output terminal of the D flip-flop 41 is connected to the D input terminal of the D flip-flop 42, and the Q output terminal of the D flip-flop 42 is connected to the input side of the AND circuit 43. The non-display detector 25 in FIG. 4 takes in the data enable signal DE in synchronization with the input clock signal CLKIN and outputs an output control signal from the AND circuit 43.

  FIG. 7 shows a data enable signal DE and an input clock signal CLKIN input to the non-display detector 25, an output control signal CS1 output from the non-display detector 25, and transmitters 27-1 and 27-2. The signal waveforms of data signals CH1 and CH2 to be output are shown.

  The output controller 26 includes an inverter Inv13, a PMOS transistor P41 and an NMOS transistor N41, a PMOS transistor P42 and an NMOS transistor N42, and NMOS transistors N43 and N44, as shown in FIG. That is, the output controller 26 has the same circuit configuration as the output controller 6 of the first embodiment described above.

  The output controller 26 receives a serialized CMOS level signal from the parallel / serial converter 21 via inverters Inv11 and Inv12. The output controller 26 receives an output control signal as a non-display period detection signal output from the non-display detector 25.

  The output controller 26 turns on the PMOS transistors P41 and P42 and turns on the NMOS transistors N41 and N42 when the output control signal CS1 from the non-display detector 25 becomes “H” and represents the display period T2. Then, the NMOS transistors N43 and N44 are turned off. Therefore, the output controller 26 is in a normal operation in which the inverter Inv12 is conducted to the NMOS transistor N1 and the inverter Inv11 is conducted to the NMOS transistor N1.

  On the other hand, when the output control signal CS1 from the non-display detector 25 becomes “L” and represents the non-display period T1, the output controller 26 turns off the PMOS transistors P41 and P42 and the NMOS transistors N41 and N42. Is turned off, while the NMOS transistors N43 and N44 are turned on. Therefore, this output controller 26 makes the inverters Inv11, Inv12 and the NMOS transistors N1, N2 of the transmitters 27-1, 27-2 non-conductive and turns off the NMOS transistors N1, N2, N3, N4. Let Thereby, the current loop between the transmitters 27-1 and 27-2 and the transmission lines 24-1 and 24-2 is interrupted.

  As a result, the transmitters 27-1 and 27- in the non-display period T1 are prevented from continuously consuming a constant current through the current loop regardless of display or non-display as in the prior art. 2 power consumption can be reduced.

(Third embodiment)
Next, a third embodiment as a modified example of the second embodiment will be described. This third embodiment has a circuit configuration shown in FIG. 8 in place of the transmitter 27-1 to 27-4 in FIG. 2 and a CMOS configuration in place of the output controller 26 in FIG. 2. The output controller 36 is different from the second embodiment described above.

  FIG. 8 shows a transmitter 37-1 having a CMOS configuration according to the third embodiment. Although not shown, the other three transmitters have the same CMOS configuration as the transmitter 37-1.

  In the transmitter 37-1, the source of the PMOS transistor P31 and the drain of the NMOS transistor N31 are connected, the drain of the PMOS transistor P31 is connected to the current source I31, and the source of the NMOS transistor N31 is connected to the current sink I32. Has been. The source of the PMOS transistor P32 and the drain of the NMOS transistor N32 are connected, the drain of the PMOS transistor P32 is connected to the current source I31, and the source of the NMOS transistor N32 is connected to the current sink I32.

  The connection point between the source of the PMOS transistor P31 and the drain of the NMOS transistor N31 is connected to the wire LVDS + of the transmission line 24-1, and the connection point between the drain of the PMOS transistor P32 and the drain of the NMOS transistor N32 is the transmission line 24--. 1 wire LVDS−. A terminating resistor R50 is connected between the wires LVDS + and LVDS−.

  The output controller 36 includes an inverter Inv23, a parallel circuit PC51 of a PMOS transistor P51 and an NMOS transistor N51, a parallel circuit PC52 of a PMOS transistor P52 and an NMOS transistor N52, and a parallel circuit PC53 of a PMOS transistor P53 and an NMOS transistor N53. And a parallel circuit PC54 of a PMOS transistor P54 and an NMOS transistor N54.

  The drain of the PMOS transistor P51 of the parallel circuit PC51 and the drain of the NMOS transistor N51 are connected, and the source of the PMOS transistor P51 and the source of the NMOS transistor N51 are connected. A connection point between the drain of the PMOS transistor P51 and the drain of the NMOS transistor N51 is connected to the output side of the inverter Inv22. The connection point between the source of the PMOS transistor P51 and the source of the NMOS transistor N51 is connected to the gate of the PMOS transistor P31 of the transmitter 37-1. The gate of the PMOS transistor P51 is connected to the output side of the inverter Inv23, and the gate of the NMOS transistor N51 is connected to the connection line L51. The connection line L51 is connected to an input terminal to which an output control signal from the non-display detector 25 is input. The input side of the inverter Inv23 is connected to the connection line L51.

  The output controller 36 includes a PMOS transistor P55. The PMOS transistor P55 has a gate connected to the connection line L51, a source connected to the voltage source, and a drain connected to the PMOS transistor P31 of the transmitter 37-1. Connected to the gate.

  In the parallel circuit PC52 of the output controller 36, the source of the PMOS transistor P52 and the drain of the NMOS transistor N52 are connected, and the drain of the PMOS transistor P52 and the source of the NMOS transistor N52 are connected.

  A connection point between the source of the PMOS transistor P52 of the parallel circuit PC52 and the drain of the NMOS transistor N52 is connected to a connection line L50 connecting the inverter Inv22 and the parallel circuit PC51. Further, the connection point between the drain of the PMOS transistor P52 of the parallel circuit PC52 and the source of the NMOS transistor N52 is connected to the gate of the NMOS transistor N31 of the transmitter 37-1 via a connection line L52.

  The drain of the NMOS transistor N57 is connected to the connection line L52, and the source of the NMOS transistor N57 is connected to the ground. The gate of the NMOS transistor N57 is connected to the connection line L54 by the connection line L53. This connection line L53 is connected to the connection line L54, and this connection line L54 is connected to the output side of the inverter Inv23.

  The gate of the PMOS transistor P52 is connected to the connection line L53, and the gate of the NMOS transistor N52 is connected to the connection line L51.

  The source of the PMOS transistor P53 of the parallel circuit PC53 of the output controller 36 and the drain of the NMOS transistor N53 are connected, and the drain of the PMOS transistor P53 and the source of the NMOS transistor N53 are connected.

  A connection point between the source of the PMOS transistor P53 of the parallel circuit PC53 and the drain of the NMOS transistor N53 is connected to a connection line between the inverter Inv22 and the inverter Inv21 through a connection line L56. The connection point between the drain of the PMOS transistor P53 and the source of the NMOS transistor N53 is connected to the gate of the PMOS transistor P32 of the transmitter 37-1 by a connection line L55. The drain of the PMOS transistor P56 is connected to the connection line L55, and the source of the PMOS transistor P56 is connected to the voltage source. Further, the gate of the PMOS transistor P53 of the parallel circuit PC53 is connected to the connection line L54, and the gate of the NMOS transistor N53 is connected to the connection line L51.

  The source of the PMOS transistor P54 of the parallel connection circuit PC54 of the output controller 36 and the drain of the NMOS transistor 54 are connected, and the drain of the PMOS transistor P54 and the source of the NMOS transistor 54 are connected.

  The connection point between the source of the PMOS transistor P54 and the drain of the NMOS transistor 54 is connected to the connection line L56, and the connection point between the drain of the PMOS transistor P54 and the source of the NMOS transistor 54 is connected to the transmitter 37- This is connected to the gate of one NMOS transistor N32.

  The drain of the NMOS transistor N58 is connected to the connection line L57, and the source of the NMOS transistor N58 is connected to the ground. The gate of the NMOS transistor N58 is connected to the connection line L54 via a connection line L58, and the gate of the PMOS transistor P54 is connected to the connection line L58. The gate of the NMOS transistor N54 is connected to the connection line L51.

  The output controller 36 receives CMOS input data from the parallel / serial converter 21 via the two inverters Inv21 and Inv22. The CMOS input data includes a data enable signal DE as a control signal, a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, and an input data signal RGB as a display data signal.

  When the output control signal from the non-display detector 25 is “H” and the input data signal RGB is in the display state, the output controller 36 sets the transmitter 37-1 to normal operation. That is, the transistors of the parallel circuits PC51 to PC54 are turned on, and the PMOS transistor P55, the NMOS transistor N57, the PMOS transistor P56, and the NMOS transistor N58 are turned off. As a result, the output controller 36 makes the output of the inverter Inv21 conductive to the gate of the PMOS transistor P32 and the gate of the NMOS transistor N32 of the transmitter 37-1, via the connection lines L56, L55, and L57. Further, the output of the inverter Inv22 is made conductive to the gate of the PMOS transistor P31 and the gate of the NMOS transistor N31 of the transmitter 37-1 via connection lines L50 and L52.

  On the other hand, when the output control signal from the non-display detector 25 is “L” and the input data signal RGB is in the non-display state, the output controller 36 has the transistors P31, P32, N31, and N32 are turned off to interrupt the current loop formed by the transmission line 24-1 and the terminating resistor R50.

  That is, when the output control signal is “L”, the transistors of the parallel circuits PC51 to PC54 are turned off, and the PMOS transistor P55, the NMOS transistor N57, the PMOS transistor P56, and the NMOS transistor N58 are turned on. Thereby, the output controller 36 cuts off between the inverters Inv21, Inv22 and the transmitter 37-1, and turns off the transistors P31, P32, N31, and N32 of the transmitter 37-1.

  Therefore, the output controller 36 can reduce the power consumption of the transmitter 37-1 in the non-display state.

  In the first to third embodiments described above, the non-display detector detects the non-display period of the display data signal by the data enable signal of the control signal. However, the vertical synchronization signal VSYNC or the horizontal of the control signal is detected. The non-display period of the display data signal may be detected by the synchronization signal HSYNC.

  Similar to the data enable signal DE, the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are display timing signals, and are used at a timing as shown in FIG. 5A in a display device (digital interface display device such as a liquid crystal panel).

  At normal liquid crystal display timing, the period from when the horizontal synchronization signal HSYNC becomes active (low active) until the data enable signal DE becomes active is a non-display period. The period until the data enable signal DE becomes active is defined by the number of clocks. Therefore, the non-display detector that detects the non-display period using the horizontal synchronization signal HSYNC can be realized by including a counter circuit configured as follows.

  Now, as shown in the operation timing chart of FIG. 9, when the horizontal synchronization signal HSYNC becomes active, a count start pulse of the counter circuit is generated. The counter circuit counts a predetermined number of clocks during the period from the time when the start pulse is generated until the data enable signal DE becomes active. CS1 is output to the output controllers 6 and 26 as a non-display period detection signal. On the other hand, in a period other than the non-display period, the non-display detector 25 sets the output control signal CS1 to “H” and outputs it to the output controller. The period other than the non-display period is a display period, and the output controller operates the transmitters 27-1 and 27-2 normally.

  As described above, the non-display detector 25 includes the counter circuit, and the counter circuit detects the non-display period using the horizontal synchronization signal HSYNC and outputs the output control signal CS1 as the non-display period detection signal. Output to the controller 26. As a result, the output controller 26 controls the transmission output levels of the transmitters 27-1 and 27-2 based on the output control signal CS1, and the current consumption can be reduced for the extra non-display period. It becomes possible to reduce the power consumption of the transmitters 27-1 and 27-2 during the period.

  Next, the non-display detector 25 detects the non-display period of the display data signal using the vertical synchronization signal VSYNC among the control signals, and based on the non-display period detection signal output by the non-display detector 25. A case where the power consumption is reduced by the output control unit 26 performing output control of the transmitters 27-1 and 27-2 will be described below.

  Similar to the horizontal synchronization signal HSYNC, in the normal liquid crystal display, the vertical synchronization signal VSYNC becomes active, and one-screen display starts from when it becomes active. A period from this time until the data enable signal DE becomes active is a non-display period. The period until the data enable signal DE becomes active is normally defined by the number of clocks.

  Therefore, when the non-display period is detected using the vertical synchronization signal VSYNC, it can be realized by configuring the counter circuit included in the non-display detector 25 as follows.

  Now, as shown in the operation timing chart of FIG. 10, when the vertical synchronization signal VSYNC becomes active, the count start pulse of the counter circuit is generated. The counter circuit counts a predetermined number of clocks during the period from when the count start pulse is generated until the data enable signal DE becomes active, and during this period, the output of "L" indicating that it is a non-display period The control signal CS1 is output to the output controller 26 as a non-display period detection signal. On the other hand, in a period other than the non-display period, the non-display detector 25 sets the output control signal CS1 to “H” and outputs it to the output controller. The period other than the non-display period is a display period, and the output controller operates the transmitters 27-1 and 27-2 normally. Thus, the counter circuit detects the non-display period using the vertical synchronization signal VSYNC, and outputs the output control signal CS1 as the non-display period detection signal to the output controller 26, whereby the output controller 26 In the non-display period, the extra current consumption of the transmitter can be reduced.

  As described above, the non-display detector 25 as the non-display period detector detects the display / non-display state of the display data signal by using the synchronization signals (VSYNC, HSYNC) and the data enable signal (DE) as control signals. The output control unit 26 controls the LVDS transmission output level of the transmitters 27-1 and 27-2 according to the detected state. Thereby, unnecessary current consumption of the transmitter can be suppressed. In addition, it goes without saying that an LVDS transmission / reception apparatus that further suppresses unnecessary power consumption can be realized if the power control is performed more precisely by combining the display period and the non-display period detection method of the display data signal in the embodiment described above. Yes.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows 1st Embodiment of the serial data transmission / reception apparatus of this invention. It is a block diagram which shows 2nd Embodiment of the serial data transmission / reception apparatus of this invention. It is a block diagram which shows the non-display detector 25 and the output controller 26 of the said 2nd Embodiment. FIG. 4 is a circuit diagram of the non-display detector 25. FIG. 10 is a timing chart showing signal waveforms of a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data signal RGB, and a clock signal CLKIN in the second embodiment. FIG. 5B is an enlarged timing chart showing in detail input data R0 to R5, G0 to G5, and B0 to B5 forming the input data signal RGB shown in FIG. 5A. The horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC, and the data enable signal DE shown in FIG. 5A are enlarged, and the input data signal RGB, the horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC, and the data enable signal DE which are parallel data signals are shown. 5 is a timing chart showing LVDS data signals CH1 to CH3, which are serial data signals obtained by parallel-serial conversion. It is a circuit diagram which shows the structure of the LVDS signal transmitter and output controller of the said 1st, 2 embodiment. In the second embodiment, the data enable signal DE and the input clock signal CLKIN input to the non-display detector 25, the output control signal CS1 output from the non-display detector 25, and the transmitters 27-1, 27. 2 is a timing chart showing signal waveforms of data signals CH1 and CH2 output by -2. It is a circuit diagram which shows the circuit structure of the transmitter of a CMOS structure with which 3rd Embodiment as a modification of the said 2nd Embodiment and an output controller are provided. In the said embodiment, it is an operation | movement timing diagram which shows operation | movement in case the non-display detector outputs the output control signal CS1 based on the horizontal synchronizing signal HSYNC. In the said embodiment, it is an operation | movement timing diagram which shows operation | movement in case the non-display detector outputs the output control signal CS1 based on the vertical synchronizing signal VSYNC. It is a block diagram which shows the transmission / reception apparatus of the conventional LVDS system. It is a circuit diagram of the transmission part of the said conventional LVDS system transmission / reception apparatus. It is a circuit diagram of the transmission part of the conventional RSDS transmission system. It is a figure which shows the display system of the liquid crystal display device which employ | adopted the transmission system of the LVDS system.

Explanation of symbols

1, 21 Parallel-serial converter 2, 27-1 to 27-4, 37-1 LVDS signal transmitter 3, 30-1 to 30-4 LVDS signal receiver 4, 24-1 to 24-4 Transmission path 5 , 25 Non-display detector 6, 26, 36 Output controller 22, 32 PLL (phase locked loop) circuit 31 Serial / parallel converter T Transmitter R Receiver LVDS +, LVDS- Wire R10, R50 Termination resistors L1-L3 Input Line L01 to L03 Output line VSYNC Vertical synchronization signal HSYNC Horizontal synchronization signal DE Data enable signal RGB Input data signal CLKIN Clock signal CH1 to CH3 LVDS data signal T1 Non-display period T2 Display period CS1 Output control signal

Claims (6)

A transmission line;
A parallel data signal is input and the parallel data signal is converted into a plurality of differential serial data signals and transmitted to the transmission path;
A receiver that receives the differential serial data signal from the transmitter via the transmission path;
A termination resistor inserted into the transmission path for transmitting the differential serial data signal and forming a current loop with the transmitter; and
The amplitude of the differential serial data signal is determined by the current value flowing through the current loop,
The parallel data signal includes a display data signal mapped to the differential serial data signal, a synchronization signal, and a data enable signal.
At least one of the synchronization signal and the data enable signal is input and, based on the state of at least one of the synchronization signal and the data enable signal, detects a non-display period in the display data signal and outputs a non-display period detection signal A non-display period detection unit to perform,
A non-display period detection signal output from the non-display period detection unit, and an output control unit that controls a transmission output level of the transmission unit based on the non-display period detection signal. Serial data transmitter / receiver. The serial data transmission / reception device according to claim 1,
A non-display period detection signal is input and the transmission unit is controlled based on the non-display period detection signal to stop transmission of the differential serial data signal to the transmission path. A serial data transmission / reception device. The serial data transmitting / receiving device according to claim 1 or 2,
The data enable signal is a signal that becomes active or inactive according to whether the display data signal is a signal corresponding to a display period or a signal corresponding to a non-display period,
The non-display period detection unit
A serial data transmitting / receiving apparatus, wherein a non-display period in the display data signal is detected based on the data enable signal. The serial data transmitting / receiving apparatus according to any one of claims 1 to 3,
The synchronization signal includes a horizontal synchronization signal,
The non-display period detection unit
A counter that counts the number of clocks of the clock signal from when the horizontal synchronization signal becomes active to when the data enable signal becomes active while a predetermined clock signal is input;
A serial data transmitting / receiving apparatus, wherein the count period by the counter is detected as a non-display period in the display data signal. The serial data transmitting / receiving device according to any one of claims 1 to 4,
The synchronization signal includes a vertical synchronization signal,
The non-display period detection unit
A counter that counts the number of clocks of the clock signal from when the vertical synchronization signal becomes active to when the data enable signal becomes active while a predetermined clock signal is input;
A serial data transmitting / receiving apparatus, wherein the count period by the counter is detected as a non-display period in the display data signal. 6. A semiconductor integrated circuit having a differential small amplitude signal interface system including the non-display period detection unit and the output control unit included in the serial data transmitting / receiving apparatus according to claim 1.

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