TWI813323B - Display device and signal quality adjustment method - Google Patents
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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Abstract
Description
本揭示中所述實施例內容是有關於一種顯示裝置及訊號品質調整方法,且特別是有關於訊號衰減補償的顯示裝置及訊號品質調整方法。The embodiments described in this disclosure relate to a display device and a signal quality adjustment method, and in particular, to a display device and signal quality adjustment method for signal attenuation compensation.
隨著顯示裝置的解析度提高,顯示裝置的面板尺寸逐漸變大。在面板傳輸的介面中,隨著傳送路徑越長,傳送端到接收端的訊號衰減越嚴重,需要以不同的補償強度進行訊號補償。如此,需要源極驅動器中的多個子源極驅動器做不同的補償設定。當子源極驅動器的數量越多或是訊號補償的檔位越多時,所需的控制元件會越多,會造成面板的體積較大,也需要較多的成本。此外,當源極驅動器與不同的時序控制器配合時,需以人力花時間調整補償值。As the resolution of the display device increases, the panel size of the display device gradually increases. In a panel transmission interface, as the transmission path becomes longer, the signal attenuation from the transmitting end to the receiving end becomes more severe, and different compensation strengths are required for signal compensation. In this way, multiple sub-source drivers in the source driver need to make different compensation settings. When the number of sub-source drivers increases or the number of signal compensation levels increases, more control components will be required, resulting in a larger panel size and higher cost. In addition, when the source driver is used with different timing controllers, it takes manual time to adjust the compensation value.
因此,需要更佳的訊號補償方法,能夠降低成本、減少人力開發時間並增加產品共用性,為本領域待改進的問題之一。Therefore, there is a need for better signal compensation methods that can reduce costs, reduce manpower development time and increase product commonality, which is one of the issues to be improved in this field.
本揭示之一態樣是在提供一種顯示裝置,包含源極驅動器、時序控制器、掃描驅動器與主動區域面板。源極驅動器包含多個子源極驅動器。時序控制器耦接於源極驅動器。時序控制器包含多個傳送端電路。多個傳送端電路分別與多個子源極驅動器中的一者相對應。多個傳送端電路各自傳送差動訊號至多個子源極驅動器中的相對應的一者。掃描驅動器耦接於時序控制器,用以輸出多個掃描訊號。主動區域面板耦接於源極驅動器與掃描驅動器。於比對時間區間,差動訊號包含多個時脈訊號以及多個測試訊號。多個子源極驅動器更用以依據多個測試訊號以及多個增益值產生多個測試資料,多個子源極驅動器依據多個測試資料與參考資料產生多個比對結果,並於比對時間區間結束後依據多個比對結果判定多個子源極驅動器各自的最佳增益值。於顯示時間區間,差動訊號包含資料訊號,且多個子源極驅動器依據多個子源極驅動器各自的最佳增益值輸出資料訊號至主動區域面板,以使主動區域面板依據資料訊號以及多個掃描訊號顯示多個畫面。 One aspect of the present disclosure is to provide a display device, including a source driver, a timing controller, a scan driver and an active area panel. The source driver contains multiple sub-source drivers. The timing controller is coupled to the source driver. The timing controller contains multiple transmitter circuits. The plurality of transmission end circuits respectively correspond to one of the plurality of sub-source drivers. Each of the plurality of transmission end circuits transmits a differential signal to a corresponding one of the plurality of sub-source drivers. The scan driver is coupled to the timing controller and used to output a plurality of scan signals. The active area panel is coupled to the source driver and the scan driver. During the comparison time interval, the differential signal includes multiple clock signals and multiple test signals. Multiple sub-source drivers are further used to generate multiple test data based on multiple test signals and multiple gain values. Multiple sub-source drivers generate multiple comparison results based on multiple test data and reference materials, and generate multiple comparison results within the comparison time interval. After completion, the optimal gain values of each of the multiple sub-source drivers are determined based on multiple comparison results. During the display time interval, the differential signal includes the data signal, and the multiple sub-source drivers output the data signal to the active area panel according to the optimal gain value of each of the multiple sub-source drivers, so that the active area panel operates according to the data signal and multiple scans. The signal displays multiple screens.
本揭示之另一態樣是在提供一種訊號品質調整方法,適用於顯示裝置。顯示裝置包含源極驅動器以及時序控制器。源極驅動器包含多個子源極驅動器,時序控制器包含多個傳送端電路。多個傳送端電路分別與多個子源極驅動器中的對應子源極驅動器相對應。訊號品質調整方法包含以下步驟:於比對時間區間,由多個傳送端電路傳送多個時脈訊號以及多個測試訊號至多個子源極驅動器;於比對時間區間,多個子源極驅動器中的每一者依據多個測試訊號產生多個測試資料,並依據多個測試資料與參考資料產生多個比對結果;於比對時間區間結束後,由多個子源極驅動器中的每一者依據多個比對結果判定多個子源極驅動器各自的最佳增益值;以及於顯示時間區間,由多個傳送端電路傳送多個資料訊號至多個子源極驅動器,並由多個子源極驅動器依據多個子源極驅動器各自的最佳增益值輸出多個資料訊號至主動區域面板,以使主動區域面板顯示多個畫面。Another aspect of the present disclosure is to provide a signal quality adjustment method suitable for display devices. The display device includes a source driver and a timing controller. The source driver includes multiple sub-source drivers, and the timing controller includes multiple transmitter circuits. The plurality of transmission end circuits respectively correspond to corresponding sub-source drivers among the plurality of sub-source drivers. The signal quality adjustment method includes the following steps: during the comparison time interval, multiple transmission end circuits transmit multiple clock signals and multiple test signals to multiple sub-source drivers; during the comparison time interval, multiple sub-source drivers Each generates multiple test data based on multiple test signals, and generates multiple comparison results based on multiple test data and reference materials; after the comparison time interval ends, each of the multiple sub-source drivers generates The multiple comparison results determine the optimal gain value of each of the multiple sub-source drivers; and in the display time interval, the multiple transmission end circuits transmit multiple data signals to the multiple sub-source drivers, and the multiple sub-source drivers use the multiple The optimal gain values of each sub-source driver output multiple data signals to the active area panel, so that the active area panel displays multiple images.
以下揭示提供許多不同實施例或例證用以實施本發明的不同特徵。特殊例證中的元件及配置在以下討論中被用來簡化本揭示。所討論的任何例證只用來作解說的用途,並不會以任何方式限制本發明或其例證之範圍和意義。此外,本揭示在不同例證中可能重複引用數字符號且/或字母,這些重複皆為了簡化及闡述,其本身並未指定以下討論中不同實施例且/或配置之間的關係。The following disclosure provides many different embodiments or illustrations for implementing various features of the invention. Particular illustrations of components and arrangements are used in the following discussion to simplify the present disclosure. Any examples discussed are for illustrative purposes only and do not in any way limit the scope and significance of the invention or its examples. In addition, this disclosure may repeatedly refer to numerical symbols and/or letters in different examples. These repetitions are for simplicity and explanation, and do not themselves specify the relationship between different embodiments and/or configurations in the following discussion.
在全篇說明書與申請專利範圍所使用之用詞(terms),除有特別註明外,通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。某些用以描述本揭露之用詞將於下或在此說明書的別處討論,以提供本領域技術人員在有關本揭露之描述上額外的引導。Unless otherwise noted, the terms used throughout the specification and patent claims generally have their ordinary meanings as used in the field, in the disclosure and in the particular content. Certain terms used to describe the present disclosure are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in describing the present disclosure.
關於本文中所使用之『耦接』或『連接』,均可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,而『耦接』或『連接』還可指二或多個元件相互操作或動作。As used in this article, "coupling" or "connection" can refer to two or more elements that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other, and "coupled" or "connected" "Connection" can also refer to the mutual operation or action of two or more components.
在本文中,使用第一、第二與第三等等之詞彙,是用於描述各種元件、組件、區域、層與/或區塊是可以被理解的。但是這些元件、組件、區域、層與/或區塊不應該被這些術語所限制。這些詞彙只限於用來辨別單一元件、組件、區域、層與/或區塊。因此,在下文中的一第一元件、組件、區域、層與/或區塊也可被稱為第二元件、組件、區域、層與/或區塊,而不脫離本發明的本意。如本文所用,詞彙『與/或』包含了列出的關聯項目中的一個或多個的任何組合。本揭示文件中提到的「及/或」是指表列元件的任一者、全部或至少一者的任意組合。It will be understood that the terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or blocks. However, these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are limited to identifying a single element, component, region, layer and/or block. Therefore, a first element, component, region, layer and/or block below can also be termed as a second element, component, region, layer and/or block without departing from the spirit of the present invention. As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The "and/or" mentioned in this disclosure document refers to any one, all or any combination of at least one of the listed elements.
請參閱第1圖。第1圖係根據本揭示之一些實施例所繪示之一種顯示裝置100的示意圖。如第1圖所繪示,顯示裝置100包含時序控制器110、源極驅動器130、掃描驅動器150以及主動區域面板170。於連接關係上,時序控制器110耦接於源極驅動器130與掃描驅動器150。源極驅動器130與掃描驅動器150耦接於主動區域面板170。See
請參閱第2圖。第2圖係根據本揭示之一些實施例所繪示之第1圖中的顯示裝置100的部分示意圖。如第2圖所繪示,時序控制器110包含多個傳送端電路112-1至112-N。源極驅動器130包含多個子源極驅動器132-1至132-N。傳送端電路112-1至112-N與子源極驅動器132-1至132-N之間為一對一的對應關係。例如,傳送端電路112-1對應於子源極驅動器132-1,傳送端電路112-2對應於子源極驅動器132-2,其餘依此類推。此外,時序控制器110更包含處理電路114。
See picture 2. FIG. 2 is a partial schematic diagram of the
於訊號傳輸上,傳送端電路112-1輸出差動訊號S1至子源極驅動器132-1,傳送端電路112-2輸出差動訊號S2至子源極驅動器132-2,其餘依此類推。處理電路114輸出控制訊號SW1至子源極驅動器132-1至子源極驅動器132-N,並輸出控制訊號SW2至子源極驅動器132-1至子源極驅動器132-N。子源極驅動器132-1至子源極驅動器132-N並回傳控制訊號SW1和控制訊號SW2至處理電路114。差動訊號S1至SN係為一對一、單向的傳輸關係,而控制訊號SW1和SW2係為一對多、雙向的傳輸關係。
In terms of signal transmission, the transmitting end circuit 112-1 outputs the differential signal S1 to the sub-source driver 132-1, the transmitting end circuit 112-2 outputs the differential signal S2 to the sub-source driver 132-2, and so on. The
請參閱第3圖。第3圖係根據本揭示之一些實施例所繪示之子源極驅動器132的部分的示意圖。於第3圖中所繪示的子源極驅動器132可用以表示第2圖中的子源極驅動器132-1至132-N。
See picture 3. FIG. 3 is a schematic diagram of a portion of the
如第3圖所繪示。子源極驅動器132包含接收端電路134以及調整電路136。接收端電路134與調整電路136相耦接。接收端電路134包含等化器電路142、取樣電路144與鎖相電路146。調整電路136包含比對電路152、記憶體154、等化器控制電路156與參考資料電路158。
As shown in Figure 3. The
於子源極驅動器132和第2圖中的時序控制器110之間的訊號傳輸上,等化器電路142接收差動訊號S。等化器電路142依據控制訊號SW2的電壓準位選擇性連接取樣電路144和鎖相電路146中的一者。等化器電路142依據控
制訊號SW1的電壓準位選擇性連接記憶體154和等化器控制電路156中的一者。
During the signal transmission between the
關於子源極驅動器132和第2圖中的時序控制器110的詳細操作,將於以下參閱第4圖說明。
Detailed operations of the
請參閱第4圖。第4圖係根據本揭示之一些實施例所繪示之一種訊號品質調整方法400的流程圖。如第4圖所示,訊號品質調整方法400包含步驟S410至步驟S470。
See picture 4. Figure 4 is a flow chart of a signal
步驟S410:於比對時間區間,由傳送端電路傳送時脈訊號以及測試訊號至子源極驅動器。請一併參閱第5圖。第5圖係根據本揭示之一些實施例所繪示之時序圖500的示意圖。 Step S410: During the comparison time interval, the transmitter circuit transmits the clock signal and the test signal to the sub-source driver. Please also refer to Figure 5. Figure 5 is a schematic diagram of a timing diagram 500 according to some embodiments of the present disclosure.
需注意的是,為了便於說明,在第5圖中,係以第1圖中的源極驅動器130包含兩個子源極驅動器為例進行說明。然而,更多子源極驅動器的情況均包含在本揭示的實施範圍內,且可依據以下所述的包含兩個子源極驅動器的情況理解。
It should be noted that, for convenience of explanation, in FIG. 5 , the
第5圖中的差動訊號S1係由第2圖中的傳送端電路112-1傳送至子源極驅動器132-1的訊號,差動訊號S2係由第2圖中的傳送端電路112-2傳送至子源極驅動器132-2的訊號。 The differential signal S1 in Figure 5 is a signal transmitted to the sub-source driver 132-1 from the transmission end circuit 112-1 in Figure 2, and the differential signal S2 is transmitted from the transmission end circuit 112- in Figure 2 2 signals sent to the sub-source driver 132-2.
如第5圖所繪示。時序圖500中包含比對時間區間TI1以及顯示時間區間TI3。 As shown in Figure 5. The timing diagram 500 includes a comparison time interval TI1 and a display time interval TI3.
請一併參閱第2圖和第3圖。當由時序控制器110傳送至源極驅動器130的控制訊號SW1為低電壓準位時,
開始比對時間區間TI1,如第1圖所繪示的顯示裝置100操作於比對模式。而當控制訊號SW1為高電壓準位時,結束比對時間區間TI1,如第1圖所繪示的顯示裝置100操作於顯示模式。
Please refer to Figures 2 and 3 together. When the control signal SW1 sent from the
此外,如第3圖所繪示,當由時序控制器110傳送至源極驅動器130的控制訊號SW1為低電壓準位L時,等化器控制電路156連接至等化器電路142。而當由時序控制器110傳送至源極驅動器130的控制訊號SW1為高電壓準位H時,記憶體154連接至等化器電路142。
In addition, as shown in FIG. 3 , when the control signal SW1 transmitted from the
請回頭參閱第5圖。於比對時間區間TI1內,當由時序控制器110傳送至源極驅動器130的控制訊號SW2為低電壓準位時,第2圖中的子源極驅動器132-1和132-2由時序控制器110接收時脈訊號CLK1至CLK4。而當由時序控制器110傳送至源極驅動器130的控制訊號SW2為高電壓準位時,第2圖中的子源極驅動器132-1和132-2由時序控制器110接收測試訊號TS1至TS4。
Please refer back to Figure 5. During the comparison time interval TI1, when the control signal SW2 sent from the
如第3圖所繪示,當由時序控制器110傳送至源極驅動器130的控制訊號SW2為低電壓準位時,等化器電路142連接至鎖相電路146。而當由時序控制器110傳送至源極驅動器130的控制訊號SW2為高電壓準位時,等化器電路142連接至取樣電路144。
As shown in FIG. 3 , when the control signal SW2 transmitted from the
於部分實施例中,時脈訊號CLK1至CLK4與測試訊號TS1至TS4係經由第1圖中的差動訊號S1至S2所傳送。此外,如第5圖所繪示,時脈訊號CLK1至CLK4與測 試訊號TS1至TS4係依據控制訊號SW2的電壓準位輪流傳送。 In some embodiments, the clock signals CLK1 to CLK4 and the test signals TS1 to TS4 are transmitted through the differential signals S1 to S2 in FIG. 1 . In addition, as shown in Figure 5, the clock signals CLK1 to CLK4 are The test signals TS1 to TS4 are transmitted in turn according to the voltage level of the control signal SW2.
請一併參閱第3圖和第5圖。於時間區間t11,由時序控制器110傳送至源極驅動器130的控制訊號SW2為低電壓準位,此時等化器電路142連接至鎖相電路146,時脈訊號CLK經由等化器電路142與鎖相電路146傳送至取樣電路144與比對電路152,以將取樣電路144與比對電路152的時脈對齊。
Please refer to Figure 3 and Figure 5 together. In the time interval t11, the control signal SW2 sent from the
接著,於時間區間t21,由時序控制器110傳送至源極驅動器130的控制訊號SW2為高電壓準位,此時等化器電路142連接至取樣電路144,測試訊號TS1經由等化器電路142傳送至取樣電路144。取樣電路144對測試訊號TS1進行取樣以產生測試資料。
Then, in the time interval t21 , the control signal SW2 transmitted from the
關於時間區間t12、t22、t13、t23、t14、t24的操作與時間區間t11和t21的操作相類似,在此不再詳細敘述。 The operations on the time intervals t12, t22, t13, t23, t14, and t24 are similar to the operations on the time intervals t11 and t21, and will not be described in detail here.
步驟S430:於比對時間區間,由子源極驅動器中的每一者依據測試訊號產生測試資料,並依據測試資料與參考資料產生比對結果。 Step S430: During the comparison time interval, each of the sub-source drivers generates test data based on the test signal, and generates a comparison result based on the test data and reference materials.
請一併參閱第3圖。舉例而言,於測試訊號TS1經由等化器電路142傳送至取樣電路144之後,取樣電路144對測試訊號TS1進行取樣以產生測試資料TD1,並將測試資料TD1傳送至比對電路152。類似地,於測試訊號TS2經由等化器電路142傳送至取樣電路144之後,取樣電路
144對測試訊號TS2進行取樣以產生測試資料TD2,並將測試資料TD2傳送至比對電路152。其餘測試資料TD3和TD4依此類推。
Please also refer to Figure 3. For example, after the test signal TS1 is sent to the sampling circuit 144 through the
請一併參閱第3圖。第5圖中的訊號Rx1-EQ係由第2圖中的子源極驅動器132-1的等化器控制電路156傳送至等化器電路142的訊號。訊號Rx1-Error係第2圖中的子源極驅動器132-1的比對電路152產生的比對結果。訊號Rx2-EQ係由第2圖中的子源極驅動器132-2的等化器控制電路156傳送至等化器電路142的訊號。訊號Rx2-Error係第2圖中的子源極驅動器132-2的比對電路152產生的比對結果。
Please also refer to Figure 3. The signal Rx1-EQ in FIG. 5 is a signal transmitted to the
於部分實施例中,第3圖中的等化器控制電路156用以產生多個增益參數至接收端電路134的等化器電路142,接著等化器電路142依據增益參數產生增益值。
In some embodiments, the
舉例而言,於時間區間t11和t21,等化器控制電路156輸出增益參數EQ0至等化器電路142。等化器電路142依據增益參數EQ0產生相對應於增益參數EQ0的增益值0dB。於時間區間t12和t22,等化器控制電路156輸出增益參數EQ1至等化器電路142。等化器電路142依據增益參數EQ1產生相對應於增益參數EQ1的增益值3dB。於時間區間t13和t23,等化器控制電路156輸出增益參數EQ2至等化器電路142。等化器電路142依據增益參數EQ2產生相對應於增益參數EQ2的增益值6dB。於時間區間t14和t24,等化器控制電路156輸出增益參數EQ3至等
化器電路142。等化器電路142依據增益參數EQ3產生相對應於增益參數EQ3的增益值9dB。上述增益參數和增益值之間的對應關係僅為例示說明之用,本揭示的實施方式不以上述為限制。
For example, during the time intervals t11 and t21, the
於部分實施例中,等化器電路142將測試訊號經由增益值放大後,將放大後的測試訊號傳送至取樣電路144,取樣電路144依據放大後的測試訊號產生測試資料TD,並將測試資料TD傳送至比對電路152。另一方面,參考資料電路158輸出參考資料RD至比對電路152。比對電路152比對測試資料TD和參考資料RD之後,產生比對結果。
In some embodiments, the
於部分實施例中,比對電路152比對測試資料TD和參考資料RD之間的差異位元數,以作為比對結果。於部分實施例中,比對電路152比對測試資料TD相對於參考資料RD的錯誤位元數,以作為比對結果。
In some embodiments, the
舉例而言,於時間區間t21,子源極驅動器132-1的比對電路152比對依據測試訊號TS1所產生的測試資料TD1和參考資料RD,判定測試資料TD1和參考資料RD之間的差異位元數為100位元,因此對應於增益參數EQ0的比對結果即為100位元。再舉例而言,於時間區間t21,子源極驅動器132-2的比對電路152比對依據測試訊號TS1所產生的測試資料TD1和參考資料RD,判定測試資料TD1和參考資料RD之間的差異位元數為60位元,因此對
應於增益參數EQ0的比對結果即為60位元。其餘比對結果依此類推,在此不再詳細敘述。
For example, in the time interval t21, the
於部分實施例中,於時脈訊號CLK1至CLK4與測試訊號TS1至TS4之間包含對齊訊號TA。對齊訊號TA用以使測試資料TD和參考資料RD在時序上對齊。 In some embodiments, the alignment signal TA is included between the clock signals CLK1 to CLK4 and the test signals TS1 to TS4. The alignment signal TA is used to align the test data TD and the reference material RD in timing.
請參閱第6圖。第6圖係根據本揭示之一些實施例所繪示之一種比對結果600的示意圖。如第6圖所繪示,測試資料TD依序包含時脈資料、標頭資料、第一測試資料、第二測試資料。參考資料RD依序包含對齊資料、第一參考資料、第二參考資料。對齊資料用以使測試資料TD的第一測試資料和參考資料RD第一參考資料於時序上相對齊。每當測試資料與參考資料不同時,錯誤位元數即加1。假設第一測試資料和第一參考資料相同,而第二測試資料與第二參考資料不同,則計數器(未繪示)於第一時序時為0,於第二時序時為1。
See Figure 6. Figure 6 is a schematic diagram of a
請一併參閱第3圖。記憶體154用以儲存比對結果。
Please also refer to Figure 3. The
請回到第4圖。步驟S450:於比對時間區間結束後,由子源極驅動器中的每一者依據比對結果判定子源極驅動器各自的最佳增益值。 Please go back to picture 4. Step S450: After the comparison time interval ends, each of the sub-source drivers determines the optimal gain value of each sub-source driver based on the comparison result.
於部分實施例中,第3圖中的記憶體154包含處理電路(未繪示),用以判斷子源極驅動器各自的最佳增益參數,以使子源極驅動器進而得知與最佳增益參數相對應的最佳增益值。於部分實施例中,最佳比對結果係為比對結果中錯誤位元數最低者,而最佳增益參數即為比對結果中錯誤位元數最低的增益參數。In some embodiments, the
舉例而言,請一併參閱第5圖。對子源極驅動器132-1而言,最佳增益參數係錯誤位元數最低的增益參數EQ2。對子源極驅動器132-2而言,最佳增益參數係錯誤位元數最低的增益參數EQ3。For example, please also see Figure 5. For the sub-source driver 132-1, the optimal gain parameter is the gain parameter EQ2 with the lowest number of error bits. For the sub-source driver 132-2, the optimal gain parameter is the gain parameter EQ3 with the lowest number of error bits.
步驟S470:於顯示時間區間,由傳送端電路傳送資料訊號至子源極驅動器,並由子源極驅動器依據子源極驅動器各自的最佳增益值輸出資料訊號至主動區域面板,以使主動區域面板顯示畫面。Step S470: During the display time interval, the transmission end circuit transmits the data signal to the sub-source driver, and the sub-source driver outputs the data signal to the active area panel according to the optimal gain value of each sub-source driver, so that the active area panel display screen.
請一併參閱第5圖。於部分實施例中,顯示時間區間TI3包含切換時間區間TI40、回傳時間區間TI41以及一般顯示時間區間TI42。Please also refer to Figure 5. In some embodiments, the display time interval TI3 includes a switching time interval TI40, a return time interval TI41, and a general display time interval TI42.
於切換時間區間TI40,控制訊號SW1由低電壓準位切換至高電壓準位。In the switching time interval TI40, the control signal SW1 switches from a low voltage level to a high voltage level.
於回傳時間區間TI41,子源極驅動器132依序經由控制訊號SW2傳送比對結果至時序控制器110。於部分實施例中,子源極驅動器132接收時序控制器110傳送的差動訊號S,並依據差動訊號S中的時脈訊號和回傳觸發訊號依序回傳比對結果至時序控制器110。In the return time interval TI41, the
舉例而言,於時間區間t15,子源極驅動器132-1接收到回傳觸發訊號FBEN為高電壓位準,而子源極驅動器132-2接收到回傳觸發訊號FBEN為低電壓位準,因此於時間區間t16,子源極驅動器132-1回傳子源極驅動器132-1的比對結果至時序控制器110的處理電路114(即為第5圖上的Rx1回傳)。於時間區間t25,子源極驅動器132-1接收到回傳觸發訊號FBEN為低電壓位準,而子源極驅動器132-2接收到回傳觸發訊號FBEN為高電壓位準,因此於時間區間t26,子源極驅動器132-2回傳子源極驅動器132-2的比對結果至時序控制器110的處理電路114(即為第5圖上的Rx2回傳)。For example, in the time interval t15, the sub-source driver 132-1 receives the feedback trigger signal FBEN which is at a high voltage level, and the sub-source driver 132-2 receives the feedback trigger signal FBEN which is at a low voltage level. Therefore, in the time interval t16, the sub-source driver 132-1 returns the comparison result of the sub-source driver 132-1 to the
於部分實施例中,若是處理電路114判定子源極驅動器132回傳的比對結果不理想,例如處理電路114判定子源極驅動器132-1回傳的比對結果的錯誤位元數太高,則處理電路114調整顯示裝置100的振幅或預加強值,並於調整顯示裝置100的振幅或預加強值之後,重新執行比對模式。In some embodiments, if the
於部分實施例中,於顯示時間區間TI3,當子源極驅動器132的時脈訊號失鎖時,子源極驅動器132經由控制訊號SW2回傳子源極驅動器132的鎖定狀態至時序控制器110。於部分實施例中,子源極驅動器132將控制訊號SW2的電壓位準拉至低電壓位準,以使時序控制器110得知子源極驅動器132的時脈訊號失鎖,時序控制器110並重新傳送時脈訊號至子源極驅動器132以重新鎖定子源極驅動器132的時脈訊號。In some embodiments, during the display time interval TI3, when the clock signal of the
於一般顯示時間區間TI42,子源極驅動器132依據子源極驅動器132各自的最佳增益值輸出資料訊號至主動區域面板170,以使主動區域面板170顯示畫面。In the general display time interval TI42, the
請一併參閱第3圖。於一般顯示時間區間TI42控制訊號SW1為高電壓準位,記憶體154與等化器電路142相連接,並將最佳增益參數傳送至等化器電路142。Please also refer to Figure 3. In the normal display time interval TI42, the control signal SW1 is at a high voltage level, the
舉例而言,子源極驅動器132-1的記憶體154將子源極驅動器132-1的最佳增益參數EQ2傳送至子源極驅動器132-1的等化器電路142。子源極驅動器132-1接收資料訊號(例如為RGB資料訊號)後,依據與最佳增益參數EQ2相對應的最佳增益值放大資料訊號,並將放大後的資料訊號傳送至主動區域面板170,以使主動區域面板170顯示畫面。For example, the
同樣地,子源極驅動器132-2的記憶體154將子源極驅動器132-2的最佳增益參數EQ3傳送至子源極驅動器132-2的等化器電路142。子源極驅動器132-2接收資料訊號(例如為RGB資料訊號)後,依據與最佳增益參數EQ3相對應的最佳增益值放大資料訊號,並將放大後的資料訊號傳送至主動區域面板170,以使主動區域面板170顯示畫面。Similarly, the
請再回到第1圖。於部分實施例中,第1圖中的掃描驅動器150輸出多個掃描訊號至主動區域面板170,主動區域面板170再依據掃描驅動器150輸出的多個掃描訊號以及源極驅動器130輸出的多個資料訊號顯示畫面。Please go back to
須注意的是,如第5圖所述之時脈訊號、資料訊號、增益參數等的數量僅為例示說明之用,本實施方式不以上述為限制。It should be noted that the numbers of clock signals, data signals, gain parameters, etc. as shown in Figure 5 are only for illustration, and this embodiment is not limited to the above.
由上述本揭示之實施方式可知,本揭示之實施例藉由提供一種顯示裝置及訊號品質調整方法,且特別是有關於訊號衰減補償的顯示裝置及訊號品質調整方法,由調整電路透過改變補償增益值並比對測試資料與參考資料,再從所有的比對結果中選擇最佳的補償增益。如此,無需由人力調整補償值的設定,也無須較多的控制元件,可降低成本、減少人力開發時間並增加產品共用性。As can be seen from the above embodiments of the present disclosure, the embodiments of the present disclosure provide a display device and a signal quality adjustment method, and in particular, a display device and a signal quality adjustment method related to signal attenuation compensation. The adjustment circuit changes the compensation gain. values and compare test data with reference materials, and then select the best compensation gain from all comparison results. In this way, there is no need for manual adjustment of the compensation value setting, and there is no need for more control components, which can reduce costs, reduce human development time, and increase product commonality.
另外,上述例示包含依序的示範步驟,但該些步驟不必依所顯示的順序被執行。以不同順序執行該些步驟皆在本揭示內容的考量範圍內。在本揭示內容之實施例的精神與範圍內,可視情況增加、取代、變更順序及/或省略該些步驟。In addition, the above illustrations include sequential exemplary steps, but the steps need not be performed in the order shown. It is within the scope of this disclosure to perform these steps in a different order. These steps may be added, substituted, changed in order and/or omitted as appropriate within the spirit and scope of the embodiments of the present disclosure.
雖然本揭示已以實施方式揭示如上,然其並非用以限定本揭示,任何熟習此技藝者,在不脫離本揭示之精神和範圍內,當可作各種之更動與潤飾,因此本揭示之保護範圍當視後附之申請專利範圍所界定者為準。Although the present disclosure has been disclosed in the form of implementation, it is not intended to limit the present disclosure. Anyone familiar with this art can make various modifications and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection of the present disclosure is The scope shall be determined by the appended patent application scope.
100:顯示裝置 110:時序控制器 130:源極驅動器 150:掃描驅動器 170:主動區域面板100:Display device 110: Timing controller 130: Source driver 150:Scan drive 170: Active area panel
112-1,112-2,112-N:傳送端電路 112-1, 112-2, 112-N: Transmission circuit
132,132-1,132-2,132-N:子源極驅動器 132,132-1,132-2,132-N: Sub-source driver
S,S1,S2,SN:差動訊號 S, S1, S2, SN: differential signal
114:處理電路 114: Processing circuit
SW1,SW2:控制訊號 SW1, SW2: control signal
134:接收端電路 134: Receiver circuit
136:調整電路 136:Adjust circuit
TD,TD1,TD2,TD3,TD4:測試資料 TD, TD1, TD2, TD3, TD4: test data
RD:參考資料 RD: reference materials
H:高電壓準位 H: high voltage level
L:低電壓準位 L: low voltage level
CLK:時脈訊號 CLK: clock signal
142:等化器電路 142: Equalizer circuit
144:取樣電路 144: Sampling circuit
146:鎖相電路 146: Phase lock circuit
152:比對電路 152:Comparison circuit
154:記憶體 154:Memory
156:等化器控制電路 156: Equalizer control circuit
158:參考資料電路 158:Reference circuit
400:訊號品質調整方法 400: Signal quality adjustment method
S410,S430,S450,S470:步驟 S410, S430, S450, S470: steps
Rx1-EQ,Rx2-EQ:訊號 Rx1-EQ, Rx2-EQ: signal
Rx1-Error,Rx2-Error:訊號 Rx1-Error, Rx2-Error: signal
TI1,TI3,TI40,TI41,TI42:時間區間 TI1, TI3, TI40, TI41, TI42: time interval
t11,t21,t12,t22,t13,t23:時間區間 t11,t21,t12,t22,t13,t23: time interval
t14,t24,t15,t16,t25,t26:時間區間 t14,t24,t15,t16,t25,t26: time interval
CLK1,CLK2,CLK3,CLK4:時脈訊號 CLK1, CLK2, CLK3, CLK4: clock signal
TA:對齊訊號 TA: alignment signal
TS1,TS2,TS3,TS4:測試訊號 TS1, TS2, TS3, TS4: test signal
FBEN:回傳觸發訊號 FBEN: Return trigger signal
EQ0,EQ1,EQ2,EQ3:增益參數 EQ0, EQ1, EQ2, EQ3: gain parameters
為讓本揭示之上述和其他目的、特徵、優點與實施例能夠更明顯易懂,所附圖式之說明如下: 第1圖係根據本揭示之一些實施例所繪示之一種顯示裝置的示意圖; 第2圖係根據本揭示之一些實施例所繪示之第1圖中的顯示裝置的部分示意圖; 第3圖係根據本揭示之一些實施例所繪示之子源極驅動器的部分的示意圖; 第4圖係根據本揭示之一些實施例所繪示之一種訊號品質調整方法的流程圖; 第5圖係根據本揭示之一些實施例所繪示之時序圖的示意圖;以及 第6圖係根據本揭示之一些實施例所繪示之一種比對結果的示意圖。 In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: Figure 1 is a schematic diagram of a display device according to some embodiments of the present disclosure; Figure 2 is a partial schematic diagram of the display device in Figure 1 according to some embodiments of the present disclosure; Figure 3 is a schematic diagram of a portion of a sub-source driver according to some embodiments of the present disclosure; Figure 4 is a flow chart of a signal quality adjustment method according to some embodiments of the present disclosure; Figure 5 is a schematic diagram of a timing diagram according to some embodiments of the present disclosure; and Figure 6 is a schematic diagram of a comparison result according to some embodiments of the present disclosure.
132:子源極驅動器 132: Sub-source driver
S:差動訊號 S: Differential signal
SW1,SW2:控制訊號 SW1, SW2: control signal
134:接收端電路 134: Receiver circuit
136:調整電路 136:Adjust circuit
TD:測試資料 TD: test data
RD:參考資料 RD: reference materials
H:高電壓準位 H: high voltage level
L:低電壓準位 L: low voltage level
142:等化器電路 142: Equalizer circuit
144:取樣電路 144: Sampling circuit
146:鎖相電路 146: Phase lock circuit
152:比對電路 152:Comparison circuit
154:記憶體 154:Memory
156:等化器控制電路 156: Equalizer control circuit
158:參考資料電路 158:Reference circuit
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TW201933306A (en) * | 2018-01-22 | 2019-08-16 | 奇景光電股份有限公司 | Timing controller and operation method thereof |
CN110459158A (en) * | 2019-01-21 | 2019-11-15 | 友达光电股份有限公司 | Driving device and its driving signal generating method |
US20200251036A1 (en) * | 2019-01-31 | 2020-08-06 | Silicon Works Co., Ltd. | Data processing device, data driving device and system for driving display device |
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KR100883778B1 (en) * | 2008-03-20 | 2009-02-20 | 주식회사 아나패스 | Display and method for transmitting clock signal in blank period |
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US11024249B2 (en) * | 2019-03-27 | 2021-06-01 | Samsung Display Co., Ltd. | Display device and driving method thereof |
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TW201933306A (en) * | 2018-01-22 | 2019-08-16 | 奇景光電股份有限公司 | Timing controller and operation method thereof |
CN110459158A (en) * | 2019-01-21 | 2019-11-15 | 友达光电股份有限公司 | Driving device and its driving signal generating method |
US20200251036A1 (en) * | 2019-01-31 | 2020-08-06 | Silicon Works Co., Ltd. | Data processing device, data driving device and system for driving display device |
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