TWI813323B - Display device and signal quality adjustment method - Google Patents

Abstract

A display device includes a source driver, a timing controller, a scan driver and an active area panel is disclosed. The source driver includes several sub-source drivers. The timing controller includes several transmitter circuits. The transmitter circuits transmit the differential signals to the sub-source drivers. In the comparison time interval, the differential signals include clock signals and test signals. The sub-source drivers generate test data according to the test signals and the gain values, the sub-source drivers generate comparison results according to the test data and the reference data and determine the optimal gain values of the sub-source drivers according to the comparison results. In the display time interval, the differential signals include the data signals. The sub-source drivers output data signals to the active area panel according to the optimal gain values, so that the active area panel displays images.

Description

Display device and signal quality adjustment method

The embodiments described in this disclosure relate to a display device and a signal quality adjustment method, and in particular, to a display device and signal quality adjustment method for signal attenuation compensation.

As the resolution of the display device increases, the panel size of the display device gradually increases. In a panel transmission interface, as the transmission path becomes longer, the signal attenuation from the transmitting end to the receiving end becomes more severe, and different compensation strengths are required for signal compensation. In this way, multiple sub-source drivers in the source driver need to make different compensation settings. When the number of sub-source drivers increases or the number of signal compensation levels increases, more control components will be required, resulting in a larger panel size and higher cost. In addition, when the source driver is used with different timing controllers, it takes manual time to adjust the compensation value.

Therefore, there is a need for better signal compensation methods that can reduce costs, reduce manpower development time and increase product commonality, which is one of the issues to be improved in this field.

One aspect of the present disclosure is to provide a display device, including a source driver, a timing controller, a scan driver and an active area panel. The source driver contains multiple sub-source drivers. The timing controller is coupled to the source driver. The timing controller contains multiple transmitter circuits. The plurality of transmission end circuits respectively correspond to one of the plurality of sub-source drivers. Each of the plurality of transmission end circuits transmits a differential signal to a corresponding one of the plurality of sub-source drivers. The scan driver is coupled to the timing controller and used to output a plurality of scan signals. The active area panel is coupled to the source driver and the scan driver. During the comparison time interval, the differential signal includes multiple clock signals and multiple test signals. Multiple sub-source drivers are further used to generate multiple test data based on multiple test signals and multiple gain values. Multiple sub-source drivers generate multiple comparison results based on multiple test data and reference materials, and generate multiple comparison results within the comparison time interval. After completion, the optimal gain values of each of the multiple sub-source drivers are determined based on multiple comparison results. During the display time interval, the differential signal includes the data signal, and the multiple sub-source drivers output the data signal to the active area panel according to the optimal gain value of each of the multiple sub-source drivers, so that the active area panel operates according to the data signal and multiple scans. The signal displays multiple screens.

Another aspect of the present disclosure is to provide a signal quality adjustment method suitable for display devices. The display device includes a source driver and a timing controller. The source driver includes multiple sub-source drivers, and the timing controller includes multiple transmitter circuits. The plurality of transmission end circuits respectively correspond to corresponding sub-source drivers among the plurality of sub-source drivers. The signal quality adjustment method includes the following steps: during the comparison time interval, multiple transmission end circuits transmit multiple clock signals and multiple test signals to multiple sub-source drivers; during the comparison time interval, multiple sub-source drivers Each generates multiple test data based on multiple test signals, and generates multiple comparison results based on multiple test data and reference materials; after the comparison time interval ends, each of the multiple sub-source drivers generates The multiple comparison results determine the optimal gain value of each of the multiple sub-source drivers; and in the display time interval, the multiple transmission end circuits transmit multiple data signals to the multiple sub-source drivers, and the multiple sub-source drivers use the multiple The optimal gain values of each sub-source driver output multiple data signals to the active area panel, so that the active area panel displays multiple images.

The following disclosure provides many different embodiments or illustrations for implementing various features of the invention. Particular illustrations of components and arrangements are used in the following discussion to simplify the present disclosure. Any examples discussed are for illustrative purposes only and do not in any way limit the scope and significance of the invention or its examples. In addition, this disclosure may repeatedly refer to numerical symbols and/or letters in different examples. These repetitions are for simplicity and explanation, and do not themselves specify the relationship between different embodiments and/or configurations in the following discussion.

Unless otherwise noted, the terms used throughout the specification and patent claims generally have their ordinary meanings as used in the field, in the disclosure and in the particular content. Certain terms used to describe the present disclosure are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in describing the present disclosure.

As used in this article, "coupling" or "connection" can refer to two or more elements that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other, and "coupled" or "connected" "Connection" can also refer to the mutual operation or action of two or more components.

It will be understood that the terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or blocks. However, these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are limited to identifying a single element, component, region, layer and/or block. Therefore, a first element, component, region, layer and/or block below can also be termed as a second element, component, region, layer and/or block without departing from the spirit of the present invention. As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The "and/or" mentioned in this disclosure document refers to any one, all or any combination of at least one of the listed elements.

See picture 1. Figure 1 is a schematic diagram of a display device 100 according to some embodiments of the present disclosure. As shown in FIG. 1 , the display device 100 includes a timing controller 110 , a source driver 130 , a scan driver 150 and an active area panel 170 . In terms of connection relationship, the timing controller 110 is coupled to the source driver 130 and the scan driver 150 . The source driver 130 and the scan driver 150 are coupled to the active area panel 170 .

See picture 2. FIG. 2 is a partial schematic diagram of the display device 100 in FIG. 1 according to some embodiments of the present disclosure. As shown in FIG. 2 , the timing controller 110 includes a plurality of transmitter circuits 112-1 to 112-N. The source driver 130 includes a plurality of sub-source drivers 132-1 to 132-N. There is a one-to-one correspondence between the transmission end circuits 112-1 to 112-N and the sub-source drivers 132-1 to 132-N. For example, the transmitting end circuit 112-1 corresponds to the sub-source driver 132-1, the transmitting end circuit 112-2 corresponds to the sub-source driver 132-2, and so on. In addition, the timing controller 110 further includes a processing circuit 114 .

In terms of signal transmission, the transmitting end circuit 112-1 outputs the differential signal S1 to the sub-source driver 132-1, the transmitting end circuit 112-2 outputs the differential signal S2 to the sub-source driver 132-2, and so on. The processing circuit 114 outputs the control signal SW1 to the sub-source drivers 132-1 to 132-N, and outputs the control signal SW2 to the sub-source drivers 132-1 to 132-N. The sub-source driver 132-1 is connected to the sub-source driver 132-N and returns the control signal SW1 and the control signal SW2 to the processing circuit 114. The differential signals S1 to SN have a one-to-one, one-way transmission relationship, while the control signals SW1 and SW2 have a one-to-many, two-way transmission relationship.

See picture 3. FIG. 3 is a schematic diagram of a portion of the sub-source driver 132 according to some embodiments of the present disclosure. The sub-source driver 132 shown in FIG. 3 may be used to represent the sub-source drivers 132-1 to 132-N in FIG. 2.

As shown in Figure 3. The sub-source driver 132 includes a receiving circuit 134 and an adjustment circuit 136 . The receiving circuit 134 is coupled to the adjustment circuit 136 . The receiving circuit 134 includes an equalizer circuit 142, a sampling circuit 144 and a phase lock circuit 146. The adjustment circuit 136 includes a comparison circuit 152 , a memory 154 , an equalizer control circuit 156 and a reference circuit 158 .

During the signal transmission between the sub-source driver 132 and the timing controller 110 in FIG. 2, the equalizer circuit 142 receives the differential signal S. The equalizer circuit 142 selectively connects one of the sampling circuit 144 and the phase lock circuit 146 according to the voltage level of the control signal SW2. The equalizer circuit 142 controls The voltage level of the control signal SW1 is selectively connected to one of the memory 154 and the equalizer control circuit 156 .

Detailed operations of the sub-source driver 132 and the timing controller 110 in FIG. 2 will be described below with reference to FIG. 4 .

See picture 4. Figure 4 is a flow chart of a signal quality adjustment method 400 according to some embodiments of the present disclosure. As shown in FIG. 4 , the signal quality adjustment method 400 includes steps S410 to S470.

Step S410: During the comparison time interval, the transmitter circuit transmits the clock signal and the test signal to the sub-source driver. Please also refer to Figure 5. Figure 5 is a schematic diagram of a timing diagram 500 according to some embodiments of the present disclosure.

It should be noted that, for convenience of explanation, in FIG. 5 , the source driver 130 in FIG. 1 is taken as an example that includes two sub-source drivers. However, the case of more sub-source drivers is included in the implementation scope of the present disclosure, and can be understood based on the case of including two sub-source drivers described below.

The differential signal S1 in Figure 5 is a signal transmitted to the sub-source driver 132-1 from the transmission end circuit 112-1 in Figure 2, and the differential signal S2 is transmitted from the transmission end circuit 112- in Figure 2 2 signals sent to the sub-source driver 132-2.

As shown in Figure 5. The timing diagram 500 includes a comparison time interval TI1 and a display time interval TI3.

Please refer to Figures 2 and 3 together. When the control signal SW1 sent from the timing controller 110 to the source driver 130 is at a low voltage level, Starting the comparison time interval TI1, the display device 100 as shown in FIG. 1 operates in the comparison mode. When the control signal SW1 is at a high voltage level, the comparison time interval TI1 ends, and the display device 100 as shown in FIG. 1 operates in the display mode.

In addition, as shown in FIG. 3 , when the control signal SW1 transmitted from the timing controller 110 to the source driver 130 is the low voltage level L, the equalizer control circuit 156 is connected to the equalizer circuit 142 . When the control signal SW1 sent from the timing controller 110 to the source driver 130 is at the high voltage level H, the memory 154 is connected to the equalizer circuit 142 .

Please refer back to Figure 5. During the comparison time interval TI1, when the control signal SW2 sent from the timing controller 110 to the source driver 130 is at a low voltage level, the sub-source drivers 132-1 and 132-2 in Figure 2 are controlled by the timing The processor 110 receives clock signals CLK1 to CLK4. When the control signal SW2 sent from the timing controller 110 to the source driver 130 is at a high voltage level, the sub-source drivers 132-1 and 132-2 in Figure 2 receive the test signal TS1 from the timing controller 110 to TS4.

As shown in FIG. 3 , when the control signal SW2 transmitted from the timing controller 110 to the source driver 130 is at a low voltage level, the equalizer circuit 142 is connected to the phase lock circuit 146 . When the control signal SW2 transmitted from the timing controller 110 to the source driver 130 is at a high voltage level, the equalizer circuit 142 is connected to the sampling circuit 144 .

In some embodiments, the clock signals CLK1 to CLK4 and the test signals TS1 to TS4 are transmitted through the differential signals S1 to S2 in FIG. 1 . In addition, as shown in Figure 5, the clock signals CLK1 to CLK4 are The test signals TS1 to TS4 are transmitted in turn according to the voltage level of the control signal SW2.

Please refer to Figure 3 and Figure 5 together. In the time interval t11, the control signal SW2 sent from the timing controller 110 to the source driver 130 is at a low voltage level. At this time, the equalizer circuit 142 is connected to the phase lock circuit 146, and the clock signal CLK passes through the equalizer circuit 142. The AND phase lock circuit 146 is sent to the sampling circuit 144 and the comparison circuit 152 to align the clocks of the sampling circuit 144 and the comparison circuit 152 .

Then, in the time interval t21 , the control signal SW2 transmitted from the timing controller 110 to the source driver 130 is at a high voltage level. At this time, the equalizer circuit 142 is connected to the sampling circuit 144 , and the test signal TS1 passes through the equalizer circuit 142 sent to sampling circuit 144. The sampling circuit 144 samples the test signal TS1 to generate test data.

The operations on the time intervals t12, t22, t13, t23, t14, and t24 are similar to the operations on the time intervals t11 and t21, and will not be described in detail here.

Step S430: During the comparison time interval, each of the sub-source drivers generates test data based on the test signal, and generates a comparison result based on the test data and reference materials.

Please also refer to Figure 3. For example, after the test signal TS1 is sent to the sampling circuit 144 through the equalizer circuit 142, the sampling circuit 144 samples the test signal TS1 to generate the test data TD1, and sends the test data TD1 to the comparison circuit 152. Similarly, after the test signal TS2 is transmitted to the sampling circuit 144 through the equalizer circuit 142, the sampling circuit 144 samples the test signal TS2 to generate test data TD2, and sends the test data TD2 to the comparison circuit 152 . The rest of the test data TD3 and TD4 can be deduced in the same way.

Please also refer to Figure 3. The signal Rx1-EQ in FIG. 5 is a signal transmitted to the equalizer circuit 142 from the equalizer control circuit 156 of the sub-source driver 132-1 in FIG. 2. The signal Rx1-Error is the comparison result generated by the comparison circuit 152 of the sub-source driver 132-1 in Figure 2. The signal Rx2-EQ is a signal transmitted from the equalizer control circuit 156 of the sub-source driver 132-2 in FIG. 2 to the equalizer circuit 142. The signal Rx2-Error is the comparison result generated by the comparison circuit 152 of the sub-source driver 132-2 in Figure 2.

In some embodiments, the equalizer control circuit 156 in FIG. 3 is used to generate a plurality of gain parameters to the equalizer circuit 142 of the receiving end circuit 134, and then the equalizer circuit 142 generates a gain value according to the gain parameters.

For example, during the time intervals t11 and t21, the equalizer control circuit 156 outputs the gain parameter EQ0 to the equalizer circuit 142. The equalizer circuit 142 generates a gain value 0 dB corresponding to the gain parameter EQ0 according to the gain parameter EQ0. During the time interval t12 and t22, the equalizer control circuit 156 outputs the gain parameter EQ1 to the equalizer circuit 142. The equalizer circuit 142 generates a gain value 3dB corresponding to the gain parameter EQ1 according to the gain parameter EQ1. During the time intervals t13 and t23, the equalizer control circuit 156 outputs the gain parameter EQ2 to the equalizer circuit 142. The equalizer circuit 142 generates a gain value of 6 dB corresponding to the gain parameter EQ2 according to the gain parameter EQ2. During the time interval t14 and t24, the equalizer control circuit 156 outputs the gain parameter EQ3 to equal converter circuit 142. The equalizer circuit 142 generates a gain value of 9 dB corresponding to the gain parameter EQ3 according to the gain parameter EQ3. The above-mentioned correspondence between gain parameters and gain values is only for illustrative purposes, and the embodiments of the present disclosure are not limited thereto.

In some embodiments, the equalizer circuit 142 amplifies the test signal through the gain value, and then transmits the amplified test signal to the sampling circuit 144. The sampling circuit 144 generates test data TD based on the amplified test signal, and converts the test data into TD. TD is sent to comparison circuit 152. On the other hand, the reference circuit 158 outputs the reference RD to the comparison circuit 152 . After comparing the test data TD and the reference material RD, the comparison circuit 152 generates a comparison result.

In some embodiments, the comparison circuit 152 compares the number of difference bits between the test data TD and the reference material RD as the comparison result. In some embodiments, the comparison circuit 152 compares the number of error bits in the test data TD relative to the reference RD to serve as the comparison result.

For example, in the time interval t21, the comparison circuit 152 of the sub-source driver 132-1 compares the test data TD1 generated according to the test signal TS1 and the reference RD, and determines the difference between the test data TD1 and the reference RD. The number of bits is 100 bits, so the comparison result corresponding to the gain parameter EQ0 is 100 bits. For another example, in the time interval t21, the comparison circuit 152 of the sub-source driver 132-2 compares the test data TD1 generated according to the test signal TS1 and the reference RD, and determines the difference between the test data TD1 and the reference RD. The number of difference bits is 60 bits, so for The comparison result corresponding to the gain parameter EQ0 is 60 bits. The rest of the comparison results are deduced in the same way and will not be described in detail here.

In some embodiments, the alignment signal TA is included between the clock signals CLK1 to CLK4 and the test signals TS1 to TS4. The alignment signal TA is used to align the test data TD and the reference material RD in timing.

See Figure 6. Figure 6 is a schematic diagram of a comparison result 600 according to some embodiments of the present disclosure. As shown in Figure 6, the test data TD includes clock data, header data, first test data, and second test data in order. The reference material RD includes the alignment data, the first reference material, and the second reference material in this order. The alignment data is used to align the first test data of the test data TD and the first reference material of the reference RD in time sequence. Whenever the test data differs from the reference, the number of error bits is increased by one. Assuming that the first test data and the first reference are the same, and the second test data and the second reference are different, the counter (not shown) is 0 at the first timing and is 1 at the second timing.

Please also refer to Figure 3. The memory 154 is used to store comparison results.

Please go back to picture 4. Step S450: After the comparison time interval ends, each of the sub-source drivers determines the optimal gain value of each sub-source driver based on the comparison result.

In some embodiments, the memory 154 in Figure 3 includes a processing circuit (not shown) for determining the optimal gain parameter of each sub-source driver, so that the sub-source driver can further determine the optimal gain. The optimal gain value corresponding to the parameter. In some embodiments, the best comparison result is the one with the lowest number of error bits in the comparison result, and the best gain parameter is the gain parameter with the lowest number of error bits in the comparison result.

For example, please also see Figure 5. For the sub-source driver 132-1, the optimal gain parameter is the gain parameter EQ2 with the lowest number of error bits. For the sub-source driver 132-2, the optimal gain parameter is the gain parameter EQ3 with the lowest number of error bits.

Step S470: During the display time interval, the transmission end circuit transmits the data signal to the sub-source driver, and the sub-source driver outputs the data signal to the active area panel according to the optimal gain value of each sub-source driver, so that the active area panel display screen.

Please also refer to Figure 5. In some embodiments, the display time interval TI3 includes a switching time interval TI40, a return time interval TI41, and a general display time interval TI42.

In the switching time interval TI40, the control signal SW1 switches from a low voltage level to a high voltage level.

In the return time interval TI41, the sub-source driver 132 sequentially transmits the comparison results to the timing controller 110 via the control signal SW2. In some embodiments, the sub-source driver 132 receives the differential signal S transmitted by the timing controller 110, and returns the comparison result to the timing controller in sequence according to the clock signal and the return trigger signal in the differential signal S. 110.

For example, in the time interval t15, the sub-source driver 132-1 receives the feedback trigger signal FBEN which is at a high voltage level, and the sub-source driver 132-2 receives the feedback trigger signal FBEN which is at a low voltage level. Therefore, in the time interval t16, the sub-source driver 132-1 returns the comparison result of the sub-source driver 132-1 to the processing circuit 114 of the timing controller 110 (ie, the Rx1 return in FIG. 5). In the time interval t25, the sub-source driver 132-1 receives the return trigger signal FBEN which is at a low voltage level, and the sub-source driver 132-2 receives the return trigger signal FBEN which is at a high voltage level. Therefore, in the time interval t25 At t26, the sub-source driver 132-2 returns the comparison result of the sub-source driver 132-2 to the processing circuit 114 of the timing controller 110 (ie, the Rx2 return in Figure 5).

In some embodiments, if the processing circuit 114 determines that the comparison result returned by the sub-source driver 132 is not ideal, for example, the processing circuit 114 determines that the number of error bits in the comparison result returned by the sub-source driver 132-1 is too high. , then the processing circuit 114 adjusts the amplitude or pre-emphasis value of the display device 100 and re-executes the comparison mode after adjusting the amplitude or pre-emphasis value of the display device 100 .

In some embodiments, during the display time interval TI3, when the clock signal of the sub-source driver 132 loses lock, the sub-source driver 132 returns the lock status of the sub-source driver 132 to the timing controller 110 via the control signal SW2. . In some embodiments, the sub-source driver 132 pulls the voltage level of the control signal SW2 to a low voltage level, so that the timing controller 110 knows that the clock signal of the sub-source driver 132 is out of lock, and the timing controller 110 also The clock signal is re-transmitted to the sub-source driver 132 to re-lock the clock signal of the sub-source driver 132 .

In the general display time interval TI42, the sub-source driver 132 outputs a data signal to the active area panel 170 according to the optimal gain value of each sub-source driver 132, so that the active area panel 170 displays a picture.

Please also refer to Figure 3. In the normal display time interval TI42, the control signal SW1 is at a high voltage level, the memory 154 is connected to the equalizer circuit 142, and transmits the optimal gain parameter to the equalizer circuit 142.

For example, the memory 154 of the sub-source driver 132-1 transmits the optimal gain parameter EQ2 of the sub-source driver 132-1 to the equalizer circuit 142 of the sub-source driver 132-1. After receiving the data signal (for example, RGB data signal), the sub-source driver 132-1 amplifies the data signal according to the optimal gain value corresponding to the optimal gain parameter EQ2, and transmits the amplified data signal to the active area panel 170 , so that the active area panel 170 displays the picture.

Similarly, the memory 154 of the sub-source driver 132-2 transmits the optimal gain parameter EQ3 of the sub-source driver 132-2 to the equalizer circuit 142 of the sub-source driver 132-2. After receiving the data signal (for example, RGB data signal), the sub-source driver 132-2 amplifies the data signal according to the optimal gain value corresponding to the optimal gain parameter EQ3, and transmits the amplified data signal to the active area panel 170 , so that the active area panel 170 displays the picture.

Please go back to picture 1. In some embodiments, the scan driver 150 in FIG. 1 outputs a plurality of scan signals to the active area panel 170 , and the active area panel 170 then outputs a plurality of scan signals based on the scan signals output by the scan driver 150 and a plurality of data output by the source driver 130 Signal display screen.

It should be noted that the numbers of clock signals, data signals, gain parameters, etc. as shown in Figure 5 are only for illustration, and this embodiment is not limited to the above.

As can be seen from the above embodiments of the present disclosure, the embodiments of the present disclosure provide a display device and a signal quality adjustment method, and in particular, a display device and a signal quality adjustment method related to signal attenuation compensation. The adjustment circuit changes the compensation gain. values and compare test data with reference materials, and then select the best compensation gain from all comparison results. In this way, there is no need for manual adjustment of the compensation value setting, and there is no need for more control components, which can reduce costs, reduce human development time, and increase product commonality.

In addition, the above illustrations include sequential exemplary steps, but the steps need not be performed in the order shown. It is within the scope of this disclosure to perform these steps in a different order. These steps may be added, substituted, changed in order and/or omitted as appropriate within the spirit and scope of the embodiments of the present disclosure.

Although the present disclosure has been disclosed in the form of implementation, it is not intended to limit the present disclosure. Anyone familiar with this art can make various modifications and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection of the present disclosure is The scope shall be determined by the appended patent application scope.

100:Display device 110: Timing controller 130: Source driver 150:Scan drive 170: Active area panel

112-1, 112-2, 112-N: Transmission circuit

132,132-1,132-2,132-N: Sub-source driver

S, S1, S2, SN: differential signal

114: Processing circuit

SW1, SW2: control signal

134: Receiver circuit

136:Adjust circuit

TD, TD1, TD2, TD3, TD4: test data

RD: reference materials

H: high voltage level

L: low voltage level

CLK: clock signal

142: Equalizer circuit

144: Sampling circuit

146: Phase lock circuit

152:Comparison circuit

154:Memory

156: Equalizer control circuit

158:Reference circuit

400: Signal quality adjustment method

S410, S430, S450, S470: steps

Rx1-EQ, Rx2-EQ: signal

Rx1-Error, Rx2-Error: signal

TI1, TI3, TI40, TI41, TI42: time interval

t11,t21,t12,t22,t13,t23: time interval

t14,t24,t15,t16,t25,t26: time interval

CLK1, CLK2, CLK3, CLK4: clock signal

TA: alignment signal

TS1, TS2, TS3, TS4: test signal

FBEN: Return trigger signal

EQ0, EQ1, EQ2, EQ3: gain parameters

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: Figure 1 is a schematic diagram of a display device according to some embodiments of the present disclosure; Figure 2 is a partial schematic diagram of the display device in Figure 1 according to some embodiments of the present disclosure; Figure 3 is a schematic diagram of a portion of a sub-source driver according to some embodiments of the present disclosure; Figure 4 is a flow chart of a signal quality adjustment method according to some embodiments of the present disclosure; Figure 5 is a schematic diagram of a timing diagram according to some embodiments of the present disclosure; and Figure 6 is a schematic diagram of a comparison result according to some embodiments of the present disclosure.

132: Sub-source driver

S: Differential signal

SW1, SW2: control signal

134: Receiver circuit

136:Adjust circuit

TD: test data

RD: reference materials

H: high voltage level

L: low voltage level

142: Equalizer circuit

144: Sampling circuit

146: Phase lock circuit

152:Comparison circuit

154:Memory

156: Equalizer control circuit

158:Reference circuit

Claims (20)

A display device includes: a source driver including a plurality of sub-source drivers; a timing controller coupled to the source driver, wherein the timing controller includes a plurality of transmission end circuits, wherein the transmission end circuits respectively Corresponding to one of the sub-source drivers, the transmission end circuits each transmit a differential signal to the corresponding one of the sub-source drivers; a scan driver is coupled to the timing A controller for outputting a plurality of scan signals; and an active area panel coupled to the source driver and the scan driver; wherein in a comparison time interval, the differential signal includes a plurality of clock signals and a plurality of Test signals, wherein the sub-source drivers are further used to generate a plurality of test data based on the test signals and a plurality of gain values, and the sub-source drivers generate a plurality of comparison results based on the test data and a reference material , and after the comparison time interval ends, an optimal gain value of each of the sub-source drivers is determined based on the comparison results; wherein in a display time interval, the differential signal includes a data signal, and the The sub-source driver outputs the data signal to the active area panel according to the optimal gain value of each of the sub-source drivers, so that the active area panel displays a plurality of pictures based on the data signal and the scanning signals. The display device of claim 1, wherein the timing controller is further used to transmit a first control signal to the sub-source drivers, wherein when the first control signal is a first voltage level, the The comparison time interval is compared, and when the first control signal is a second voltage level, the comparison time interval is ended. The display device of claim 2, wherein the timing controller is further used to transmit a second control signal to the sub-source drivers, wherein when the second control signal is a first voltage level, the sub-source drivers The sub-source drivers receive the clock signals, and when the second control signal is a second voltage level, the sub-source drivers receive the test signals. The display device of claim 3, wherein after the comparison time interval ends, the sub-source drivers are further used to return the comparison results in a time-shared manner through the first control signal, and through the second The control signal returns at least one locking state of the sub-source drivers. The display device of claim 1, wherein in a return time interval, the sub-source drivers are used to sequentially transmit the comparison results to the timing controller, and the timing controller is based on the comparisons. As a result, it is determined whether to adjust an amplitude or a pre-emphasis value of the display device. The display device as claimed in claim 1, wherein the sub-source drivers respectively include: a receiving end circuit for receiving the differential signal; and an adjustment circuit coupled to the receiving end circuit for receiving a first control signal transmitted by the timing controller; wherein when the first control signal is When the first control signal is a second voltage level, the display device operates in a comparison mode. When the first control signal is a second voltage level, the display device operates in a display mode. The display device of claim 6, wherein in the display mode, the adjustment circuit is further used to transmit an optimal gain parameter corresponding to the optimal gain value to the receiving circuit. The display device of claim 6, wherein the adjustment circuit includes: a comparison circuit for comparing the test data and the reference material to generate the comparison results; a memory coupled to the comparison circuit A pairing circuit for storing the comparison results and determining the best gain value corresponding to an optimal comparison result among the comparison results; and an equalizer control circuit for the comparison In pair mode, a plurality of gain parameters are output to the receiving end circuit. The display device of claim 6, wherein the adjustment circuit is further used to receive a second control signal transmitted by the timing controller; wherein in the comparison mode, the adjustment circuit is further used to receive a second control signal according to the second control signal. The control signal transmits a plurality of gain parameters to the receiving end circuit, so that the receiving end circuit generates the gain values according to the plurality of gain parameters. The display device of claim 9, wherein the receiving circuit includes: an equalizer circuit for receiving the differential signal, and receiving the gain parameters in the comparison mode, and receiving the gain parameters in the display mode. sending an optimal gain parameter among the gain parameters; a phase lock circuit for receiving the clock signals transmitted from the equalizer circuit when the second control signal is a first voltage level; and a sampling circuit for receiving the test signals transmitted from the equalizer circuit when the second control signal is a second voltage level. A signal quality adjustment method suitable for a display device, wherein the display device includes a source driver and a timing controller, wherein the source driver includes a plurality of sub-source drivers, and the timing controller includes a plurality of transmission end circuits, The transmission end circuits respectively correspond to a corresponding sub-source driver among the sub-source drivers, and the signal quality adjustment method includes: in a comparison time interval, the transmission end circuits transmit a plurality of time pulse signals and a plurality of test signals to the sub-source drivers; during the comparison time interval, each of the sub-source drivers generates a plurality of test data based on the test signals, and based on the test data Generate multiple comparison results with a reference material; After the comparison time interval ends, each of the sub-source drivers determines an optimal gain value of each of the sub-source drivers based on the comparison results; and in a display time interval, by The transmission end circuits transmit a plurality of data signals to the sub-source drivers, and the sub-source drivers output the data signals to an active area panel according to the optimal gain values of the sub-source drivers. , so that the active area panel displays multiple screens. The signal quality adjustment method as described in claim 11 further includes: sending a first control signal from the timing controller to the sub-source drivers, wherein when the first control signal is a first voltage level, The comparison time interval is started, and when the first control signal is a second voltage level, the comparison time interval is ended. The signal quality adjustment method described in claim 12 further includes: sending a second control signal from the timing controller to the sub-source drivers, wherein when the second control signal is a first voltage level, The sub-source drivers receive the clock signals, and when the second control signal is a second voltage level, the sub-source drivers receive the test signals. The signal quality adjustment method as described in claim 13 further includes: after the comparison time interval ends, the sub-source drivers return the comparison results in a time-shared manner through the first control signal, and through the The second control signal returns at least one locking state of the sub-source drivers. The signal quality adjustment method as described in claim 11 further includes: in a return time interval, the sub-source drivers sequentially transmit the comparison results to the timing controller, and the timing controller is based on the These comparison results determine whether to adjust an amplitude or a pre-emphasis value of the display device. As for the signal quality adjustment method described in claim 11, each of the sub-source drivers includes a receiving end circuit and an adjustment circuit, wherein the signal quality adjusting method further includes: receiving by the receiving end circuit the clock signals, the test signals and the data signals; and the adjustment circuit receives a first control signal transmitted by the timing controller, wherein when the first control signal is a first voltage level , the display device operates in a comparison mode, wherein when the first control signal is a second voltage level, the display device operates in a display mode. The signal quality adjustment method described in request item 16 further includes: In the display mode, the adjustment circuit transmits an optimal gain parameter corresponding to the optimal gain value to the receiving circuit. The signal quality adjustment method as described in claim 16, wherein the adjustment circuit includes a comparison circuit, a memory and an equalizer control circuit, wherein the signal quality adjustment method further includes: comparing the comparison circuit with the Some test data and the reference material are used to generate the comparison results; the memory stores the comparison results, and determines the best gain value corresponding to an optimal comparison result among the comparison results. ; and the equalizer control circuit outputs a plurality of gain parameters to the receiving end circuit in the comparison mode. The signal quality adjustment method as described in claim 16 further includes: in the comparison mode, the adjustment circuit transmits a plurality of gain parameters to the receiving end circuit according to a second control signal transmitted by the timing control signal, So that the receiving end circuit generates the gain values according to the plurality of gain parameters. The signal quality adjustment method as described in claim 19, wherein the receiving end circuit includes an equalizer circuit, a phase lock circuit and a sampling circuit, wherein the signal quality adjustment method further includes: the equalizer circuit in the Receive these gain parameters in comparison mode, And receive an optimal gain parameter among the gain parameters in the display mode; when the second control signal is a first voltage level, the phase lock circuit receives the gain parameters transmitted by the equalizer circuit. a clock signal; and the sampling circuit receives the test signals transmitted from the equalizer circuit when the second control signal is a second voltage level.

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