KR100876903B1 - General?purpose wideband amplifier integrated circuit and device - Google Patents

Abstract

The single-stage amplifier includes (1) first and second "gain" transistors connected in a common source configuration; (2) first and second resistors respectively providing self-biasing for the first and second transistors; (3) first and second current sources providing bias currents for the first and second transistors, respectively; And (4) a load impedance connected between the drains of the first and second transistors. The amplifier includes (5) third and fourth "compensation" transistors connected in parallel with the first and second transistors and used to compensate for eddy current capacitances of the first and second transistors; And (6) third and fourth resistors that provide their own biasing for the third and fourth transistors, respectively. Variable gain can be achieved by changing the bias current for the gain transistors. The two-stage amplifier may consist of two stages connected in a cascade fashion, each stage comprising most or all circuit elements of a single-stage amplifier.

Description

General Purpose Broadband Amplifier Integrated Circuit and Device {GENERAL―PURPOSE WIDEBAND AMPLIFIER INTEGRATED CIRCUIT AND DEVICE}

This application claims the priority of US Provisional Application No. 60 / 576,759, filed June 2, 2004 under the name "Universal Broadband Amplifier."

The present invention relates generally to circuits, in particular general purpose broadband amplifiers.

Amplifiers are usually used to amplify signals to obtain the proper signal level. Amplifiers are also widely used for a variety of applications such as communication, computing, networking, consumer electronics, and so on. For example, during wireless communications, amplifiers may be used on the transmission path to amplify a signal prior to transmission on the wireless channel and may be used on the reception path to amplify a signal received on the wireless channel.

The amplifier can be designed to provide either fixed gain or variable gain. Variable gain amplifiers (VGA) are commonly used in communications circuits (eg, receivers and transmitters) to provide variable gains and adjustable signal levels depending on operating conditions, system requirements, and / or other factors. do. For example, VGAs are commonly used to control power in wireless communication systems. In a code division multiple access (CDMA) system, the signal from each radio (eg, cellular telephone or mobile handset) is spread out over the entire system band. The signal transmitted by each radio acts as an interference to the signals transmitted by other radios in the system. Thus, the transmit power of each radio is adjusted so that the received signal quality for the radio measured at the receiving base station is maintained at the target level. This power control achieves proper performance for the radio, minimizes interference to other radios and increases system capacity.

The wireless device may be located at any location relative to the receiving base station and may require different amounts of transmit power at different locations to achieve the target received signal quality at the base station. Typically, high transmit power is required when the radio is away from the base station, and low transmit power is required when the radio is close to the base station. In a CDMA system, a wireless device may be required to adjust its transmit power over a wide range (eg, above 90 decibels) to eliminate so-called near-far effects. This wide power control range is typically achieved by distributing variable gains throughout the entire transmission chain from the analog baseband to the radio frequency (RF) front end. Thus, power control can be achieved by VGAs placed throughout the transmission chain.

Amplifiers with a simple structure and good performance are difficult to design but are highly desirable for cost, power and other considerations. VGAs with the same features are very difficult to design. Therefore, there is a need for an amplifier having a simple structure and having good performance.

Various embodiments of a versatile general purpose wideband amplifier are described herein. The amplifier is simple in design and suitable for high frequency and / or wideband applications. The amplifier can be operated as a fixed gain amplifier or a wide dynamic range VGA.

Embodiments of a single-stage amplifier include first and second "gain" transistors, first and second resistors, first and second current sources, and load impedance. The first and second transistors are connected in a common source configuration, amplify the differential input signal, and provide a differential output signal. The first and second resistors are connected between the drain (or collector) and the gate (or base) of the first and second transistors, respectively, and provide self biasing for these transistors. The first and second current sources are connected to the drains of the first and second transistors, respectively, and provide a bias current to these transistors. The load impedance is connected between the drains of the first and second transistors.

The amplifier may further include third and fourth "compensation" transistors and third and fourth transistors. The third and fourth transistors are connected in parallel with the first and second transistors, respectively, and compensate for the gate-drain eddy capacitance of the first and second transistors, respectively. The third and fourth resistors provide self-biasing for the third and fourth transistors, respectively.

The transistors may be field effect transistors (FET), bipolar junction transistors (BJT), or the like. The load impedance can be a resistor, inductor, capacitor, or a combination thereof. The first and second current sources may provide a fixed amount or variable amount of bias current to the first and second transistors. Variable gain for the amplifier can be achieved by varying the bias current.

An embodiment of a two stage amplifier includes two stages connected in a cascade fashion. Each stage includes first and second gain transistors, first and second transistors, first and second current sources, and first and second load impedances. The circuit elements of each stage are connected in the same way for a single-stage amplifier despite the first and second load impedances connected in series and connected between the drains of the first and second transistors. The first and second transistors for each stage receive and amplify the differential input signal for the stage and provide a differential output signal for the stage. The common node is formed between the first and second load impedances for each stage. Common nodes for both stages may be connected together to provide (1) biasing for the second stage, and (2) negative feedback for common-mode rejection. Compensation transistors can be used for each stage.

Various aspects and embodiments of the invention are further described below.

The features and properties of the present invention will become more apparent upon consideration of the following detailed description with reference to the drawings in which like reference numerals represent like means.

1 shows a single-stage amplifier.

2 shows a single-stage amplifier with compensation transistors.

3 shows a two-stage amplifier.

4 shows a two-stage amplifier with compensation transistors.

5 shows a multi-stage amplifier.

6 shows a cascade current mirror used to supply bias currents.

7 is a plot showing variable gain for a two-stage amplifier.

8 is a block diagram illustrating a wireless device.

The term "typically" is used herein to mean "use as an example." Any embodiment or design described herein “typically” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

1 shows a schematic diagram of a single-stage amplifier 100 according to one embodiment. Amplifier 100 includes gain transistors 120a and 120b connected in a common-source configuration. Transistor 120a is configured to receive a source (or emitter) connected to circuit ground, a gate (or bias) for receiving non-inverting input signal In + through AC coupling capacitor 124a, and an inverting output signal Out-. Has a drain (or collector) to provide. Transistor 120b has a source connected to circuit ground, a gate that receives an inverted input signal In- through an AC coupled capacitor 124b, and a drain that provides a non-inverted output signal Out +. Thus, the amplifier 100 receives the differential input signals In + and In- and provides the differential output signals Out + and Out-.

Resistor 122a is connected between the drain and gate of transistor 120a and provides self-biasing for transistor 120a. Similarly, resistor 122b is connected between the drain and gate of transistor 120b and provides self-biasing for transistor 120b. The drain of transistor 120a is connected to current source 150a and the drain of transistor 120b is connected to current source 150b. The load impedance 140 is connected to the drains of the transistors 120a and 120b.

In the embodiment shown in FIG. 1, transistors 120a and 120b are N-channel FETs (N-FETs). In general, transistors 120a and 120b are, for example, P-channel FETs (P-FETs), BJTs, gallium arsenide (GaAs) FETs, hetero-junction bipolar transistors (HBT), high electron mobility transistors Any type such as HEMT may be a transistor. For clarity, the following description assumes that the transistors are N-channel FETs.

The load impedance 140 may be the resistive load shown in FIG. 1, suitable for a broadband amplifier. The load impedance 140 may be a reactive load (eg, inductor) suitable for narrowband amplifiers. Load impedance 140 may also be a composite load with resistive and reactive elements.

Current sources 150a and 150b provide bias current for transistors 120a and 120b, respectively. The current sources 150a and 150b may provide a fixed / constant bias current amount. Optionally, current sources 150a and 150b may provide a variable amount of bias current based on the control signal. The gain of amplifier 100 can be adjusted by controlling the bias currents for transistors 120a and 120b as described below.

Amplifier 100 may be used for wideband and / or high frequency applications because the nodes of amplifier 100 are of low impedance. The impedances at the output nodes Out + and Out− are determined by the load impedance 140.

Each transistor 120 has a transconductance (denoted as g _m ) that is determined by the transistor type, operating range, and bias current for the transistor (denoted as I _D ). A bias current for each transistor 120, referred to as a drain or collector current, is provided by the associated current source 150.

The transconductance g _m as a function of drain current I _D for a metal oxide semiconductor FET (MOSFET) operating in the saturation region for the long channel model can be expressed as

수식(1)

Formula (1)

는 전하 캐리어 이동도이며;here,

Is the charge carrier mobility;

는 단위면적당 게이트 산화물 커패시턴스이며;

Is the gate oxide capacitance per unit area;

W is the channel width for the transistor;

L is the channel length for the transistor.

These various parameters for transistors are known.

The transconductance g _m as a function of drain current I _D for a MOSFET operating in the sub-threshold region can be expressed as

수식(2)

Formula (2)

는 비식별 인자이며, V_T는 열 전압이다.here,

Is the non-identification factor and V _T is the thermal voltage.

The transconductance g _m as a function of the drain current I _D for the bipolar junction transistor in normal operation can be expressed as

수식(3)

Formula (3)

As described in equations (1) and (2), different types of transistors and different operating regions are associated with different functions for transconductance g _m versus drain current I _D. Other transistor types and operating regions can have different functions for transconductance versus drain current.

은 다음과 같이 표현될 수 있다.Regardless of how the transconductance g _m can be expressed, the gain of each transistor 120 of the single-stage amplifier 100

Can be expressed as

수식(4)

Formula (4)

에 대한 더 정확한 수식은 부하 임피던스(140), 전류 소스들(150a, 150b)의 N-FET들(120a, 120b) 및 P-FET들에 대한 와류 커패시턴스 및 출력 저항, 및 외부 부하(예컨대, 다음 스테이지의 N-FET들의 입력 커패시턴스)으로 수식(4)의 부하 임피던스 Z를 대체함으로서 획득될 수 있다. 부하(140)의 임피던스는 전형적으로 와류 및 외부 부하들의 임피던스보다 훨씬 작다(더 우세하다). 수식(4)은 각각의 트랜지스터(120)의 이득

이 트랜스컨덕턴스 g_m과 직접 관련된다는 것을 표시한다. 증폭기(100)의 이득은 차동 설계시 각각의 트랜지스터(120)의 이득

의 2배이다. 앞의 수식들에 의하여 기술된 바와같이, 가변 이득은 트랜지스터들(120a, 120b)의 드레인 전류 I_D를 조절함으로서 증폭기(100)에서 획득될 수 있으며, 이는 각각의 트랜지스터의 트랜스컨덕턴스 g_m을 변화시키고, 그 다음에 g_m을 변화는 트랜지스터의 이득

을 변화시킨다. 증폭기(100)는 이하에 기술된 바와같이 VGA로서 사용될 수 있다.Where Z is the load impedance 140. For simplicity, equation (4) does not include external or parasitic loads. benefit

A more accurate formula for load impedance 140, eddy current capacitance and output resistance for N-FETs 120a, 120b and P-FETs of current sources 150a, 150b, and external load (e.g., Input capacitance of the N-FETs of the stage) can be obtained by substituting the load impedance Z of equation (4). The impedance of the load 140 is typically much smaller (more prevalent) than the impedance of the vortex and external loads. Equation (4) is the gain of each transistor 120

Indicates that it is directly related to this transconductance g _m . The gain of the amplifier 100 is the gain of each transistor 120 in the differential design

2 times As described by the above equations, the variable gain can be obtained in the amplifier 100 by adjusting the drain current I _D of the transistors 120a and 120b, which changes the transconductance g _m of each transistor. Then change g _m to the gain of the transistor

To change. Amplifier 100 may be used as a VGA as described below.

Resistors 122a and 122b provide self-biasing for transistors 120a and 120b, respectively. Self-biasing each transistor 120 through a resistor 122 provides various advantages. First, the biasing circuit is very simplified. Second, accurate control of the transconductance g _m of each transistor 120 is such that the transistor is a diode connected by a resistor 122 and the voltages at all four nodes of the transistor (gate, source, drain and bulk) are very high. It is possible because it is limited. Third, the drain current I _D can be easily changed to change the biasing of the transistor 120. AC-coupled capacitances 124a and 124b connect different input signals In + and In- to the gates of transistors 120a and 120b, respectively, to prevent affecting the self-biasing of these transistors. To be used.

2 is a schematic block diagram of a single-stage amplifier 102 according to another embodiment. Amplifier 102 includes all circuit elements of amplifier 100 of FIG. 1. Moreover, amplifier 102 further includes compensation resistors 130a and 130b, resistors 132a and 132b and capacitors 134a and 134b. Transistor 130a is connected in parallel with transistor 120a and has a source connected to circuit ground and a drain connected to the drain of transistor 120a. Resistor 132a has one end connected to the gate of transistor 130a and the other end connected to circuit ground. Capacitor 134a has one end connected to the gate of transistor 130a and the other end for receiving the inverting input signal In-. Similarly, transistor 130b is connected in parallel with transistor 120b and has a source connected to circuit ground and a drain connected to the drain of transistor 120b. Resistor 132b has one end connected to the gate of transistor 130b and the other end connected to the circuit ground. Capacitor 134b has one end connected to the gate of transistor 130b and the other end for receiving the non-inverting input signal In +. Thus, transistors 130a and 130b receive In− and In + input signals at their gate through AC coupling capacitors 134a and 134b, respectively, and their own vias to circuit ground by transistors 132a and 132b, respectively. It is fresh.

를 각각 가진다. 이러한 와류 커패시턴스

는 여러가지 악영향을 유발한다. 첫째, 와류 커패시턴스

는 증폭기의 대역폭을 감소시킨다. 둘째, 와류 커패시턴스

는 증폭기의 동적 범위를 제한한다. 동적 범위는 증폭기에 의하여 실현가능한 큰 신호 레벨 대 작은 신호 레벨의 비이다. 누설 전류는 와류 커패시턴스

를 통해 각각의 트랜지스터(120)의 드레인 및 게이트 사이에 흐른다. 트랜스컨덕턴스 g_m가 작을때, 와류 커패시턴스

를 통해 흐르는 누설 전류는 비교적 크며, 이는 감소된 동적 범위를 야기한다. 와류 커패시턴스

는 전형적으로 작으며, 누설 전류가 신호 전류와 동등하지(comparable) 않다면 보통 성능을 저하시키지 않는다. Transistors 120a and 120b are parasitic capacitors between the drain and gate of the transistor

Each has Such eddy current capacitance

Causes various adverse effects. First, eddy current capacitance

Reduces the bandwidth of the amplifier. Second, eddy current capacitance

Limits the dynamic range of the amplifier. Dynamic range is the ratio of large signal level to small signal level achievable by an amplifier. Leakage Current Vortex Capacitance

It flows through the drain and the gate of each transistor 120 through. Vortex capacitance when transconductance g _m is small

The leakage current flowing through is relatively large, which results in a reduced dynamic range. Eddy Current Capacitance

Is typically small and usually does not degrade performance unless the leakage current is compatible with the signal current.

의 악영향들을 완화시키기 위하여 사용되는 보상 트랜지스터들이다. 트랜지스터들(130a, 130b)은 이들 트랜지스터들의 각각이 트랜지스터의 게이트 및 드레인사이에서 동일한 와류 커패시턴스

를 가진다. 트랜지스터들(130a, 130b)은 각각 트랜지스터들(120a, 120b)에 대한 In+ 및 In- 입력신호들과 반대 극성을 가지는 In- 및 In+ 입력신호들에 의하여 구동된다. 따라서, 트랜지스터(130a)를 통해 흐르는 누설 전류는 트랜지스터(120a)를 통해 흐르는 누설전류와 반대 극성을 가진다. 양 트랜지스터들(120a, 130a)의 드레인들을 통해 흐르는 순(net) 누설전류는 대략 0이며, 트랜지스터(120a)의 와류 커패시턴스

는 트랜지스터(130a)에 의하여 효과적으로 보상된다. 트랜지스터(130a)는 게이트가 저항기(132a)를 통해 회로 접지에 바이어싱되어 증폭기(102)의 이득에 최소로 영향을 미치기 때문에 0의 트랜스컨덕턴스 g_m를 가진다. 트랜지스터(130b)는 트랜지스터(130a)가 트랜지스터(120a)의 와류 커패시턴스

를 보상하는 방식으로 트랜지스터(120b)의 와류 커패시턴스

를 보상한다. 트랜지스터들(130a, 130b)은 차동 입력 신호(In+ 및 In-)를 크게 감쇠시키도록 한다.Transistors 130a and 130b have eddy current capacitances of transistors 120a and 120b, respectively.

Compensation transistors that are used to mitigate the adverse effects of a. Transistors 130a and 130b have a eddy current capacitance in which each of these transistors is equal between the gate and the drain of the transistor.

Has Transistors 130a and 130b are driven by In- and In + input signals having opposite polarities to In + and In- input signals for transistors 120a and 120b, respectively. Therefore, the leakage current flowing through the transistor 130a has a polarity opposite to the leakage current flowing through the transistor 120a. The net leakage current flowing through the drains of both transistors 120a and 130a is approximately zero, and the eddy current capacitance of transistor 120a

Is effectively compensated by the transistor 130a. Transistor 130a has a transconductance g _m of zero because the gate is biased to circuit ground through resistor 132a to minimize the gain of amplifier 102. Transistor 130b has a eddy current capacitance of transistor 120a.

Vortex capacitance of transistor 120b in a manner that compensates for

To compensate. Transistors 130a and 130b allow to greatly attenuate the differential input signals In + and In−.

3 shows a schematic diagram of a two-stage amplifier 104 according to another embodiment. The amplifier 104 comprises two stages 110, 112 connected in a cascade manner.

The first stage 110 is provided with transistors 120a and 120b, resistors 122a and 122b, capacitors 124a and 124b, load impedances 140a and 140b, and current sources 150a and 150b. Self-biased pseudo-differential amplifier. Transistors 120a and 120b, resistors 122a and 122b, capacitors 124a and 124b and current sources 150a and 150b are connected in the manner described above with respect to FIG. The gate bias of transistors 120a and 120b is set by current sources 150a and 150b through resistors 122a and 122b, respectively. Load impedances 140a and 140b are connected in series and to the drains of transistors 120a and 120b. The load impedances 140a, 140b are used as the load of the first stage 110 and may be resistors, inductors, capacitors or a combination thereof. Drains of the transistors 120a and 120b provide the differential input signals Out 1-and Out 1+ for the first stage 110. The first stage 110 is similar to the single-stage amplifier 100 shown in FIG. 1 except that the load impedance 140 of FIG. 1 is replaced by the load impedances 140a and 140b of FIG. 3.

The second stage 112 is composed of transistors 160a and 160b, load impedances 180a and 180b, and current sources 190a and 190b, which are transistors 120a and 120b of the first stage, It is connected in the same manner as the load impedances 140a and 140b and the current sources 150a and 150b. Gates of transistors 160a and 160b that are differential inputs to second stage 112 are connected to drains of transistors 120a and 120b that are differential outputs of first stage 110, respectively. Load impedances 180a and 180b are connected in series and to the drains of transistors 160a and 160b. The load impedances 180a, 180b are used as the load of the second stage 112 and may be resistors, inductors, capacitors or a combination thereof. The load impedances 140a and 140b for the first stage 110 and the load impedances 180a and 180b for the second stage 112 may be independently selected based on the application in which the amplifier 104 is to be used. . For example, load impedances 140a and 140b may be resistors, and load impedances 180a and 180b may be parallel resonator tanks. Current sources 190a and 190b are connected to the drains of transistors 160a and 160b, respectively, and provide bias current for these transistors. The drains of the transistors 160a and 160b provide differential output signals Out + and Out− to the second stage 112, which is another output signal to the amplifier 104.

In the embodiment shown in FIG. 3, the common node C1 of the load impedances 140a and 140b for the first stage 110 is connected to the load impedances 180a and 180b for the second stage 112. It is connected to the common node C2. This connection of node C1 to node C2 provides several advantages. First, the connection sets the drain voltage of the transistors 160a, 160b of the second stage 112 appropriately. In an ideal case, this drain voltage is equal to the gate bias voltage of transistors 160a and 160b, and transistors 160a and 160b are biased at the same operating point as transistors 120a and 120b. However, mismatches of transistors and current sources will generate different drain voltages for transistors 120a and 120b of first stage 110 and transistors 160a and 160b of second stage 112, This causes a gain control error. In general, such mismatches cause secondary phenomena. Thus, transistors 160a, 160b of second stage 112 obtain biasing from first stage 110, and self-biasing resistors are not needed for transistors 160a, 160b. Second, this connection provides a negative feedback loop between the two amplification stages. The feedback loop provides rejection of the common mode voltages supplied to the differential inputs In + and In− of the first stage 110 and includes a common-mode including power supply noise provided in the common mode for the amplifier 104. It helps to suppress the noise.

4 shows a schematic diagram of a two-stage amplifier 106 according to another embodiment. The amplifier 106 comprises a first stage 114 and a second stage 116 connected in a cascade manner. The stages 114, 116 include all circuit elements of the stages 110, 112 of the amplifier 104 in FIG. 3. Moreover, the first stage 114 of the amplifier 106 further includes compensation transistors 130a and 130b, biasing resistors 132a and 132b, and AC coupling capacitors 134a and 134b. The second stage 116 of the amplifier 106 further includes compensation transistors 170a, 170b, biasing resistors 172a, 172b, and AC coupling capacitors 174a, 174b.

In the first stage 114, the compensation transistors 130a and 130b are connected in parallel with the transistors 120a and 120b, respectively. Resistors 132a and 130b provide biasing for transistors 130a and 130b, respectively. Capacitors 134a and 134b provide AC coupling of In- and In + input signals to the gates of transistors 130a and 130b, respectively. Compensation transistors 130a and 130b are cross-excited and receive input signals complementary to their corresponding gain transistors 120a and 120b, respectively. In the second stage 116, the compensation transistors 170a, 170b are connected in parallel with the transistors 160a, 160b, respectively. Resistors 172a and 172b provide biasing for transistors 170a and 170b, respectively. Capacitors 174a and 174b provide an AC coupling of Out1 + and Out1- signals from first stage 114 to gates of transistors 170a and 170b, respectively. Compensation transistors 170a and 170b receive signals complementary to corresponding gain transistors 160a and 160b, respectively.

를 통해 누설 전류를 완화시킬 수 있다. 유사하게, 보상 트랜지스터들(170a, 170b)은 각각 트랜지스터들(160a, 160b)의 와류 커패시턴스

를 통해 누설 전류를 완화시킬 수 있다. 보상 트랜지스터들(130a, 130b, 170a, 170b)의 게이트들은 각각 저항기들(132a, 132b, 172a, 172b)을 통해 회로 접지에 바이어싱된다. 그러므로, 이들 보상 트랜지스터들은 0의 트랜스컨덕턴스 g_m를 가지며 이에 따라 증폭기(106)의 이득에 최소로 영향을 미친다.Compensation transistors 130a and 130b have gate-drain eddy current capacitances of transistors 120a and 120b, respectively.

The leakage current can be mitigated through Similarly, compensating transistors 170a and 170b may be the eddy current capacitances of transistors 160a and 160b, respectively.

The leakage current can be mitigated through Gates of compensation transistors 130a, 130b, 170a, 170b are biased to circuit ground through resistors 132a, 132b, 172a, 172b, respectively. Therefore, these compensation transistors have a transconductance g _m of zero and thus minimally affect the gain of the amplifier 106.

5 shows a block diagram of a multi-stage amplifier 108 according to another embodiment. Amplifier 108 includes N stages 510a through 510n, where N can be any integer greater than one. The first stage 510a may be implemented as the first stage 110 of FIG. 3 or the first stage 114 of FIG. 4. Each of the next stages 510a to 510n may be implemented as the second stage 112 of FIG. 3 or the second stage 116 of FIG. 4. The first stage 510a receives differential input signals In + and In− for the amplifier 500. The differential output of each stage 510 is connected to the differential input of the next stage except for the last stage 510n. The final stage 510n provides the differential output signals Out + and Out- for the amplifier 500. Common nodes of the load impedances for all stages 510a-510n can be connected together as shown in FIG. 5 to provide biasing and common-mode feedback as described above with respect to FIG. 3. Optionally, common nodes for N stages 510 may be connected via bias circuits not shown in FIG. 5.

In normal operation, the gain of each amplifier stage is the product of the transistor transconductance g _m and the load impedance Z for that stage, as described in equation (4). For the amplifiers 104, 106, 108 of FIGS. 3, 4, and 5, each having two or more stages, the overall gain of the amplifier is the product of the linear gain of the individual stages (or sum of logarithmic gains).

에 영향을 미친다. 가변 이득 전류는 다양한 회로 설계들을 사용하여 제공될 수 있다.Each amplifier shown in FIGS. 1-5 can be operated as a fixed gain amplifier or a variable gain amplifier (VGA). Gain control for VGA can be achieved by varying the drain current I _D affecting the transconductance g _m as described above, which in turn is transistor gain

Affects. Variable gain current can be provided using various circuit designs.

6 illustrates an embodiment of a wide-swing cascade current mirror 600 that can be used to supply variable bias currents for all gain transistors of the heavy amplifier. Current mirror 600 may be used for current sources 150a and 150b of FIGS. 1 and 2 and may provide drain current for gain transistors 120a and 120b of amplifiers 100 and 102. have. The current mirror 600 can be used for the current sources 150a, 150b, 190a, 190b of FIGS. 3 and 4, and the gain transistors 120a, 120b, 160a, 160b of the amplifiers 104, 106. Can provide drain currents for.

In the embodiment shown in FIG. 6, current mirror 600 provides bias current for K gain transistors, where K = 2 for single-stage amplifiers 100, 102 of FIGS. 1 and 2. And K = 4 for the two-stage amplifiers 104 and 106 of FIGS. 3 and 4. Current mirror 600 includes transistors 610, 612, current source 614, and K pairs of transistors 620a, 622a through 620k, 622k. For the embodiment shown in FIG. 6, all transistors are implemented with P-channel FETs. Transistors 610 and 612 and current source 614 are connected in series. Transistor 610 has a source connected to power supply V _DD , a gate connected to node D, and a drain connected to the source of transistor 612. Transistor 612 has a gate that receives bias voltage V _bias and a drain connected to one end of current source 614. The other end of current source 614 is connected to circuit ground. Current source 614 provides a reference current I _ref , which can be a fixed or adjustable current.

Pairs of transistors 620a, 622a through 620k, 622k are used to provide drain current I _D for the K gain transistors of the amplifier. Each pair for transistors 620i and 622i is connected in series with a pair of transistors 610 and 612 and in a current mirror configuration, where i = 1, ..., K. Thus, the gates of transistors 620a through 620k are connected together to the gate of transistor 610, and the sources of transistors 620a through 620k are connected to power supply V _DD . Gates of transistors 622a through 622k are connected together to the gate of transistor 612. The drains of the transistors 620a through 620k are connected to the sources of the transistors 622a through 622k, respectively. The drains of the transistors (622a) is a drain of the available drain current I _D for the first gain transistor and the drain of the transistor (622b) provides a drain current I _D for the second gain transistor, the transistor (622k) is K Provide the drain current I _D for the -th gain transistor.

Transistors 620a through 620k may have the same size and may be further scaled according to the sizes of K gain transistors that receive drain current through transistors 620a through 620k. Transistors 622a through 622k may have the same size and may be further scaled according to the sizes of K gain transistors. The sizes of the transistors 620i and 622i for each pair may be scaled in proportion to the sizes of the transistors 610 and 612 to achieve the proper drain current amount of the i-th gain transistor.

The amount of current flowing through each pair of transistors 620i and 622i (drain for the i-th gain transistor) for a given bias voltage V _bias supplied to the gate of transistor 612 and the gates of transistors 622a to 622k. The current I _D ) is determined by the ratio of (1) the reference current I _ref provided by the current source 614, and (2) the size of the transistors 620i, 622i to the size of the transistors 610, 612. . The drain current I _D can be adjusted by changing the reference current I _ref . A bias voltage V _bias provides a proper gate bias for transistor 612 and transistors 622a through 622k to keep the transistors away from the triode region. The bias voltage V _bias may be generated by a bias current not shown in FIG. 6.

The gain transistors for all stages of the amplifier can be equally biased with the same drain current I _D. This can be accomplished by ensuring that all K transistors 620a through 620k have the same size and that all K transistors 622a through 622k have the same size. Optionally, the gain transistors for each stage of the amplifier can be biased with a different drain current selected for that stage. For example, the drain current for the gain transistors of each stage can be determined based on the load on the stage, eg, the larger drain current for the large load. Different drain currents for the different stages can be obtained by ensuring that the transistors 620 and 622 used for each stage have an appropriate size.

FIG. 6 shows a specific design for the current sources of the amplifiers of FIGS. 1-5. Fixed or variable drain currents for the gain transistors may be provided with other known current source designs.

FIG. 7 shows a plot of the variable gain achievable by the two-stage amplifier 106 of FIG. 4. 7 relates to a typical CMOS VGA design at 850 MHz. In FIG. 7, the vertical axis shows the total gain (dB) for the two-stage amplifier, and the horizontal axis shows the control voltage V _ctrl (used to adjust the reference current I _ref of the current source 614 of the current mirror 600). Bolts). As shown in FIG. 7, a wide gain range of 60 decibels (dB) or more can be achieved by the amplifier 106 even in a simple circuit design.

The amplifier embodiments described herein provide the following advantages.

1. It provides very simple structure and simple transistor biasing method. Transistor size and bias current are all gain transistors biased to approximately the same gate voltage and V _gd is zero. This allows accurate gate control of the gain transistors.

2. DC coupling between stages eliminates coupling losses and saves die area for AC coupling capacitors.

3. All nodes of the amplifier are low impedance. Thus, the amplifier is inherently wideband and suitable for RF applications.

4. The compensation transistors can mitigate the leakage current flowing through the gate-drain eddy capacitance C _gd of the gain transistors. Thus, the amplifier can be used as a high attenuation amplifier.

5. A large range of gain control can easily be achieved, for example, 60 dB or more for the typical design of the two-stage amplifier 106 of FIG. The gain range is determined by the dynamic range of the drain current.

The amplifier described herein may be used for a variety of broadband and / or high frequency applications such as communications, networking, computing, consumer electronics, and the like. Amplifiers include CDMA Systems, Time Division Multiple Access (TDMA) Systems, Pan-European Mobile Communications (GSM) Systems, Next Generation Mobile Phone Systems (AMPS), Satellite Positioning Systems (GPS), Multiple-Input Multiple-Output (MIMO) Systems, Quadrature It can be used in wireless communication systems such as frequency division multiplexing (OFDM) systems, orthogonal frequency division multiple access (OFDMA) systems, wireless local area networks (WLAN), and the like. The use of amplifiers for wireless communication is described below.

8 shows a block diagram of a wireless device 800 that may be used for wireless communication. Wireless device 800 may be a cellular telephone, a user terminal, a handset, a personal digital assistant (PDA) or any other device or design. The wireless device 800 may provide bidirectional communication through a transmission path and a reception path.

On the transmission path, a digital signal processor (DSP) 810 processes the traffic data and provides a stream of chips to the transceiver unit 820. Within the transceiver unit 820, one or more digital-to-analog converters (DACs) 822 convert the stream of chips into one or more analog signals. The analog signal (s) are amplified by amplifier (824), filtered by filter 826, amplified by variable gain by VGA 828 and from baseband to RF by mixer 830. The frequency is upconverted to generate an RF signal. Frequency upconversion is performed with a local oscillator (LO) signal from a voltage controlled oscillator (VCO) / phase-locked loop (PLL) 832. The RF signal is buffered by buffer 834, filtered by filter 836, amplified by power amplifier (PA) 838, routed through duplexer (D) 840, and antenna 842. Is sent).

On the receive path, the signal is received by antenna 842, routed through duplexer 840, amplified by low noise amplifier (LNA) 844, filtered by filter 846, and VGA 848. Is amplified with variable gain and frequency downconverted from RF to baseband by mixer 850 using LO signal from VCO / PLL 852. The down-converted signal is buffered by buffer 854, filtered by filter 856, amplified by amplifier 858, and digitized by one or more analog-to-digital converters (ADCs) 860. To generate one or more streams of samples. The sample stream (s) are provided to a digital signal processor 810 to perform the processing.

8 shows a specific transceiver design using a direct-conversion structure. In a typical transceiver, signal conditioning for each signal path may be performed by one or more stages of known amplifiers, filters, mixers, and the like. 8 shows some of the circuit blocks that can be used for signal conditioning. The amplifier described herein can be used for various amplifiers and buffers in the transmit and receive paths.

The amplifier described herein can be used for various frequency ranges including baseband, intermediate frequency (IF), RF, and the like. For example, the amplifier may be used for various frequency bands used for wireless communication as described below.

824 내지 894 MHz의 셀룰라 대역,

Cellular band of 824-894 MHz,

1850 내지 1990 MHz의 개인통신시스템(PCS) 대역,

Personal communications system (PCS) band from 1850 to 1990 MHz,

1710 내지 1880 MHz의 디지털 셀룰라 시스템(DCS) 대역,

1710 to 1880 MHz digital cellular system (DCS) band,

890 내지 960 MHz의 GSM900,

GSM900 from 890 to 960 MHz,

1920 내지 2170 MHz의 국제이동통신-2000(IMT-2000) 대역,

International Mobile Communication-2000 (IMT-2000) band of 1920 to 2170 MHz,

1574.4 내지 1576.4 MHz의 위성위치확인시스템(GPS) 대역.

Satellite positioning system (GPS) band from 1574.4 to 1576.4 MHz.

The amplifier described herein may be fabricated with a variety of integrated circuit (IC) processes such as complementary metal oxide semiconductor (CMOS), bipolar, bipolar-CMOS (Bi-CMOS), gallium arsenide (GaAs), and the like. Amplifiers can be manufactured from various types of ICs, such as radio frequency ICs (RFICs).

The foregoing description of the described embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and novel features described herein.

Claims (27)

First and second transistors connected in a common source configuration; A first resistor connected between the drain and the gate of the first transistor and operative to provide biasing to the first transistor; A second resistor connected between the drain and the gate of the second transistor and operative to provide biasing to the second transistor; First and second current sources connected to drains of the first and second transistors, respectively, and operative to provide bias current to the first and second transistors, respectively; And And a load impedance connected between the drains of the first and second transistors. 2. The general purpose broadband amplifier integrated circuit of claim 1, wherein the first and second current sources are operable to provide a variable amount of bias current to the first and second transistors, respectively. 2. The general purpose wideband amplifier integrated circuit of claim 1, wherein the first and second current sources are operable to provide a fixed amount of bias current to the first and second transistors, respectively. 2. The general purpose broadband amplifier integrated circuit of claim 1, wherein the first and second transistors are field effect transistors (FETs). 2. The general purpose broadband amplifier integrated circuit of claim 1, wherein the first and second transistors are metal-oxide semiconductor (MOS) transistors. 2. The general purpose wideband amplifier integrated circuit of claim 1, wherein the first and second transistors are bipolar junction transistors (BJTs). 2. The general purpose wideband amplifier integrated circuit of claim 1, wherein the load impedance is a resistor. 2. The general purpose wideband amplifier integrated circuit of claim 1, wherein the load impedance is a complex load consisting of resistive and reactive elements. The semiconductor device of claim 1, further comprising third and fourth transistors connected in parallel with the first and second transistors, respectively. Wherein the first and third transistors are operable to receive non-inverting and inverting input signals of the differential input signal, respectively, and the second and fourth transistors are operable to receive inverting and non-inverting input signals, respectively. Broadband amplifier integrated circuit. 10. The device of claim 9, further comprising: a third resistor connected to the gate and circuit ground of the third transistor; And And a fourth resistor connected to the gate and circuit ground of the fourth transistor. First and second transistors connected in a common source configuration; A first resistor connected between the drain and the gate of the first transistor and operative to provide biasing to the first transistor; A second resistor connected between the drain and the gate of the second transistor and operative to provide biasing to the second transistor; First and second current sources respectively connected to the drains of the first and second transistors and operative to provide bias currents to the first and second transistors, respectively; And And a load impedance connected to the drains of the first and second transistors. 12. The device of claim 11, further comprising third and fourth transistors connected in parallel with the first and second transistors, respectively. Wherein the first and third transistors are operable to receive the non-inverting and inverting input signals of the differential input signal, respectively, and the second and fourth transistors are operable to receive the inverting and non-inverting input signals, respectively. Broadband amplifier device. First and second transistors connected in a common source configuration and operative to receive the non-inverting and inverting input signals of the differential input signal, respectively; Third and fourth transistors connected in parallel with the first and second transistors, respectively, and operative to receive inverted and non-inverted input signals of the differential input signal, respectively; First and second current sources connected to the drains of the first and second transistors respectively and operative to provide a bias current to the first and second transistors, respectively; And And a load impedance connected to the drains of the first and second transistors. A general purpose broadband amplifier integrated circuit comprising at least two amplifier stages connected in a cascade manner, each amplifier stage comprising: First and second transistors connected in a common source configuration and operative to receive a differential input signal to the amplifier stage and provide a differential output signal to the amplifier stage; First and second current sources connected to the first and second transistors, respectively, and operative to provide a bias current to the first and second transistors, respectively; And And first and second load impedances connected to each of the first and second transistors and further connected to a common node for the amplifier stage. 15. The general purpose broadband amplifier integrated circuit of claim 14, wherein common nodes for the at least two amplifier stages are connected together. 15. The apparatus of claim 14, wherein the first of the at least two amplifier stages is: A first resistor connected between the drain and the gate of the first transistor and operative to provide biasing to the first transistor; And And a second resistor connected between the drain and the gate of the second transistor and operative to provide biasing to the second transistor. 15. The apparatus of claim 14, wherein each amplifier stage comprises third and fourth transistors connected in parallel with the first and second transistors, respectively, The first and third transistors are operable to receive non-inverting and inverting input signals of the differential input signal to the amplifier stage, respectively, and the second and fourth transistors are operable to receive inverting and non-inverting input signals, respectively. General purpose broadband amplifier integrated circuit, characterized in that. 15. The universal broadband of claim 14, wherein the first and second current sources for each amplifier stage are operable to provide varying amounts of bias current to the first and second transistors, respectively. Amplifier integrated circuit. 15. The variable amount of bias current of claim 14, wherein the first and second current sources for the at least two amplifier stages achieve a gain range of at least 60 decibels (dB) for the at least two amplifier stages. And a general purpose wideband amplifier integrated circuit operable to provide. 15. The general purpose broadband amplifier integrated circuit of claim 14, wherein the first and second current sources for the at least two amplifier stages are implemented with a cascade current mirror. The method of claim 20, wherein the cascade current mirror, A first pair of transistors connected in series; A reference current source connected in series with the first pair of transistors; And A pair of transistors for each of the first and second current sources for the at least two amplifier stages, wherein the pair of transistors are connected in series, and a gate for each transistor of the pair of transistors is And a gate of the first pair of corresponding transistors. 15. The general purpose broadband amplifier integrated circuit of claim 14, wherein the first and second transistors for the at least two amplifier stages are field effect transistors (FETs). 15. The general purpose broadband amplifier integrated circuit of claim 14, wherein the differential input signal to the first amplifier stage is AC connected to the first and second transistors of the first amplifier stage. 15. The general purpose broadband amplifier integrated circuit of claim 14, wherein the differential output signal for each amplifier stage except for the last amplifier stage is a DC connected to the first and second transistors of the next amplifier stage. A general purpose broadband amplifier device comprising at least two amplifier stages connected in a cascade fashion, wherein each amplifier stage comprises: First and second transistors connected in a common source configuration and receiving a differential input signal to the amplifier stage and providing a differential output signal to the amplifier stage; First and second current sources connected to the first and second transistors, respectively, and operative to provide a bias current to the first and second transistors, respectively; And And first and second load impedances connected to each of the first and second transistors and further connected to a common node for the amplifier stage. 26. The apparatus of claim 25, wherein each amplifier stage comprises third and fourth transistors connected in parallel with the first and second transistors, respectively, The first and third transistors operate to receive non-inverting and inverting input signals, respectively, of the differential input signal to the amplifier stage, and the second and fourth transistors operate to receive inverting and non-inverting input signals, respectively. A universal broadband amplifier device, characterized in that. 27. The universal wideband amplifier device of claim 25, wherein common nodes for the at least two amplifier stages are connected together.

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