KR100876885B1 - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package and a method of manufacturing the same are disclosed. The semiconductor package may include a semiconductor chip having a bonding pad exposed therein, a redistribution pattern electrically connected to the bonding pad and extending toward an edge of the semiconductor chip, and covering the semiconductor chip and covering a side surface of the redistribution pattern, The upper surface includes an insulating film pattern that is exposed. A method of manufacturing a semiconductor package may include providing a semiconductor chip having a bonding pad exposed thereon, forming an insulating layer pattern on the semiconductor chip having a line-shaped opening exposing the bonding pad and extending toward an edge of the semiconductor chip; A redistribution pattern electrically connected to the bonding pad in the opening.

Description

Semiconductor package and manufacturing method therefor {SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF}

1 is a plan view of a semiconductor package according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3 is a cross-sectional view taken along the line II-II 'of FIG. 1.

4 is a cross-sectional view illustrating a part of a semiconductor package according to a second exemplary embodiment of the present invention.

5 is a cross-sectional view illustrating a part of a semiconductor package according to a third exemplary embodiment of the present invention.

6 is a cross-sectional view illustrating a part of a semiconductor package according to a fourth exemplary embodiment of the present invention.

7 to 12 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a fifth embodiment of the present invention.

13 to 17 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a sixth embodiment of the present invention.

18 and 19 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a seventh embodiment of the present invention.

20 and 21 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an eighth embodiment of the present invention.

The present invention relates to a semiconductor package and a method of manufacturing the same.

Recently, semiconductor devices have been developed to store massive data and to process data stored in a short time.

In general, a semiconductor package is a semiconductor chip manufacturing process of forming a semiconductor chip by integrating devices such as transistors, resistors, capacitors, and the like on a semiconductor chip such as a wafer, and electrically connecting and brittleness to an external circuit board and the like by individualizing the semiconductor chip from the wafer. It is manufactured by a package process that protects weak semiconductor chips from externally applied shocks and / or vibrations.

BACKGROUND Semiconductor packages containing semiconductor devices are applied to personal computers, television receivers, home appliances, information and communication devices, and the like.

Recently, with the miniaturization of electronic products, semiconductor packages require high integration and various functions.

Recently, according to such a demand, a stack package in which a plurality of semiconductor chips performing various functions has been developed has been developed. In order to implement a semiconductor package in which a plurality of semiconductor chips are stacked, a rewiring technology for changing wirings of each semiconductor chip is required.

Conventional redistribution technology forms an insulating film exposing the bonding pads of each semiconductor chip on the surface of each semiconductor chip, and forms a wire electrically connected to the bonding pads on the insulating film.

However, when forming an insulating film on the surface of the semiconductor chip after the insulating film as in the prior art, there is a problem that the volume of the semiconductor package is greatly increased by the rearranged wiring.

In addition, when a plurality of semiconductor chips are stacked in a state in which wiring is formed on the insulating film, and voids are formed at the boundary between the wiring and the insulating film due to the step between the wiring and the insulating film when the semiconductor chips are filled with the insulating material. There are also frequent problems.

One object of the present invention is to provide a semiconductor package which greatly reduces the thickness and / or volume, and prevents the generation of voids at the boundary between the wiring and the insulating film.

Another object of the present invention is to provide a method of manufacturing a semiconductor package which greatly reduces thickness and / or volume and prevents voids from occurring at boundary portions of wirings and insulating films.

A semiconductor package for realizing an object of the present invention includes a semiconductor chip exposed to a bonding pad, a redistribution pattern electrically connected to the bonding pad and extending toward an edge of the semiconductor chip, and covering the semiconductor chip. The side surface of the line pattern may include an insulating layer pattern covering the top surface of the redistribution pattern.

The seed metal pattern may be disposed between the redistribution pattern and the insulating layer pattern of the semiconductor package.

The insulating layer pattern of the semiconductor package may further include at least one auxiliary pattern overlapping the redistribution pattern.

A seed metal pattern disposed on an inner surface of the insulating layer pattern and a sidewall of the auxiliary pattern, wherein the redistribution pattern is disposed on the seed metal pattern and includes a first metal redistribution pattern; A second redistribution pattern covering the redistribution pattern and including a second metal and a third redistribution pattern disposed on the second redistribution pattern and including a third metal may be included.

The first metal comprises copper, the second metal comprises nickel, and the third metal comprises gold.

The first redistribution pattern of the semiconductor package is disposed on the same plane as the top surface of the insulating layer pattern.

The semiconductor package includes a seed metal pattern covering an inner side surface of the insulating layer pattern, a portion of an upper surface of the insulating layer pattern, and an upper surface and sidewalls of the auxiliary pattern, the semiconductor package being disposed on the seed metal pattern and protruding from an upper surface of the insulating layer pattern. A first redistribution pattern including a first metal and a second redistribution pattern disposed on the first redistribution and including a second metal. The first metal may be copper, and the second metal may be gold.

The semiconductor package includes a seed metal pattern covering an inner side surface of the insulating layer pattern, a portion of an upper surface of the insulating layer pattern, and an upper surface and sidewalls of the auxiliary pattern, the semiconductor package being disposed on the seed metal pattern and protruding from an upper surface of the insulating layer pattern. Contains a redistribution pattern. The seed metal pattern may include copper, and the redistribution pattern may include gold.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package, the method including: providing a semiconductor chip having a bonding pad exposed thereon; Forming a pattern on the semiconductor chip and a redistribution pattern electrically connected to the bonding pad in the opening.

The forming of the insulating layer pattern may include forming an insulating layer on the semiconductor chip, and forming a photoresist pattern having a line-shaped opening extending toward an edge of the semiconductor chip, exposing the bonding pad on the insulating layer. And patterning the insulating layer pattern using the photoresist pattern as an etching mask.

The forming of the insulating layer pattern may include forming an insulating layer on the semiconductor chip, a line-shaped opening exposing the bonding pad on the insulating layer and extending toward an edge of the semiconductor chip, and an auxiliary photoresist formed in the opening. Forming a photoresist pattern having a pattern and patterning the insulating layer pattern using the photoresist pattern as an etch mask.

The forming of the redistribution pattern may include forming a seed metal film disposed along the insulating film pattern, forming a metal film filling the opening using the seed metal film and covering the top surface of the insulating film pattern, and the insulating film pattern being Removing the metal film until it is exposed, wherein the metal film is formed by a plating method. The metal film may be any one of copper and gold.

The metal layer may be removed until the insulating layer pattern is exposed by any one of an etch back etching process and a chemical mechanical polishing process.

After polishing the metal layer, the method may include selectively forming a plating layer on the redistribution pattern exposed from the insulating layer pattern.

The forming of the plating layer may include forming a nickel plating layer on the metal film and forming a gold plating layer on the nickel plating layer.

The forming of the redistribution pattern may include forming a seed metal film disposed along the insulating film pattern, forming a metal film filling the opening using the seed metal film and covering an upper surface of the insulating film pattern, and part of the metal film. Forming a preliminary first redistribution pattern to form a preliminary first redistribution pattern, forming a photoresist pattern on the preliminary first redistribution pattern to expose an opening of the insulating layer pattern, and using the photoresist pattern as a plating mask Forming a second redistribution pattern on the first preliminary redistribution pattern corresponding to the opening, removing the photoresist pattern from the first preliminary redistribution pattern, and etching the second redistribution pattern The first prerewiring pattern is removed by removing the first preliminary rewiring pattern disposed on the insulating layer pattern using And a step of sex.

The thickness of the second redistribution pattern is formed to be thicker than the thickness of the preliminary redistribution pattern.

The forming of the redistribution pattern may include forming a seed metal film disposed along the insulating film pattern, forming a metal film filling the opening using the seed metal film and covering an upper surface of the insulating film pattern, and part of the metal film. Forming a preliminary redistribution pattern by forming a preliminary redistribution pattern, forming a photoresist pattern in a portion corresponding to the opening, and patterning the preliminary redistribution pattern using the photoresist pattern as an etching mask to form a redistribution pattern It includes a step.

Hereinafter, a semiconductor package and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and the general knowledge in the art. Those skilled in the art can implement the present invention in various other forms without departing from the technical spirit of the present invention.

Semiconductor package

Example  One

1 is a plan view of a semiconductor package according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1. 3 is a cross-sectional view taken along the line II-II 'of FIG. 1.

1 to 3, the semiconductor package 100 includes a semiconductor chip 10, a redistribution pattern 20, and an insulating film pattern 30.

In the present embodiment, the semiconductor chip 10 may be a semiconductor chip or a wafer on which semiconductor chips are formed.

The semiconductor chip 10 may include a data storage unit (not shown) that stores data, a data processor (not shown) that processes data, and bonding pads 12 that input / output data.

In this embodiment, the bonding pads 12 are disposed along the first direction FD shown in FIG. 1, for example, in the center of the semiconductor chip 10. The bonding pad 12 is formed on the surface of the semiconductor chip 10 and is electrically connected to the data storage unit and / or the data processing unit.

The semiconductor chip 10 having the bonding pads 12 may include a passivation layer 14 exposing the bonding pads 12, as shown in FIG. 2.

Referring to FIG. 3, an insulating film pattern 30 having an opening 32 is disposed on the protective film 14. The bonding pads of the semiconductor chip 10 are exposed by the openings 32. The opening 32 exposing the bonding pads extends from the center of the semiconductor chip 10 toward the edge portion of the semiconductor chip 10.

A seed metal pattern 29 having a thin thickness is disposed on the inner surface of the insulating film pattern 30 formed by the opening 32 and the protective film 14 exposed by the opening 32. The seed metal pattern 29 may include copper. In FIG. 3, the seed metal pattern 29 is not disposed on the top surface of the insulating film pattern 30, but selectively disposed on the passivation film 14 exposed by the inner surface and the opening 32 of the insulating film pattern 30. do.

The redistribution pattern 20 is disposed on the seed metal pattern 29. In the present embodiment, the redistribution pattern 20 may include, for example, copper, and the upper surface of the redistribution pattern 20 is disposed on the same plane as the upper surface of the insulating film pattern 30.

According to this embodiment, the insulating film pattern 30 is disposed on the protective film 14 together with the redistribution pattern 20. Since the insulating film pattern 30 and the redistribution pattern 20 are disposed together on the passivation layer 14, the step difference between the redistribution pattern 20 and the insulating film pattern 30 is greatly reduced, thereby increasing the volume of the semiconductor package. Of course, it is possible to prevent the generation of voids around the redistribution pattern 20 due to the step difference between the redistribution pattern 20 and the insulating film pattern 30.

Example  2

4 is a cross-sectional view illustrating a part of a semiconductor package according to a second exemplary embodiment of the present invention. The semiconductor package according to the present exemplary embodiment is substantially the same as the semiconductor package illustrated in FIGS. 1 to 3 except for the redistribution pattern and the insulating layer pattern. Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given.

Referring to FIG. 4, an insulating film pattern 30 having an opening 32 is disposed on the protective film 14 of the semiconductor chip 10. A portion of the opening 32 exposes the bonding pads of the semiconductor chip 10. The opening 32 exposing the bonding pads extends from the center of the semiconductor chip 10 toward the edge portion of the semiconductor chip 10.

The auxiliary pattern 31 is disposed on the passivation layer 14 exposed by the opening 32. The auxiliary pattern 31 is formed along the opening 32, and at least one is arranged in parallel with each other. A plurality of irregularities are formed in the opening 32 by the auxiliary pattern 31.

On the other hand, the inner surface of the insulating film pattern 30 formed by the opening 32, the side surface of the auxiliary pattern 31 and the protective film 14 exposed by the opening 32 and the auxiliary pattern 31 each have a thin thickness. The seed metal pattern 29 is disposed. The seed metal pattern 29 may include copper. In FIG. 3, the seed metal pattern 29 is not disposed on the top surface of the insulating layer pattern 30 and the top surface of the protective pattern 31.

The redistribution pattern 20 is formed on the seed metal pattern 29. In the present exemplary embodiment, the redistribution pattern 20 includes a first redistribution pattern 21, a second redistribution pattern 22, and a third redistribution pattern 23.

The first redistribution pattern 21 may include, for example, a first metal. In the present embodiment, the first metal may be copper, for example. The upper surface of the first redistribution pattern 21 is disposed on the same plane as the upper surface of the insulating film pattern 30.

The second redistribution pattern 22 is disposed on the first redistribution pattern 21. The second redistribution pattern 22 may include, for example, a second metal. In the present embodiment, the second metal may be nickel, for example.

The third redistribution pattern 23 is disposed on the second redistribution pattern 22. The third redistribution pattern 23 may include, for example, a third metal. In this embodiment, the third wiring can be gold, for example.

According to the present exemplary embodiment, the insulating layer pattern 30 is disposed on the passivation layer 14 together with the redistribution pattern 20 having the first to third rewiring patterns 21, 22, and 23. Since the insulating film pattern 30 and the redistribution pattern 20 are formed together on the passivation layer 14, the step difference between the redistribution pattern 20 and the insulating film pattern 30 is greatly reduced, thereby increasing the volume of the semiconductor package. Of course, it is possible to prevent the generation of voids around the redistribution pattern 20 due to the step difference between the redistribution pattern 20 and the insulating film pattern 30.

Example  3

5 is a cross-sectional view illustrating a part of a semiconductor package according to a third exemplary embodiment of the present invention. The semiconductor package according to the present exemplary embodiment is substantially the same as the semiconductor package illustrated in FIGS. 1 to 3 except for the redistribution pattern, the insulating layer pattern, and the seed metal pattern. Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given.

Referring to FIG. 5, an insulating film pattern 30 having an opening 32 is disposed on the passivation layer 14 disposed on the semiconductor chip 10. A portion of the opening 32 exposes the bonding pads of the semiconductor chip 10. The opening 32 exposing the bonding pads extends from the center of the semiconductor chip 10 toward the edge portion of the semiconductor chip 10.

The auxiliary pattern 31 is disposed on the passivation layer 14 exposed by the opening 32. The auxiliary pattern 31 is formed along the opening 32 and at least one is arranged in parallel with each other. A plurality of irregularities are formed in the opening 32 by the auxiliary pattern 31.

On the other hand, the inner surface of the insulating film pattern 30 formed by the opening 32, a part of the upper surface of the insulating film pattern 30, the upper and side surfaces of the auxiliary pattern 31, and the exposure 32 and the auxiliary pattern 31 are exposed. The seed metal patterns 33 each having a thin thickness are disposed on the passivation layer 14. The seed metal pattern 33 may include copper.

The redistribution pattern 20 is formed on the seed metal pattern 33. In the present embodiment, the redistribution pattern 20 includes a first redistribution pattern 24 and a second redistribution pattern 25.

The first redistribution pattern 24 may include, for example, a first metal. In the present embodiment, the first metal may be copper, for example. The upper surface of the first redistribution pattern 24 protrudes from the upper surface of the insulating film pattern 30 to a predetermined height.

The second redistribution pattern 25 is disposed on the first redistribution pattern 24. The second redistribution pattern 25 may include, for example, a second metal. In the present embodiment, the second metal may be gold, for example.

According to the present exemplary embodiment, the insulating film pattern 30 is disposed on the passivation layer 14 together with the redistribution pattern 20 having the first and second redistribution patterns 24 and 25. Since the insulating film pattern 30 and the redistribution pattern 20 are formed together on the passivation layer 14, the step difference between the redistribution pattern 20 and the insulating film pattern 30 is greatly reduced, thereby increasing the volume of the semiconductor package. Of course, it is possible to prevent the generation of voids around the redistribution pattern 20 due to the step difference between the redistribution pattern 20 and the insulating film pattern 30.

Example  4

6 is a cross-sectional view illustrating a part of a semiconductor package according to a fourth exemplary embodiment of the present invention. The semiconductor package according to the present exemplary embodiment is substantially the same as the semiconductor package illustrated in FIGS. 1 to 3 except for the redistribution pattern and the insulating layer pattern. Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given.

Referring to FIG. 6, an insulating film pattern 30 having an opening 32 is disposed on the passivation layer 14 disposed on the semiconductor chip 10. A portion of the opening 32 exposes the bonding pads of the semiconductor chip 10. The opening 32 exposing the bonding pads extends from the center of the semiconductor chip 10 to the edge portion of the semiconductor chip 10.

The auxiliary pattern 31 is disposed on the passivation layer 14 exposed by the opening 32. The auxiliary pattern 31 is formed along the opening 32, and at least one is arranged in parallel with each other. A plurality of irregularities are formed in the opening 32 by the auxiliary pattern 31.

On the other hand, the inner surface of the insulating film pattern 30 formed by the opening 32, a part of the upper surface of the insulating film pattern 30, the upper and side surfaces of the auxiliary pattern 31, and the exposure 32 and the auxiliary pattern 31 are exposed. The seed metal patterns 34 each having a thin thickness are disposed on the passivation layer 14. The seed metal pattern 34 may include copper.

The redistribution pattern 26 is disposed on the seed metal pattern 34. In the present embodiment, the redistribution pattern 26 may include gold. The redistribution pattern 26 protrudes a predetermined thickness from the top surface of the insulating film pattern 30.

According to the present embodiment, the insulating film pattern 30 is disposed on the protective film 14 together with the redistribution pattern 20 having the redistribution patterns 26 made of gold. Since the insulating film pattern 30 and the redistribution pattern 20 are formed together on the passivation layer 14, the step difference between the redistribution pattern 20 and the insulating film pattern 30 is greatly reduced, thereby increasing the volume of the semiconductor package. Of course, it is possible to prevent the generation of voids around the redistribution pattern 20 due to the step difference between the redistribution pattern 20 and the insulating film pattern 30.

Manufacturing method of semiconductor package

Example  5

7 to 12 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a fifth embodiment of the present invention.

7 is a plan view illustrating a semiconductor chip of a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 7, a semiconductor chip 10 is manufactured to manufacture a semiconductor package.

After the semiconductor chip 10 having a data storage unit (not shown) for storing data using a thin film processing process and a data processing unit (not shown) for processing data is manufactured, the data storage unit and / or the data processing unit may be electrically Bonding pads 12 connected to each other are formed.

After the bonding pads 12 are formed, a protective film 14 including a nitride film and / or an oxide film is formed on the surface of the semiconductor chip 10. The bonding pads 12 formed on the semiconductor chip 10 are exposed from the protective film 14. The bonding pads 12 are formed in the center of the semiconductor chip 10 along the first direction FD shown in FIG. 7, for example.

FIG. 8 is a plan view illustrating an insulating film pattern formed on the semiconductor chip of FIG. 7. FIG. 9 is a cross-sectional view taken along the line III-III ′ of FIG. 8. FIG. 10 is a cross-sectional view taken along the line IV-IV ′ of FIG. 8.

8 to 10, an insulating film (not shown) is formed over the entire surface of the semiconductor chip 10 to form the insulating film pattern 30. In the present embodiment, the insulating film may include an inorganic material and / or an organic material, and the insulating film may be formed through, for example, a chemical vapor deposition process.

Referring to FIG. 9, a photoresist film (not shown) including a photosensitive material is formed on the insulating film, for example. The photoresist film may be formed through a spin coating process or the like.

After the photoresist film is formed, the photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern 17 on the insulating film. At this time, the photoresist pattern 17 has substantially the same size and shape as the rearrangement wiring to be formed later.

After the photoresist pattern is formed, the insulating film is patterned using the photoresist pattern as an etching mask to form the insulating film pattern 30 having the opening 32 shown in FIG. 10 on the protective film 14.

A portion of the opening 32 formed in the insulating film pattern 30 exposes the bonding pad 12 of the semiconductor chip 10 as shown in FIG. 8, and the opening 32 exposing the bonding pad 12 is a semiconductor. It extends from the center of the chip 10 toward the edge portion of the semiconductor chip 10.

FIG. 11 is a cross-sectional view illustrating the formation of a seed metal film and a metal film on the insulating film pattern illustrated in FIG. 10.

Referring to FIG. 11, the seed metal film 29a and the metal film 20a are sequentially formed on the insulating film pattern 30 having the opening 32 formed therein.

In this embodiment, examples of materials that can be used as the seed metal film 29a and the metal film 20a include copper, and the seed metal film 29a and the metal film 20a may be formed by a sputtering process or a chemical vapor deposition process. Or the like is formed on the insulating film pattern 30.

FIG. 12 is a cross-sectional view illustrating a rewiring pattern formed by polishing or etching the metal film of FIG. 11.

Referring to FIG. 12, after the seed metal film 29a and the metal film 20a are sequentially formed on the insulating film pattern 30, the metal film 20a and the seed metal film 29a may be chemically mechanically polished or etched. The rearrangement wiring 20 and the seed metal pattern 29 are formed together in the opening 32 of the insulating layer pattern 30 by patterning by a back etching process.

In this embodiment, in order to form the rearrangement wiring 20 and the seed metal pattern 29, the metal film 20a and the seed metal film 29a are subjected to a chemical mechanical polishing process until the insulating film pattern 30 is exposed. It may be polished by, or may be etched by an etching process until the portion of the seed metal film 29a formed on the insulating film pattern 30 is completely removed.

In the present embodiment, since the rearrangement wiring 20 and the seed metal pattern 29 are formed by a chemical mechanical polishing process or an etching process, the top surface of the redistribution pattern 20 is coplanar with the top surface of the insulating film pattern 30. Is disposed on.

According to the present embodiment, since the insulating film pattern 30 is formed on the protective film 14 together with the redistribution pattern 20, the step between the redistribution pattern 20 and the insulating film pattern 30 can be greatly reduced. As a result, the volume of the semiconductor package may be reduced, and the voids may be prevented from being generated around the redistribution pattern 20 due to the step difference between the redistribution pattern 20 and the insulating layer pattern 30.

Example  6

13 to 17 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a sixth embodiment of the present invention. The manufacturing method of the semiconductor package according to the present exemplary embodiment is substantially the same as the manufacturing method of the semiconductor package described above except for the process of forming the redistribution pattern and the insulating film pattern. Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given.

FIG. 13 is a cross-sectional view illustrating an insulating layer pattern, an auxiliary pattern, and a seed metal layer formed on the semiconductor chip illustrated in FIG. 7.

Referring to FIG. 13, an insulating film (not shown) is formed over the entire surface of the protective film 14 formed on the semiconductor chip 10, and a photoresist film (not shown) is formed over the entire surface of the insulating film.

The photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern 37. The photoresist pattern 37 includes a first photoresist pattern 38 for forming the opening 32 and a second photoresist pattern 39 formed in a wall shape in the opening 32.

The insulating layer is patterned using the photoresist pattern 37 including the first and second photoresist patterns 38 and 39 as an etch mask, and the auxiliary pattern 31 is formed on the passivation layer 14 exposed by the opening 32. An insulating film pattern 30 having a structure is formed.

After the insulating film pattern 30 is formed, the photoresist pattern 37 formed on the insulating film pattern 30 is removed from the insulating film pattern 30 by an ashing process and / or a strip process.

14 is a cross-sectional view illustrating a seed metal film disposed on the insulating film pattern formed in FIG. 13.

Referring to FIG. 14, after the photoresist pattern 37 is removed, the seed metal film 32a is formed on the insulating film pattern 30. The seed metal film 32a may include copper, and the seed metal film 32a is formed by a chemical vapor deposition process or a sputtering process.

FIG. 15 is a cross-sectional view illustrating a metal film covering the seed metal film illustrated in FIG. 14.

Referring to FIG. 15, after the seed metal film 32a is formed, the metal film 21a including the first metal is formed on the seed metal film 32a using, for example, a plating process. The first metal of the metal film 21a may include, for example, copper.

FIG. 16 is a cross-sectional view illustrating the formation of a first redistribution pattern by patterning the metal film and the seed metal film shown in FIG. 15.

Referring to FIG. 16, after the metal film 21a is formed, the metal film 21a and the seed metal film 32a are patterned by using a chemical mechanical polishing process or an etch back process. In this embodiment, for example, the metal film 21a and the seed metal film 32a disposed on the insulating film pattern 30 are polished until the insulating film pattern 30 is exposed using a chemical mechanical polishing process. As a result, the seed metal pattern 32 and the first redistribution pattern 21 are formed.

FIG. 17 is a cross-sectional view illustrating the formation of second and third redistribution patterns on the first redistribution pattern illustrated in FIG. 16.

Referring to FIG. 17, after the first redistribution pattern 21 is formed, the second cultivation including the second metal on the first redistribution pattern 21 through a plating process using the first redistribution pattern 21. The line pattern 22 may be formed. In this embodiment, the second metal may include nickel.

After the second redistribution pattern 22 is formed, the third redistribution pattern 23 including the third metal may be formed through a plating process using the second redistribution pattern 22. In the present embodiment, the third metal may include gold.

According to the present exemplary embodiment, the insulating film pattern 30 is formed on the passivation layer 14 together with the redistribution pattern 20 having the first to third redistribution patterns 21, 22, and 23. Since the insulating film pattern 30 and the redistribution pattern 20 are formed together on the passivation layer 14, the step difference between the redistribution pattern 20 and the insulating film pattern 30 is greatly reduced, thereby increasing the volume of the semiconductor package. As a result, the voids may be prevented from being generated around the redistribution pattern 20 due to the step difference between the redistribution pattern 20 and the insulating layer pattern 30.

Example  7

18 and 19 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a seventh embodiment of the present invention.

Referring back to FIGS. 13 and 14, an insulating film (not shown) is formed over the entire surface of the protective film 14 formed on the semiconductor chip 10, and a photoresist film (not shown) is formed over the entire surface of the insulating film. .

The photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern 37. The photoresist pattern 37 includes a first photoresist pattern 38 for forming the opening 32 and a second photoresist pattern 39 formed in a wall shape in the opening 32.

The insulating film is patterned by using the photoresist pattern 37 including the first and second photoresist patterns 38 and 39 as an etch mask and exposed on the protective film 14 exposed by the opening 32 as shown in FIG. 18. As described above, the insulating film pattern 30 having the auxiliary pattern 31 is formed.

After the insulating film pattern 30 is formed, the photoresist pattern 37 formed on the insulating film pattern 30 is removed from the insulating film pattern 30 by an ashing process and / or a strip process.

Referring to FIG. 18 again, after the photoresist pattern is removed, the seed metal film 33a is formed on the insulating film pattern 30. The seed metal film 33a may include copper, and the seed metal film 33a is formed by a chemical vapor deposition process or a sputtering process.

After the seed metal film 33a is formed, a metal film (not shown) containing a first metal is formed on the seed metal film 33a by using a plating process. The first metal of the metal film may include copper, and the metal film is thinly formed on the upper surface of the insulating film pattern 30.

After the metal film is formed, the metal film is polished by, for example, a chemical mechanical polishing process. In this case, in the chemical mechanical polishing process, the metal film is polished so that the seed metal film 33a is not exposed, and the preliminary first redistribution pattern 24a is formed on the insulating film pattern 30. Alternatively, the preliminary first redistribution pattern 24a may be formed by an etch back etching process.

After the preliminary first redistribution pattern 24a is formed, a photoresist film is applied onto the preliminary first redistribution pattern 24, and the photoresist film is patterned by a photo process to form the preliminary first redistribution pattern 24a. Photoresist pattern 36 is formed. The photoresist pattern 36 exposes the preliminary first redistribution pattern 24a corresponding to the portion where the redistribution pattern is to be formed.

Referring to FIG. 18 again, after the preliminary first redistribution pattern 24a and the photoresist pattern 36 are formed, a plating process is performed on the preliminary first redistribution pattern 24a exposed by the photoresist pattern 36. The used second redistribution pattern 25 is formed. In the present embodiment, the second redistribution pattern 25 may include a second metal. The second metal may be gold, for example. In the present embodiment, the thickness of the second redistribution pattern 25 is formed thicker than the thickness of the preliminary first redistribution pattern 24a.

19 is a cross-sectional view illustrating the patterning of the preliminary first rewiring pattern illustrated in FIG. 18.

Referring to FIG. 19, after the second redistribution pattern 25 is formed on the preliminary first redistribution pattern 24a, the photoresist pattern 36 disposed on the preliminary first redistribution pattern 24a is ashed. Removed by a process and / or a strip process.

Subsequently, the preliminary first redistribution pattern 24a and the seed metal layer 33a are etched back using the second redistribution pattern 25 as an etch mask, and the first redistribution pattern 24a and the seed metal layer 33a are etched back under the second redistribution pattern 25. The redistribution pattern 24 and the seed metal pattern 33 are formed.

According to the present exemplary embodiment, the insulating film pattern 30 is disposed on the passivation layer 14 together with the redistribution pattern 20 having the first and second redistribution patterns 24 and 25. Since the insulating film pattern 30 and the redistribution pattern 20 are formed together on the passivation layer 14, the step difference between the redistribution pattern 20 and the insulating film pattern 30 is greatly reduced, thereby increasing the volume of the semiconductor package. As a result, the voids may be prevented from being generated around the redistribution pattern 20 due to the step difference between the redistribution pattern 20 and the insulating layer pattern 30.

Example  8

20 and 21 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an eighth embodiment of the present invention.

Referring back to FIGS. 13 and 14, an insulating film (not shown) is formed over the entire surface of the protective film 14 formed on the semiconductor chip 10, and a photoresist film (not shown) is formed over the entire surface of the insulating film. .

The photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern 37. The photoresist pattern 37 includes a first photoresist pattern 38 for forming the opening 32 and a second photoresist pattern 39 formed in a wall shape in the opening 32.

The insulating film is patterned by using the photoresist pattern 37 including the first and second photoresist patterns 38 and 39 as an etch mask and exposed on the protective film 14 exposed by the opening 32 as shown in FIG. 18. As described above, the insulating film pattern 30 having the auxiliary pattern 31 is formed.

After the insulating film pattern 30 is formed, the photoresist pattern 37 formed on the insulating film pattern 30 is removed from the insulating film pattern 30 by an ashing process and / or a strip process.

Referring to FIG. 20, after the photoresist pattern is removed, the seed metal film 34a is formed on the insulating film pattern 30. The seed metal film 34a may include copper, and the seed metal film 34a is formed by a chemical vapor deposition process or a sputtering process.

After the seed metal film 34a is formed, a metal film (not shown) including the first metal is formed on the seed metal film 34a by using a plating process. The metal film may include gold, and the metal film is thickly formed on the upper surface of the insulating film pattern 30.

After the metal film is formed, the metal film is polished by, for example, a chemical mechanical polishing process. In this case, in the chemical mechanical polishing process, the metal film is polished so that the seed metal film 34a is not exposed, and a preliminary redistribution pattern 26a is formed on the insulating film pattern 30. Alternatively, the preliminary redistribution pattern 26a may be formed by an etch back etching process.

After the preliminary redistribution pattern 26a is formed, a photoresist film is applied on the preliminary redistribution pattern 26a, and the photoresist film is patterned by a photo process to form a photoresist pattern 38 on the preliminary redistribution pattern 26a. Is formed. The photoresist pattern 38 covers the preliminary redistribution pattern 24a corresponding to the portion where the redistribution pattern is to be formed.

FIG. 21 is a cross-sectional view illustrating the patterning of the pre-rewiring pattern illustrated in FIG. 20.

Referring to FIG. 21, after the photoresist pattern 38 covering the preliminary redistribution pattern 26a is formed, the preliminary redistribution pattern 26a and the seed metal layer 34a may use the photoresist pattern 38 as an etch mask. Patterned by using, the seed metal pattern 34 and the redistribution pattern 26 is formed on the insulating film pattern (30).

According to the present embodiment, the insulating film pattern 30 is disposed on the protective film 14 together with the redistribution pattern 20 having the redistribution patterns 26 made of gold. Since the insulating film pattern 30 and the redistribution pattern 20 are formed together on the passivation layer 14, the step difference between the redistribution pattern 20 and the insulating film pattern 30 is greatly reduced, thereby increasing the volume of the semiconductor package. Of course, it is possible to prevent the generation of voids around the redistribution pattern 20 due to the step difference between the redistribution pattern 20 and the insulating film pattern 30.

As described above in detail, the insulating film pattern and the redistribution pattern are disposed on substantially the same plane on the semiconductor chip to reduce the step difference between the insulating film pattern and the redistribution pattern, thereby preventing the thickness increase of the semiconductor package and the insulating film pattern and the redistribution pattern. It has an effect of preventing the generation of voids according to the step between.

Although the detailed description of the present invention has been described with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art will have the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (22)

A semiconductor chip with exposed bonding pads; A redistribution pattern electrically connected to the bonding pads and extending toward an edge of the semiconductor chip; And An insulating film pattern covering the semiconductor chip and covering a side surface of the redistribution pattern and exposing an upper surface of the redistribution pattern, The insulating layer pattern includes at least one auxiliary pattern overlapping the redistribution pattern. The method of claim 1, And a seed metal pattern disposed between the redistribution pattern and the insulating layer pattern. delete The method of claim 1, A seed metal pattern disposed on an inner surface of the insulating layer pattern and a sidewall of the auxiliary pattern; The redistribution pattern is disposed on the seed metal pattern and includes a first redistribution pattern including a first metal, a second redistribution pattern covering the first redistribution pattern, and including a second metal. And a third redistribution pattern disposed on the pattern and comprising a third metal. The semiconductor package of claim 4, wherein the first metal comprises copper, the second metal comprises nickel, and the third metal comprises gold. The semiconductor package of claim 4, wherein the first rewiring pattern is disposed on the same plane as an upper surface of the insulating layer pattern. The method of claim 1, A seed metal pattern covering an inner side surface of the insulating layer pattern and a portion of an upper surface of the insulating layer pattern and an upper surface and sidewalls of the auxiliary pattern; A first redistribution pattern disposed on the seed metal pattern and protruding from an upper surface of the insulating layer pattern, and including a first metal and a second redistribution pattern disposed on the first redistribution and including a second metal; A semiconductor package, characterized in that. The semiconductor package of claim 7, wherein the first metal is copper and the second metal is gold. The method of claim 1, A seed metal pattern covering an inner side surface of the insulating layer pattern and a portion of an upper surface of the insulating layer pattern and an upper surface and sidewalls of the auxiliary pattern; And a redistribution pattern disposed on the seed metal pattern and protruding from an upper surface of the insulating layer pattern. The semiconductor package of claim 9, wherein the seed metal pattern comprises copper and the redistribution pattern comprises gold. delete Preparing a semiconductor chip having exposed bonding pads; Forming an insulating film pattern on the semiconductor chip, wherein the insulating pad has a line-shaped opening extending toward the edge of the semiconductor chip, exposing the bonding pads; And Forming a redistribution pattern electrically connected to the bonding pad in the opening; Forming the insulating film pattern is Forming an insulating film on the semiconductor chip; Forming a photoresist pattern exposing the bonding pads on the insulating layer and having a line-shaped opening extending toward an edge of the semiconductor chip; And And forming an insulating film pattern by patterning the insulating film using the photoresist pattern as an etching mask. Preparing a semiconductor chip having exposed bonding pads; Forming an insulating film pattern on the semiconductor chip, wherein the insulating pad has a line-shaped opening extending toward the edge of the semiconductor chip, exposing the bonding pads; And Forming a redistribution pattern electrically connected to the bonding pad in the opening; Forming the insulating film pattern is Forming an insulating film on the semiconductor chip; Forming a photoresist pattern on the insulating layer, the photoresist pattern having a line-shaped opening extending toward an edge of the semiconductor chip and an auxiliary photoresist pattern formed in the opening; And And patterning the insulating layer using the photoresist pattern as an etching mask. The method of claim 13, wherein the forming of the redistribution pattern is performed. Forming a seed metal film disposed along the insulating film pattern; Forming a metal film filling the opening by using the seed metal film and covering an upper surface of the insulating film pattern; And And removing the metal film to form a redistribution pattern until the insulating layer pattern is exposed. 15. The method of claim 14, wherein the metal film is formed by a plating method. 15. The method of claim 14, wherein the metal film is any one of copper and gold. The method of claim 14, wherein the metal film is removed until the insulating film pattern is exposed by any one of an etch back etching process and a chemical mechanical polishing process. The method of claim 14, After the polishing of the metal film, selectively forming a plating layer on the redistribution pattern exposed from the insulating film pattern. The method of claim 18, wherein the forming of the plating layer Forming a nickel plating layer on the metal film; And A method of manufacturing a semiconductor package comprising the step of forming a gold plating layer on the nickel plating layer. The method of claim 13, wherein the forming of the redistribution pattern is performed. Forming a seed metal film disposed along the insulating film pattern; Forming a metal film filling the opening by using the seed metal film and covering an upper surface of the insulating film pattern; Removing a portion of the metal film to form a preliminary first redistribution pattern; Forming a photoresist pattern on the preliminary first redistribution pattern to expose the opening of the insulating layer pattern; Forming a second redistribution pattern on the first preliminary redistribution pattern corresponding to the opening by using the photoresist pattern as a plating mask; Removing the photoresist pattern from the first preliminary redistribution pattern; And And removing the first preliminary redistribution pattern disposed on the insulating layer pattern using the second redistribution pattern as an etching mask to form a first redistribution pattern. . The method of claim 20, wherein the thickness of the second redistribution pattern is thicker than the thickness of the preliminary redistribution pattern. The method of claim 13, wherein the forming of the redistribution pattern is performed. Forming a seed metal film disposed along the insulating film pattern; Forming a metal film filling the opening by using the seed metal film and covering an upper surface of the insulating film pattern; Removing a portion of the metal film to form a pre-rewiring pattern; Forming a photoresist pattern in a portion corresponding to the opening; And And forming a redistribution pattern by patterning the preliminary redistribution pattern using the photoresist pattern as an etching mask.

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