KR100876768B1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
KR100876768B1
KR100876768B1 KR1020070098470A KR20070098470A KR100876768B1 KR 100876768 B1 KR100876768 B1 KR 100876768B1 KR 1020070098470 A KR1020070098470 A KR 1020070098470A KR 20070098470 A KR20070098470 A KR 20070098470A KR 100876768 B1 KR100876768 B1 KR 100876768B1
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South Korea
Prior art keywords
region
etch stop
stop layer
storage electrode
cell region
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KR1020070098470A
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Korean (ko)
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김지형
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

A semiconductor device and method for manufacturing the same is provided to reduce parasitic capacitance between a bit line and a storage electrode by forming the thickness of the etch prevention film formed on the top of the storage node contact of the dummy region thicker than that of the cell region. In a semiconductor device and method for manufacturing the same, an Interlayer insulating film(220) including a bit line and a storage node contact are formed on a semiconductor substrate including the cell region and dummy region. When the etch prevention film is formed on the top of interlayer insulating film, the height of the etch prevention film(230) formed in the dummy region is higher than that of the etch prevention film(230a) formed in the cell region. The etch prevention film is composed of selected one of a nitride film and an amorphous carbon layer. The height of the etch prevention film of the dummy region has 2~80 times that of the etch prevention film of the cell region.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to the prior art.

2A to 2C are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

200: semiconductor substrate 205: bit line

210: storage electrode contact 220: interlayer insulating film

230: etching prevention film 240: first photosensitive film pattern

250: sacrificial insulating film 260: storage electrode region

265: conductive film

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method of forming a storage electrode in a dummy storage electrode region.

As the degree of integration of semiconductor devices increases, the reduction of design rules has been rapidly made. Accordingly, the implementation of ultrafine patterns is required.

In particular, in order to further secure a process margin in a memory device such as a DRAM device, a process of disposing a dummy pattern around actual patterns is recognized as a major factor in the design process.

For example, in the case of a DRAM device, a dummy bit line and a dummy storage electrode are inserted and disposed to secure process margins in a photo and etching process.

1 is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to the prior art, and FIG. 1 (iii) is a cross-sectional view showing a cell region, and FIG. 1 (ii) is a cross-sectional view showing a dummy region. to be.

Referring to FIG. 1, an interlayer insulating layer 120 including a bit line 105 and a storage electrode contact plug 110 is formed on the semiconductor substrate 100.

Next, an etch stop layer 130 is formed on the interlayer insulating layer 120.

Here, the etch stop layer 130 is formed of a nitride film, it is preferable to form a thickness of 100 to 500Å.

In this case, an etch stop layer 130 having the same thickness is formed in the cell region and the dummy region.

Next, a sacrificial insulating layer 140 for a storage electrode is formed on the etch stop layer 130, and a photoresist pattern (not shown) defining a storage electrode region is formed on the sacrificial insulating layer 140.

Next, the sacrificial insulating layer 140 is etched using the photoresist pattern (not shown) as a mask to form the storage electrode region 150 through which the storage electrode contact 110 is exposed.

Next, the conductive film 160 is formed on the entire surface including the storage electrode region 150.

Here, the conductive film 160 is preferably formed of a TiN film.

Next, an etch-back process is performed to separate the conductive layer 160 and the adjacent conductive layer 160 to form a storage electrode.

Here, the critical dimension (CD) of the storage electrode region 150 of the dummy region is larger than that of the storage electrode region 150 CD of the cell region.

At this time, during the etching process for forming the storage electrode region 150 of the dummy region, the region that does not overlap with the storage electrode contact 110 below is deeply etched, such as 'A', and thus the dummy region. In FIG. 3, the distance from the bit line 105 formed at the lower portion is closer than that of the cell region.

In order to prevent this, a method of finding a condition in which the storage electrode region of the cell region and the storage electrode region of the dummy region are etched to the same depth has been proposed, but it is difficult to find such an etching condition.

In the above-described conventional semiconductor device and a method of manufacturing the same, the storage electrode on the dummy region is closer to the bit line than the storage electrode of the cell region. At this time, even if a direct short does not occur between the storage electrode and the bit line, the distance is shortened, so that parasitic capacitance is generated and acts as a noise to read the cell data, thereby degrading device characteristics.

In order to solve the above problem, by forming an etch stop layer formed on the storage electrode contact in the dummy region thicker than the cell region, the distance between the storage electrode formed in the dummy region and the bit line is farther away, thereby causing parasitic capacitance. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which reduce the parasitic capacitance to prevent noise from affecting sensing of cell data and improve device characteristics.

Method for manufacturing a semiconductor device according to the present invention

Forming an interlayer insulating film including a bit line and a storage electrode contact on a semiconductor substrate including a cell region and a dummy region;

Forming an etch stop layer on the interlayer insulating layer, wherein the height of the etch stop layer formed in the dummy area is higher than that of the cell area;

The anti-etching film is formed of any one selected from a nitride film, an amorphous carbon layer, and a combination thereof,

The etch stop layer of the dummy region is formed to have a thickness of 2 to 80 times the etch stop layer of the cell region,

The anti-etching film thickness of the cell region is 100 to 500Å,

The anti-etching film thickness of the dummy region is 1000 to 8000 kPa,

The forming of the etch stop layer may include forming a mask pattern on the etch stop layer to open the cell region;

And selectively etching the cell region using the mask pattern.

Forming a planarized sacrificial insulating layer on the etch stop layer of the cell region and the dummy region;

And etching the sacrificial insulating layer to form a storage electrode region, wherein the cell region exposes the storage electrode contact and the dummy region exposes the etch stop layer.

In addition, the semiconductor device according to the present invention

A semiconductor substrate comprising a cell region and a dummy region,

An interlayer insulating layer formed on the semiconductor substrate and including a bit line and a storage electrode contact;

And an etch stop layer provided on the interlayer insulating layer, wherein the etch stop layer of the dummy region is thicker than the etch stop layer of the cell region.

The anti-etching layer thickness of the dummy region is 2 to 80 times the thickness of the anti-etching layer of the cell region,

A sacrificial insulating layer pattern defining a storage electrode region is formed on the etch stop layer of the cell region and the dummy region, wherein the sacrificial insulating layer pattern of the cell region exposes the storage electrode contact. It is characterized by exposing the etch stop layer.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2C show a semiconductor device and a method of manufacturing the same according to the present invention, (i) of FIG. 2A to 2C is a cross-sectional view showing a cell region, and (ii) of FIG. 2A to 2C is a dummy. It is sectional drawing which shows an area.

Referring to FIG. 2A, an interlayer insulating layer 220 including a bit line 205 and a storage electrode contact 210 is formed on a semiconductor substrate 200 having a cell region and a dummy region. .

The bit line 200 may be formed, for example, in a stacked structure of a barrier metal layer (not shown), a bit line tungsten layer (not shown), and a bit line hard mask layer (not shown).

Next, a buffer oxide film (not shown) and an etch stop layer 230 are formed on the interlayer insulating layer 220.

Here, the etch stop film 230 is preferably formed of any one selected from the nitride film, the amorphous carbon layer, and a combination thereof, the thickness of the etch stop film 230 is preferably 1000 to 8000 kPa thicker than the conventional.

Referring to FIG. 2B, a first photoresist layer pattern 240 is formed on the etch stop layer 230 to open the cell region.

Next, the etch stop layer 230 in the cell region is etched using the first photoresist pattern 240 as a mask so that the etch stop layer 230a for the storage electrode having a thickness of 100 to 500 m is left.

Thus, the cell region is formed with an etch barrier layer 230a having the same thickness as the conventional electrode, and the etch barrier layer 230 with a thicker thickness is formed with the dummy region.

Next, the first photoresist pattern 240 is removed.

Referring to FIG. 2C, the sacrificial insulating layer 250 for the storage electrode is formed on the entire upper portion where the etch stop layers 230 and 230a are formed.

Here, since the cell region has a low thickness of the storage electrode etch stop layer 230a, the sacrificial insulating layer 250 is thick, and the dummy area has a thick etch stop layer 230. It can be seen that the thickness of the) is formed thinner than the cell area.

Next, a second photoresist pattern (not shown) defining a storage electrode region is formed on the sacrificial insulating layer 250.

In this case, the CD (Critical Dimension) of the storage electrode region defined in the cell region is smaller than the CD (Critical Dimension) of the storage electrode region defined in the dummy region.

Next, the sacrificial insulating layer 250 and the buffer oxide layer (not shown) are etched using the second photoresist pattern (not shown) as a mask to form the storage electrode region 260.

Next, the etch stop layers 230 and 230a are further etched.

In this case, the storage electrode region 260 of the cell region is formed to expose the storage electrode contact 210, and only a portion of the storage electrode region 260 of the dummy region is etched and the etching is stopped.

Next, the second photosensitive film pattern (not shown) is removed.

Next, a conductive film 265 is formed on the entire surface including the storage electrode region 260 of the cell region and the dummy region.

The storage electrode is formed by performing an etch-back process to remove the conductive layer 265 on the sacrificial insulating layer 250.

Here, the conductive film 265 is preferably formed of any one selected from titanium (Ti), titanium nitride film (TiN), and a combination thereof.

Next, a process of forming a dielectric film and a plate electrode on the storage electrode surface is performed.

Referring to the semiconductor device illustrated in FIG. 2C, a semiconductor substrate 200 including a cell region and a dummy region and a bit line 205 and a storage electrode contact 210 are disposed on the semiconductor substrate 200. An interlayer insulating film 220 is provided.

An etch stop layer is disposed on the interlayer insulating layer 220, and the etch stop layer 230 in the dummy region is thicker than the etch stop layer 230a for the storage electrode in the cell region.

In this case, the thickness of the anti-etching layer 230 of the dummy region is preferably 2 to 80 times the thickness of the anti-etching layer 230a for the storage electrode of the cell region.

By forming an etch barrier layer thicker than the cell region on the dummy region as described above, the depth to be etched in the dummy region during the etching of the storage electrode region is reduced, so that the distance from the bit line 205 formed in the lower portion is farther away. Parasitic capacitances on the bit lines are reduced.

The semiconductor device and the method of manufacturing the same according to the present invention form an etch stop layer formed on the storage electrode contact in the dummy region thicker than the cell region, thereby increasing the distance between the storage electrode formed in the dummy region and the bit line. As a result, parasitic capacitance is reduced, thereby preventing the parasitic capacitance from acting as a noise on sensing of cell data, thereby improving the characteristics of the device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (10)

Forming an interlayer insulating film including a bit line and a storage electrode contact on a semiconductor substrate including a cell region and a dummy region; And Forming an etch stop layer on the interlayer insulating layer, and forming a height of the etch stop layer formed in the dummy area higher than the cell area; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The etch stop layer is formed of any one selected from the nitride film, the amorphous carbon layer and a combination thereof. The method of claim 1, And the etch stop layer of the dummy region is formed to have a thickness of 2 to 80 times the etch stop layer of the cell region. The method of claim 1, The anti-etching film thickness of the cell region is a method of manufacturing a semiconductor device, characterized in that 100 to 500Å. The method of claim 1, The anti-etching film thickness of the dummy region is a method of manufacturing a semiconductor device, characterized in that 1000 to 8000 kPa. The method of claim 1, Forming the etch stop layer is Forming a mask pattern on the etch stop layer to open the cell region; And Selectively etching the cell region using the mask pattern Method of manufacturing a semiconductor device comprising a. The method of claim 1, Forming a planarized sacrificial insulating layer on the etch stop layer of the cell region and the dummy region; And And etching the sacrificial insulating layer to form a storage electrode region, wherein the cell region exposes the storage electrode contact, and the dummy region exposes the etch stop layer. A semiconductor substrate including a cell region and a dummy region; An interlayer insulating layer formed on the semiconductor substrate and including a bit line and a storage electrode contact; And And an etch stop layer provided on the interlayer insulating layer, wherein the etch stop layer of the dummy region is thicker than the etch stop layer of the cell region. The method of claim 8, The anti-etching film thickness of the dummy region is a semiconductor device, characterized in that 2 to 80 times the thickness of the anti-etching film of the cell region. The method of claim 8, A sacrificial insulating layer pattern defining a storage electrode region is formed on the etch stop layer of the cell region and the dummy region, wherein the sacrificial insulating layer pattern of the cell region exposes the storage electrode contact. A semiconductor device, characterized in that to expose the etching prevention film.
KR1020070098470A 2007-09-28 2007-09-28 Semiconductor device and method for manufacturing the same KR100876768B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115223943A (en) * 2021-04-15 2022-10-21 长鑫存储技术有限公司 Memory manufacturing method and memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036495A (en) 1998-07-21 2000-02-02 Nec Corp Manufacture of semiconductor device
KR20030059405A (en) * 2001-12-29 2003-07-10 주식회사 하이닉스반도체 Method of forming dual gate oxide
US20050136632A1 (en) 2003-12-17 2005-06-23 Rotondaro Antonio L. Implementation of split gate transistor technology with high-k gate dielectrics
KR20070088928A (en) * 2006-02-27 2007-08-30 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036495A (en) 1998-07-21 2000-02-02 Nec Corp Manufacture of semiconductor device
KR20030059405A (en) * 2001-12-29 2003-07-10 주식회사 하이닉스반도체 Method of forming dual gate oxide
US20050136632A1 (en) 2003-12-17 2005-06-23 Rotondaro Antonio L. Implementation of split gate transistor technology with high-k gate dielectrics
KR20070088928A (en) * 2006-02-27 2007-08-30 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115223943A (en) * 2021-04-15 2022-10-21 长鑫存储技术有限公司 Memory manufacturing method and memory

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