KR100876549B1 - Esd protection circuitry - Google Patents

Abstract

The ESD protecting circuit is provided to reduce the area which the ESD protecting circuit occupies in the semiconductor chip between power supplies. The ESD(Electro-Static Discharge) protection circuit(500) comprises the NPN bipolar transistor(Q1), the first resistance(R1), and the first diode(D3). The NPN bipolar transistor has the emitter terminal connected to the first node(N1) in which the first supply voltage(VCC1) is applied. The NPN bipolar transistor has the collector terminal connected to the second Node(N2) in which the second supply voltage(VCC2) is applied. The first resistance has one terminal connected to the base terminal of the NPN bipolar transistor. The first resistance has the other one terminal connected to the emitter terminal. One terminal of the first diode is connected to the second node. The first diode has the other one terminal connected to the ground voltage.

Description

ESD Protection Circuits {ESD PROTECTION CIRCUITRY}

The present invention relates to an electro-static discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit between power supply voltages suitable for integrating a plurality of power supply voltages.

When static electricity due to a human body or a machine enters an integrated semiconductor chip, very fine internal circuits in the semiconductor chip may be destroyed or malfunction. Therefore, a general semiconductor chip is provided with an ESD protection circuit capable of discharging static electricity.

1 shows a conventional ESD protection circuit.

Referring to FIG. 1, the conventional ESD protection circuit 100 includes an ESD protection circuit 110 between an input / output terminal I / O, an ESD protection circuit 120 between power supply voltages VCC1 and VCC2, and ESD protection circuit 130 between the ground voltage (GND).

The ESD protection circuit 110 at the input / output terminal basically consists of two diodes D1 and D2. That is, in the first diode D1, a cathode terminal is connected to the first power supply voltage VCC1, and an anode terminal is connected to the input / output terminal I / O. In the second diode D2, a cathode terminal is connected to an input / output terminal I / O, and an anode terminal is connected to a ground voltage GND. The ESD protection circuit 110 at the input / output terminal composed of two diodes D1 and D2 is already well known in Korean Patent Laid-Open Publication No. 1998-66467 (published on October 15, 1998). Under normal operating conditions, the discharge paths of the ESD pulses are not formed with the respective diodes D1 and D2. However, when an ESD pulse having a voltage level higher than the turn-on voltage of the first diode D1 (hereinafter referred to as a positive ESD pulse) is applied to the input / output terminal I / O, the input / output terminal I / O is applied. At 0), a discharge path of the ESD pulse, through which the positive ESD pulse may exit, is formed toward the first power supply voltage VCC1. On the contrary, when an ESD pulse having a lower voltage level than the turn-on voltage of the second diode D2 (hereinafter referred to as a negative ESD pulse) is applied to the input / output terminal I / O, the input / output terminal I / O is applied. The discharge path of the ESD pulse is formed to allow the negative ESD pulse to escape from O) to the ground voltage (GND).

The ESD protection circuit 120 between the supply voltages is required to create a discharge path of positive or negative ESD pulses between the multiple power supplies when configuring multiple power supplies in the semiconductor chip. The ESD protection circuit 120 between the power supply voltages is mainly formed by connecting diodes in series between the power supply voltages VCC1 and VCC2.

The ESD protection circuit 130 between the ground voltages is formed by connecting diodes in series between the ground voltages GND1 and GND2 similarly to the ESD protection circuit 120 between the power supply voltages VCC1 and VCC2. However, since the ground voltages GND1 and GND2 are generally connected to a substrate having a very low impedance, the ESD protection circuit 130 between the ground voltages tends to be omitted.

2 shows an ESD protection circuit applied between power supplies having the same voltage level in the related art, and FIG. 3 shows an ESD protection circuit applied between power supplies having different voltage levels.

2 and 3, an ESD protection circuit between power supply voltages having the same voltage level is composed of bidirectional shunts of diodes connected in series between power supply voltages VCC1 and VCC2. On the other hand, ESD protection circuits between power supply voltages having different voltage levels are composed of diodes connected in series in one direction rather than in both directions. This is because the discharge path of the positive ESD pulse is formed from a high voltage level to a low voltage level. That is, as a whole, the cathode terminal is connected to the power supply voltage VCC2 having a relatively high voltage level, and the anode terminal is connected to the power supply voltage VCC1 having a relatively low voltage level.

3, when the voltage levels of the power supply voltages VCC1 and VCC2 are different from each other, an ESD protection circuit requires as many diodes as the potential difference between the power supply voltages VCC1 and VCC2. For example, assuming that the potential difference between the power supply voltages VCC1 and VCC2 is 7 V and the forward voltage of the diode is 0.7 V, the ESD protection circuit between the power supply voltages may be configured as the power supply voltages VCC1 and VCC2. At least 10 diodes are needed to make the potential difference.

Therefore, the number of diodes required when the potential difference between power supply voltages is large becomes very large. This may cause the area of the semiconductor chip to increase, which may be a difficult condition for the integration of the semiconductor chip.

The technical problem to be solved by the present invention is to use an NPN bipolar transistor instead of a series connection of diodes, to provide an ESD protection circuit that can achieve an excellent ESD protection while reducing the area between the supply voltage.

One embodiment of the ESD protection circuit according to the present invention for achieving the above technical problem is that the emitter terminal is connected to the first node to which the first power supply voltage is applied, the collector terminal to the second node to which the second power supply voltage is applied. NPN bipolar transistors connected; A first resistor having one terminal connected to the base terminal of the NPN bipolar transistor and the other terminal connected to the emitter terminal; And a first diode having one end connected to the second node and the other end connected to the ground voltage.

Another embodiment of the ESD protection circuit according to the present invention for achieving the above technical problem is that the emitter terminal is connected to the fourth node to which the third power supply voltage is applied, the collector terminal is connected to the fifth node connected to the internal circuit NPN bipolar transistor; A second resistor having one terminal connected to the base terminal of the NPN bipolar transistor and the other terminal connected to the emitter terminal; A fourth diode having one end connected to the fifth node and the other end connected to a ground voltage; And a fifth diode having one end connected to the first power supply voltage and the other end connected to the fourth node.

The ESD protection circuit according to the present invention can be composed of only NPN bipolar transistors and resistors between power supply voltages having a large potential difference, and thus excellent ESD protection while greatly reducing the area occupied by the ESD protection circuit between power supply voltages in semiconductor chips. The effect can be obtained.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 illustrates an embodiment of an electro-static discharge (ESD) protection circuit according to the present invention.

The ESD protection circuit 400 shown in FIG. 4 includes an ESD protection circuit 410 at an input / output terminal and an ESD protection circuit 420 between a power supply voltage. Here, the ESD protection circuit 410 at the input / output terminal consisting of two diodes D1 and D2 may be configured similarly to the ESD protection circuit 410 at the conventional input / output terminal. Therefore, the following description will focus on the ESD protection circuit 420 between power supply voltages.

FIG. 5 illustrates one embodiment of an ESD protection circuit 420 between the power supply voltages shown in FIG. 4.

Referring to FIG. 5, an ESD protection circuit 500 between power supply voltages includes an NPN bipolar transistor Q1, a first resistor R1, and a first diode D3 connected between power supply voltages VCC1 and VCC2. It is made. Here, the first power supply voltage VCC1 is a power supply voltage used for the internal circuit 1 (430 of FIG. 4), and the second power supply voltage is a power supply voltage used for the internal circuit 2 (440 of FIG. 4).

The NPN bipolar transistor Q1 has an emitter terminal connected to a first node N1 to which a first power supply voltage VCC1 is applied, and a collector node to a second node N2 to which a second power supply voltage VCC2 is applied. Is connected to. One end of the first resistor R1 is connected to the base terminal B of the NPN bipolar transistor Q1, and the other end is connected to the emitter terminal. One end of the first diode D3 is connected to the second node N2, and the other end of the first diode D3 is connected to the ground voltage GND. In FIG. 5, the first diode D3 has a cathode terminal of the second node N2. It is shown that the anode terminal is connected to the ground voltage GND. Here, the second power supply voltage VCC2 has the same or higher voltage level than the first power supply voltage VCC1, and the ground voltage GND is lower than the first power supply voltage VCC1 and the second power supply voltage VCC2. Has a level.

The NPN bipolar transistor Q1 operates only when an ESD pulse having a voltage level higher than the turn-on voltage of the transistor (hereinafter, referred to as a positive ESD pulse) is applied to the second power supply voltage VCC2. That is, when the potential difference between the second power supply voltage VCC2 and the first power supply voltage VCC1 does not exceed the turn-on voltage of the NPN bipolar transistor Q1, the NPN bipolar transistor Q1 is turned off. Keep it.

However, when a positive ESD pulse occurs in the second power supply voltage VCC2, the generated positive ESD pulse is transferred from the collector to the base by parasitic capacitance between the collector and the base of the NPN bipolar transistor Q1. The transferred positive ESD pulse is output to the first power supply voltage VCC1 through the first resistor R1 connected to the base terminal. This is done by the discharge path (Discharge Path) of the ① ESD pulse shown in FIG.

After the NPN bipolar transistor Q1 is turned on, an ESD pulse discharge path is formed between the collector and the emitter, and the first power voltage VCC1 from the second power supply voltage VCC2 through the NPN bipolar transistor Q1. The positive ESD pulse is pulled out. This is done by the discharge path of ESD pulse # 2 shown in FIG.

When an ESD pulse having a low voltage level (hereinafter, referred to as a negative ESD pulse) at which the first diode D3 is turned on in the second power supply voltage VCC2 is generated, the generated negative ESD pulse is a first diode (see FIG. Through D3), it is pulled out to the ground voltage GND. Similarly, one end (cathode terminal) is connected to the first node N1 to form a discharge path of the ESD pulse between the first power supply voltage VCC1 and the ground voltage GND. The terminal (anode terminal) may further include a second diode D4 connected to the ground voltage GND.

FIG. 6 illustrates another embodiment of an ESD protection circuit 420 between the power supply voltages shown in FIG. 4.

Referring to FIG. 6, the ESD protection circuit 600 between the power supply voltages shown in FIG. 6 has the same basic structure as the ESD protection circuit 500 between the power supply voltages shown in FIG. 5. However, in the ESD protection circuit 600 illustrated in FIG. 6, one end is connected to the base terminal of the NPN bipolar transistor Q1 and the common terminal of the first resistor R1, and the other end is connected to the second node N2. It further illustrates that the first capacitor (C1) to be provided. Here, the first capacitor C1 is connected in parallel with a parasitic capacitor (not shown) existing between the collector and the base of the NPN bipolar transistor Q1.

Trigger time until the positive ESD pulse is generated at the second power supply voltage VCC2 and the discharge path of the ESD pulse # 2 shown in FIG. 5 is formed, that is, the discharge path of the ESD pulse # 1 is maintained. Time), in the ESD protection circuit 500 illustrated in FIG. 5, the trigger time of the positive ESD pulse is determined by the capacitance of the collector-base parasitic capacitor of the NPN bipolar transistor and the first resistor R1. At this time, the trigger time is mainly determined by the size of the first resistor (R1).

On the other hand, in the ESD protection circuit 600 illustrated in FIG. 6, the first capacitor C1 is provided in addition to the parasitic capacitor and the first resistor R1 formed between the collector and the base of the NPN bipolar transistor Q1. The trigger time is determined not only by the resistor R1 but also by the capacitance of the first capacitor C1. Thus, the ESD protection circuit 600 shown in FIG. 6 is easier to adjust the trigger time than the ESD protection circuit 500 shown in FIG. In addition, since the positive ESD pulse generated at the second power supply voltage VCC2 may be distributed to the first capacitor C1, the voltage level applied to the collector of the NPN bipolar transistor Q1 may be lowered by that amount.

In addition, the ESD protection circuit 600 between the power supply voltages shown in FIG. 6 illustrates bulk biasing (A) of the first resistor R1. In this case, when the second power supply voltage VCC2 having a relatively high voltage level is applied to the bulk of the first resistor R1, the first resistor R1 is set in a state where the bulk of the lower portion of the first resistor R1 is stabilized. Discharge of the positive ESD pulse to the first power supply voltage (VCC1) through.

FIG. 7 illustrates an example of the bulk biasing (“A”) of the first resistor illustrated in FIG. 6.

Referring to FIG. 7, an N-type impurity semiconductor region is formed on the P-type substrate 710, and the first resistor 730 is formed of a P-type impurity semiconductor on the N-type impurity semiconductor region 720. In this case, the N-type impurity semiconductor region 720 becomes a bulk of the first resistor 730.

In this case, the N-type impurity semiconductor region 720, which is the bulk of the first resistor 730, has a second power supply voltage having a relatively high voltage level for stable bulk biasing of the first resistor 730 to which the positive ESD pulse is applied. It is preferable that the VCC2 is connected to the second node N2 to which the VCC2 is applied. If the first power supply voltage VCC1 is applied to the bulk N-type impurity semiconductor region 720, a PN diode and an NPN bipolar transistor formed of a P-type resistor 730 and an N-type impurity semiconductor region 720 may be used. May form a current mirror. The current flow in the NPN bipolar transistor Q1 may be limited by the formed current mirror. This means that the magnitude of the positive ESD pulse exiting from the second power supply voltage VCC2 to the first power supply voltage VCC1 may be limited. Thus, in this case, the positive ESD pulses that can be protected are limited, so that the desired performance may not be performed properly in the ESD protection circuit.

8 illustrates another embodiment of an ESD protection circuit in accordance with the present invention.

The ESD protection circuit 800 shown in FIG. 8 is not only an ESD protection circuit 810 at the input / output terminal, but also a third power supply voltage VEE and an internal circuit 830 having a voltage level lower than the ground voltage GND. By providing an ESD protection circuit 820 between), it can be usefully applied to the discharge of the negative ESD pulse generated from the third power supply voltage (VEE).

FIG. 9 illustrates an embodiment of an ESD protection circuit 820 between the third power supply voltage VEE and the internal circuit 830.

8 and 9, the first power supply voltage VCC1 has a voltage level higher than the ground voltage GND, and the third power supply voltage VEE has a voltage level lower than the ground voltage GND. In this case, the first power supply voltage VCC1 has the highest voltage level among the voltages used by the internal circuit 830, and the third power supply voltage VEE has the lowest voltage level among the voltages used by the internal circuit 830. Voltage.

In FIG. 9, the third resistor R3 is connected to a sixth node N6 having one end connected to one end (cathode terminal) of the fourth diode D6 and the other end applied with the third power supply voltage VEE. Is connected to the fourth node N4. The third resistor R3 is used to integrate a circuit using a power supply voltage having a voltage level lower than the ground voltage GND or a voltage level lower than the ground voltage GND on one substrate. In the steady state, the third resistor R3 properly biases the positive voltage of the internal circuit 830 and the third power supply voltage VEE. That is, in the internal circuit 830 where the voltage level is relatively high, a current path is formed through the third resistor R3 to the third power supply voltage VEE having a relatively low voltage level. This corresponds to ③ path of FIG. 9. Accordingly, the power supply voltage having a lower voltage level than the ground voltage GND may be integrated through the third resistor R3 biasing the internal circuit 830 and the third power supply voltage VEE.

If the discharge path of the ESD pulse by the NPN bipolar transistor Q1 does not exist, if a negative ESD pulse occurs in the third power supply voltage VEE, the discharge path of the ESD pulse is formed only through the third resistor R3. do. In this case, the third resistor R3 consumes power by the product of the voltage and the current. At this time, since the power consumption is converted into heat, a lot of heat is generated in the third resistor R3, and the third resistor R3 may be destroyed.

The ESD protection circuit 900 illustrated in FIG. 9 includes an NPN bipolar transistor Q1, a second resistor R2, a fourth diode D6, and a fifth diode D7.

The NPN bipolar transistor Q1 has a fifth terminal in which the emitter terminal E is connected to the fourth node N4 to which the third power supply voltage VEE is applied, and the collector terminal C is connected to the internal circuit 830. It is connected to node N5. One end of the second resistor R2 is connected to the base terminal B of the NPN bipolar transistor Q1, and the other end is connected to the emitter terminal E. The fourth diode D6 has one terminal (cathode terminal) connected to the fifth node N5 and the other terminal (anode terminal) connected to the ground voltage GND. The fifth diode D7 has one terminal (cathode terminal) connected to the first power supply voltage VCC1 and the other terminal (anode terminal) connected to the fourth node N4.

When a negative ESD pulse occurs in the third power supply voltage VEE, the collector is caused by a parasitic capacitance between the collector terminal and the base terminal of the NPN bipolar transistor Q1 due to the voltage difference between the emitter and the collector of the NPN bipolar transistor Q1. The discharge path of the negative ESD pulse is formed from the terminal to the base terminal. The negative ESD pulse is discharged through the second resistor R2 connected to the base terminal by the discharge path thus formed. This is achieved by the discharge path of the ESD pulse # 1 shown in FIG. After the NPN bipolar transistor Q1 is turned on, a discharge path of an ESD pulse is formed between the collector and the emitter, and is negative to the ground voltage GND through the NPN bipolar transistor Q1 and the fourth diode D6. The ESD pulse will come off. This is done by the discharge path of ESD pulse # 2 shown in FIG.

As a result, when a negative ESD pulse occurs in the third power supply voltage VEE, the negative ESD pulse follows the discharge path of the ① ESD pulse until the NPN bipolar transistor Q1 is turned on, and then the NPN bipolar transistor is After the turn-on, it is discharged to the ground voltage GND along the discharge path of the ESD pulse # 2, so that the third resistor R3 for adjusting the bias between the third power supply voltage VEE and the internal circuit 830 is negative. It can protect against ESD pulses.

When the positive ESD pulse occurs in the third power supply voltage VEE, the fifth diode D7 is turned on so that the positive ESD pulse exits to the first power supply voltage VCC1.

FIG. 10 illustrates another embodiment of the ESD protection circuit 820 between the third power supply voltage VEE and the internal circuit 830.

In the ESD protection circuit 1000 shown in FIG. 10, one end of the ESD protection circuit 1000 is connected to the base terminal of the NPN bipolar transistor Q1 and the common terminal of the second resistor R2, and the other terminal is connected to the fifth node N5. It illustrates that the two capacitors (C2) may be further provided. Since the description of adding the second capacitor C2 to the ESD protection circuit 1000 is the same as in the ESD protection circuit 600 shown in FIG. 6, the detailed description thereof will be omitted.

The technical spirit of the present invention has been described above with reference to the accompanying drawings. However, the present invention has been described by way of example only, and is not intended to limit the present invention. In addition, it is apparent that any person having ordinary knowledge in the technical field to which the present invention belongs may make various modifications and imitations without departing from the scope of the technical idea of the present invention.

1 shows a conventional ESD protection circuit.

2 shows an ESD protection circuit applied between power supplies having the same voltage level in the related art.

3 illustrates an ESD protection circuit applied between power supplies having different voltage levels in the related art.

Figure 4 illustrates one embodiment of an ESD protection circuit in accordance with the present invention.

FIG. 5 illustrates one embodiment of an ESD protection circuit between the power supply voltages shown in FIG. 4.

FIG. 6 illustrates another embodiment of an ESD protection circuit between the power supply voltages shown in FIG. 4.

FIG. 7 illustrates an example of bulk biasing of the first resistor illustrated in FIG. 6.

8 illustrates another embodiment of an ESD protection circuit in accordance with the present invention.

9 illustrates one embodiment of an ESD protection circuit between a third power supply voltage and an internal circuit.

FIG. 10 shows another embodiment of an ESD protection circuit between a third power supply voltage and an internal circuit.

Claims (12)

An NPN bipolar transistor having an emitter terminal connected to a first node to which a first power supply voltage is applied, and a collector terminal connected to a second node to which a second power supply voltage is applied; A first resistor having one terminal connected to the base terminal of the NPN bipolar transistor and the other terminal connected to the emitter terminal; And Electro-Static Discharge (ESD) protection circuit, characterized in that the first node is connected to the second node, the other end has a first diode connected to the ground voltage. The method of claim 1, And a second diode having one end connected to the first node and the other end connected to the ground voltage. The method of claim 1, And a first capacitor having one terminal connected to the base terminal of the NPN bipolar transistor and the common terminal of the first resistor, and the other terminal connected to the second node. The method of claim 1, wherein the first resistor, An ESD protection circuit comprising a resistor formed of a P-type impurity semiconductor on an N-type impurity semiconductor region. The n-type impurity semiconductor region according to claim 4, ESD protection circuit, characterized in that the second power supply voltage is applied. The method according to any one of claims 1 to 5, wherein the second power supply voltage, ESD protection circuit having a voltage level equal to or higher than the first power supply voltage. An NPN bipolar transistor having an emitter terminal connected to a fourth node to which a third power supply voltage is applied, and a collector terminal connected to a fifth node connected to an internal circuit; A second resistor having one terminal connected to the base terminal of the NPN bipolar transistor and the other terminal connected to the emitter terminal; A fourth diode having one end connected to the fifth node and the other end connected to a ground voltage; And And a fifth diode having one end connected to a first power supply voltage and the other end connected to the fourth node. The method of claim 7, wherein And a third resistor having one end connected to a sixth node connected to the fourth diode and the other end connected to the fourth node. The method of claim 7, wherein And a second capacitor having one terminal connected to the base terminal of the NPN bipolar transistor and the common terminal of the second resistor, and the other terminal connected to the fifth node. The method of claim 7, wherein the second resistor, An ESD protection circuit comprising a resistor formed of a P-type impurity semiconductor on an N-type impurity semiconductor region. The method according to any one of claims 7 to 10, wherein the ground voltage, And a voltage level lower than the first power supply voltage, and a voltage level higher than the third power supply voltage. The method of claim 11, The first power supply voltage has the highest voltage level among the voltages used by the internal circuit, The third power supply voltage has the lowest voltage level of the voltage used by the internal circuit.

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