KR100875684B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR100875684B1
KR100875684B1 KR1020020073400A KR20020073400A KR100875684B1 KR 100875684 B1 KR100875684 B1 KR 100875684B1 KR 1020020073400 A KR1020020073400 A KR 1020020073400A KR 20020073400 A KR20020073400 A KR 20020073400A KR 100875684 B1 KR100875684 B1 KR 100875684B1
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nitride film
profile
active region
film
etching
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KR20040045580A (en
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공필구
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

본 발명은 소자분리 영역의 형성시 질화막의 프로파일을 변형하여 충분한 액티브 영역을 확보함으로써 후속 산화공정에 의한 액티브 영역의 손실로 인해 발생되는 문제를 해결할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method for manufacturing a semiconductor device that can solve the problem caused by the loss of the active region by the subsequent oxidation process by securing a sufficient active region by modifying the profile of the nitride film when forming the device isolation region.

본 발명은 반도체 기판 상에 패드 산화막 및 질화막을 순차적으로 형성하는 단계; 질화막을 경사 프로파일을 갖도록 패터닝하는 단계; 및 과도식각으로 패드 산화막 및 기판의 일부를 식각하여 경사 프로파일을 갖는 액티브 영역을 정의하는 단계를 포함하는 반도체 소자의 제조방법에 의해 달성될 수 있다. 바람직하게, 질화막은 400 내지 1200Å의 두께로 형성하고, 질화막의 패터닝은 경사식각으로 수행한다.
The present invention includes sequentially forming a pad oxide film and a nitride film on a semiconductor substrate; Patterning the nitride film to have an oblique profile; And etching a portion of the pad oxide film and the substrate by transient etching to define an active region having an inclined profile. Preferably, the nitride film is formed to a thickness of 400 to 1200 kPa, and the patterning of the nitride film is performed by oblique etching.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE} Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}             

도 1은 종래의 반도체 소자의 소자분리 영역 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a method of forming a device isolation region of a conventional semiconductor device.

도 2는 본 발명의 실시예에 따른 반도체 소자의 소자분리 영역 형성방법을 설명하기 위한 단면도.2 is a cross-sectional view illustrating a method of forming a device isolation region of a semiconductor device in accordance with an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

20 : 반도체 기판 21 : 패드 산화막20 semiconductor substrate 21 pad oxide film

22 : 질화막 23 : ARC막22 nitride film 23 ARC film

24 : 포토레지스트 패턴 24: photoresist pattern

A1, A2 : 액티브 영역
A1, A2: active area

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 STI(Sallow Trench Isolation) 구조를 적용한 소자분리 영역 형성시 액티브 영역을 충분히 확보할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of sufficiently securing an active region when forming an isolation region using a STI (Sallow Trench Isolation) structure.

일반적으로, 반도체 소자는 트랜지스터나 캐패시터 등과 같은 소자들이 형성되는 액티브 영역과, 소자의 동작이 서로 방해되지 않도록 액티브 영역들을 분리하는 소자분리 영역으로 구성되어 있다.In general, a semiconductor device is composed of an active region where elements such as a transistor or a capacitor are formed, and an isolation region that separates the active regions so that operation of the device does not interfere with each other.

일반적으로 소자분리 영역은 실리콘 반도체기판을 국부적으로 열산화시키는 로코스(Local Oxidation of Silicon; LOCOS) 공정을 주로 이용하여 형성하였다. 그러나, LOCOS 공정에 의한 소자분리 영역은 비교적 면적이 크고 경계면에 발생되는 버즈빅(bird's beak) 등의 문제로 인하여 고집적 소자에 적용하는데 한계가 있었다. 따라서, 최근 0.16㎛ 이하의 고집적 메모리 소자에서는 기판에 얕은 깊이의 트렌치를 형성하고, 이 트렌치에 산화막을 매립시켜 소자분리 영역을 형성하는 STI (Sallow Trench Isolation) 구조를 적용하고 있다.In general, the device isolation region is mainly formed by using a Local Oxidation of Silicon (LOCOS) process for locally thermally oxidizing a silicon semiconductor substrate. However, the device isolation region by the LOCOS process has a relatively large area and has a limitation in application to highly integrated devices due to problems such as bird's beak generated at the interface. Therefore, recently, in the highly integrated memory device of 0.16 mu m or less, a shallow trench isolation (STI) structure is formed in which a trench having a shallow depth is formed in a substrate, and an oxide film is buried in the trench to form an isolation region.

도 1은 이러한 STI 구조를 적용한 반도체 소자의 소자분리 영역 형성방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a method of forming an isolation region of a semiconductor device to which the STI structure is applied.

도 1을 참조하면, 반도체 기판(10) 상에 패드 산화막(11) 및 질화막(12)을 순차적으로 형성하고, 질화막(12) 상에 저부 ARC(Anti Reflective Coating)막(13)을 형성한다. 여기서, 패드 산화막(11)은 질화막(12)에 대한 스트레스를 완화시키는 완충막으로서 작용한다. 그 다음, 포토리소그라피 공정으로 ARC막(13) 상에 포토레지스트 패턴(14)을 형성한다. 그 후, 포토레지스트 패턴(14)을 마스크로하여 ARC막(13) 및 질화막(12)을 식각하고, 과도식각(over etch)으로 패드 산화막(11) 및 기판(11)의 일부를 식각하여 액티브 영역(A1)을 정의한다. 그리고 나서, 도시 되지는 않았지만, 포토레지스트 패턴(14) 제거공정, 트렌치 형성공정, 산화공정, 산화막 매립공정, 및 평탄화공정 등의 후속공정을 수행하여 STI 구조의 소자분리 영역을 형성한다. Referring to FIG. 1, a pad oxide film 11 and a nitride film 12 are sequentially formed on a semiconductor substrate 10, and a bottom anti-reflective coating (ARC) film 13 is formed on the nitride film 12. Here, the pad oxide film 11 acts as a buffer film to alleviate the stress on the nitride film 12. Next, the photoresist pattern 14 is formed on the ARC film 13 by a photolithography process. Thereafter, the ARC film 13 and the nitride film 12 are etched using the photoresist pattern 14 as a mask, and the pad oxide film 11 and a part of the substrate 11 are etched by over etching. The area A1 is defined. Subsequently, although not shown, subsequent steps such as a photoresist pattern 14 removing step, a trench forming step, an oxidation step, an oxide buried step, and a planarization step are performed to form the device isolation region of the STI structure.

상술한 종래의 STI 구조의 소자분리 영역 형성시, 질화막(12)의 식각은 일반적으로 식각개스를 수직으로 주입하는 수직식각(vertical etch)으로 수행하기 때문에 질화막(12)이 수직 프로파일을 갖게 된다. 그러나, 과도식각에 의해 기판(10)의 식각시 기판(10)의 프로파일은 질화막(12)의 프로파일을 따르기 때문에 기판(10)도 질화막(12)과 마찬가지로 수직 프로파일을 갖게 된다(도 1의 도면부호 100 참조). 이에 따라, 액티브 영역(A1)의 표면이 수직 프로파일을 갖게 됨으로써, 후속 산화공정시 액티브 영역의 손실이 발생되어 소자의 특성 및 수율이 저하될 뿐만 아니라 리프레시 특성이 열화되는 등의 문제가 발생하게 된다.
In forming the isolation region of the conventional STI structure, the etching of the nitride film 12 is generally performed by a vertical etch that vertically injects an etching gas so that the nitride film 12 has a vertical profile. However, since the profile of the substrate 10 follows the profile of the nitride film 12 when the substrate 10 is etched by the transient etching, the substrate 10 also has a vertical profile like the nitride film 12 (Fig. 1). Sign 100). As a result, the surface of the active region A1 has a vertical profile, which causes loss of the active region during the subsequent oxidation process, thereby deteriorating the characteristics and yield of the device and deteriorating the refresh characteristics. .

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 소자분리 영역의 형성시 질화막의 프로파일을 변형하여 충분한 액티브 영역을 확보함으로써 후속 산화공정에 의한 액티브 영역의 손실로 인해 발생되는 문제를 해결할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.
The present invention has been proposed in order to solve the above problems of the prior art, a problem caused by the loss of the active region by the subsequent oxidation process by ensuring a sufficient active region by modifying the profile of the nitride film when forming the device isolation region Its purpose is to provide a method of manufacturing a semiconductor device that can solve the problem.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 반도체 기판 상에 패드 산화막 및 질화막을 순차적으로 형성하는 단계; 질화막을 경사 프로파일을 갖도록 패터닝하는 단계; 및 과도식각으로 패드 산화막 및 기판의 일부를 식각하여 경사 프로파일을 갖는 액티브 영역을 정의하는 단계를 포함하는 반도체 소자의 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the object of the present invention comprises the steps of sequentially forming a pad oxide film and a nitride film on a semiconductor substrate; Patterning the nitride film to have an oblique profile; And etching a portion of the pad oxide film and the substrate by transient etching to define an active region having an inclined profile.

바람직하게, 질화막은 400 내지 1200Å의 두께로 형성하고, 질화막의 패터닝은 경사식각으로 수행한다.Preferably, the nitride film is formed to a thickness of 400 to 1200 kPa, and the patterning of the nitride film is performed by oblique etching.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 2는 본 발명의 실시예에 따른 반도체 소자의 소자분리 영역 형성방법을 설명하기 위한 단면도로서, 도 2를 참조하여 그 형성방법을 설명한다.2 is a cross-sectional view illustrating a method of forming a device isolation region of a semiconductor device in accordance with an embodiment of the present invention, with reference to FIG. 2.

도 2를 참조하면, 반도체 기판(20) 상에 패드 산화막(21) 및 질화막(22)을 순차적으로 형성하고, 질화막(22) 상에 저부 ARC막(23)을 형성한다. 여기서, 패드 산화막(21)은 질화막(22)에 대한 스트레스를 완화시키는 완충막으로서 작용하고, 바람직하게 질화막(22)은 400 내지 1200Å의 두께로 형성한다. 그 다음, ARC막(23) 상에 포토리소그라피 공정으로 포토레지스트 패턴(14)을 형성한다. Referring to FIG. 2, the pad oxide film 21 and the nitride film 22 are sequentially formed on the semiconductor substrate 20, and the bottom ARC film 23 is formed on the nitride film 22. Here, the pad oxide film 21 acts as a buffer film to alleviate the stress on the nitride film 22, and preferably the nitride film 22 is formed to a thickness of 400 to 1200 kPa. Next, the photoresist pattern 14 is formed on the ARC film 23 by a photolithography process.

그 후, 포토레지스트 패턴(24)을 마스크로하여 ARC막(23) 및 질화막(22)을 식각하는데, 먼저 질화막(22)을 식각 종말점(End Of Point; EOP)으로 하여 ARC막 (23)을 식각한 다음, 식각개스를 소정의 경사각으로 주입하는 경사식각(slope etch)으로 질화막(22)을 식각하여 경사 프로파일을 갖도록 질화막(22)을 패터닝하 고, 과도식각으로 패드 산화막(21) 및 기판(21)의 일부를 식각하여 액티브 영역(A2)을 정의한다. 이때, 기판(21)의 프로파일이 질화막(22)의 프로파일을 따르기 때문에, 기판(21)도 질화막(22)과 마찬가지로 경사 프로파일을 갖게 되어 액티브 영역(A2)의 표면이 경사 프로파일을 갖게 되므로(도 2의 도면부호 200 참조), 종래(도 1의 A1) 보다 소정 부분 넓게 액티브 영역(A2)이 정의된다.Thereafter, the ARC film 23 and the nitride film 22 are etched using the photoresist pattern 24 as a mask. First, the ARC film 23 is formed by using the nitride film 22 as an end end point (EOP). After etching, the nitride film 22 is etched by using a slope etch to inject an etching gas at a predetermined inclination angle to pattern the nitride film 22 to have an inclined profile, and the pad oxide film 21 and the substrate are overetched. A part of (21) is etched to define the active area A2. At this time, since the profile of the substrate 21 follows the profile of the nitride film 22, the substrate 21 also has an inclined profile similar to the nitride film 22, so that the surface of the active region A2 has an inclined profile (Fig. 2, the active region A2 is defined to be a predetermined portion wider than the conventional one (A1 in FIG. 1).

그리고 나서, 도시되지는 않았지만, 포토레지스트 패턴(24) 제거공정, 트렌치 형성공정, 산화공정, 산화막 매립공정, 및 평탄화공정 등의 후속공정을 수행하여 STI 구조의 소자분리 영역을 형성한다.Subsequently, although not shown, subsequent steps such as a photoresist pattern 24 removing process, a trench forming process, an oxidation process, an oxide filling process, and a planarization process are performed to form the device isolation region of the STI structure.

상기 실시예에 의하면, 액티브 영역의 표면 프로파일을 좌우하는 질화막을 종래의 수직식각 대신 경사식각으로 식각하여 수직 프로파일을 갖도록 패터닝하여 액티브 영역의 표면 프로파일도 경사 프로파일을 갖게 함으로써 종래보다 넓은 액티브 영역을 확보할 수 있게 된다. 이에 따라, 후속 산화공정시 액티브 영역의 손실에 따른 소자의 특성 및 수율 저하를 방지할 수 있을 뿐만 아니라 우수한 리프레시 특성을 얻을 수 있게 된다.According to the above embodiment, the nitride film which determines the surface profile of the active region is etched by an inclined etch instead of the conventional vertical etch so as to have a vertical profile so that the surface profile of the active region also has an inclined profile to secure a wider active region than before. You can do it. Accordingly, it is possible to prevent the deterioration of the device characteristics and the yield due to the loss of the active region during the subsequent oxidation process, as well as to obtain excellent refresh characteristics.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 소자분리 영역의 형성시 질화막의 프로파일을 변형하여 충분한 액티브 영역을 확보함으로써 후속 산화공정에 의해 액티브 영역의 손실에 따른 소자의 특성 및 수율 저하를 방지할 수 있을 뿐만 아니라 우수한 리프레시 특성을 얻을 수 있게 된다.According to the present invention, the profile of the nitride film is modified to form a sufficient active region when forming the device isolation region, thereby preventing the deterioration of device characteristics and yield due to the loss of the active region by a subsequent oxidation process, as well as excellent refresh characteristics. You will get

Claims (3)

반도체 기판 상에 패드 산화막 및 질화막을 순차적으로 형성하는 단계;Sequentially forming a pad oxide film and a nitride film on the semiconductor substrate; 상기 질화막에 대해 경사식각을 실시하여 상기 질화막이 상부에서 하부로 갈수록 폭이 증가되는 경사 프로파일을 갖도록 패터닝하는 단계; 및 Performing an inclined etching on the nitride film to pattern the nitride film to have an inclined profile that increases in width from top to bottom; And 과도식각으로 상기 패드 산화막 및 기판의 일부를 식각하여 경사 프로파일을 갖는 액티브 영역을 정의하는 단계Etching the pad oxide layer and a portion of the substrate by transient etching to define an active region having an inclined profile 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 질화막은 400 내지 1200Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The nitride film is a semiconductor device manufacturing method, characterized in that formed to a thickness of 400 to 1200 내지. 삭제delete
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980040647A (en) * 1996-11-29 1998-08-17 김광호 Device Separation Method of Semiconductor Device
KR19990055775A (en) * 1997-12-27 1999-07-15 김영환 Device isolation method of semiconductor device using trench

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980040647A (en) * 1996-11-29 1998-08-17 김광호 Device Separation Method of Semiconductor Device
KR19990055775A (en) * 1997-12-27 1999-07-15 김영환 Device isolation method of semiconductor device using trench

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