KR100866710B1 - Method for forming a word line of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a word line of a semiconductor device. In particular, after forming a first gate electrode of type I on a semiconductor substrate in a channel region, an upper portion of the first gate electrode is formed. By forming a line-type second gate electrode on the substrate to form a word line consisting of the first and second gate electrodes, the word line does not overlap with an end of an active region other than the channel region. To prevent the GIDL (Gate Induced Drain Leakage) generated at the end of the active region to increase the refresh (Refresh) characteristics, and to form a word line because it is formed by dividing the word line into first and second gate electrodes In the etching process, since the etching target (Target) is lower than the conventional technology to improve the characteristics, yield and reliability of the device by the easy etching process.

Description

Method for forming a word line of semiconductor device

1 is a layout diagram showing a conventional word line.

FIG. 2 is a cross-sectional view taken along line II of FIG. 1. FIG.

3A to 3D are layout views illustrating a word line forming method of a semiconductor device in accordance with an embodiment of the present invention.

4A to 4D are cross-sectional views taken along lines I-I and II-II of Figs. 3A to 3D, respectively.

<Description of Symbols for Main Parts of Drawings>

11,31 semiconductor substrate 12,32 active region

13,33: device isolation layer 15,35: gate oxide film

17: gate electrode 19,39: source / drain region

37: first gate electrode 41: interlayer insulating film

43 second polycrystalline silicon layer 43a second gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a word line of a semiconductor device. In particular, after forming a first gate electrode of type I on a semiconductor substrate in a channel region, an upper portion of the first gate electrode is formed. The present invention relates to a method of forming a word line of a semiconductor device, by forming a line-type second gate electrode on the substrate to form a word line including the first and second gate electrodes, thereby improving device characteristics, yield, and reliability.

1 is a layout diagram illustrating a conventional word line, and FIG. 2 is a cross-sectional view taken along line II of FIG. 1.

1 and 2, a conventional transistor is a line type in which a gate oxide film 15 is formed on a p-type semiconductor substrate 11 having an isolation layer 13 defining an active region 12. The gate electrode 17 and the source / drain regions 19 formed in the surface of the semiconductor substrate 11 on both sides of the gate electrode 17 are formed.

Here, the active region 12 defined by the device isolation layer 13 is arranged in an I type while being spaced apart from each other in the horizontal axis direction by a predetermined interval in the semiconductor substrate 11, and is arranged to be shifted from a neighboring column.

The word lines formed of the line type gate electrodes 17 are arranged on the semiconductor substrate 11 at regular intervals in the horizontal axis direction, and intersect with the active regions 12.

Subsequently, since the gate electrode 17 is a line type, the word line overlaps the end of the active region 12 other than the channel region.                         

In the conventional method of forming a word line of a semiconductor device, since the gate electrode constituting the word line is a line type, the word line overlaps with an end portion of an active region other than the channel region, resulting in a voltage difference between the word line and the source / drain region. GIDL (Gate Induced Drain Leakage) is generated, and there is a problem in that the refresh characteristic is reduced because the charge stored in the capacitor is lost by GIDL in the dynamic random access memory (DRAM).

The present invention has been made to solve the above problems, and after forming a first gate electrode of type I on a semiconductor substrate in a channel region, a second gate electrode of line type is formed on the first gate electrode. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a word line of a semiconductor device which increases refresh characteristics by forming word lines formed of first and second gate electrodes.

The present invention for achieving the above object,

Forming a first gate electrode of an I type via a gate insulating film on the first conductive semiconductor substrate including the device isolation film;

Forming a source / drain region on the semiconductor substrate at both sides of the first gate electrode;

Forming an interlayer insulating film on the entire surface including the first gate electrode;

Etching an entire surface of the upper portion of the interlayer insulating layer and the first gate electrode to planarize it;

Providing a line type second gate electrode on the first gate electrode, and forming a word line including the first and second gate electrodes;

Forming the first and second gate electrodes as one or two or more stacked structures selected from the group consisting of a polycrystalline silicon layer, a tungsten (W) layer, and an aluminum (Al) layer;

Forming a nitride film or an oxide film from the interlayer insulating film;

The front etching process is performed by a dry etching process or a wet etching,

The front surface etching process may be performed by a chemical mechanical polishing process.

The principle of the present invention is to form a first gate electrode of type I on a semiconductor substrate in the channel region, and then form a second gate electrode of line type on the first gate electrode to form the first and second gate electrodes. By forming the formed word line, the word line is not overlapped with the end of the active region other than the channel region, thereby preventing the GIDL generated at the end of the active region and increasing the refresh characteristics.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3D are layout views illustrating a word line forming method of a semiconductor device according to an exemplary embodiment of the present invention, and FIGS. 4A to 4D are lines I-I and II-II of FIGS. 3A to 3D, respectively. It is a cross section.                     

3A and 4A, a shallow trench isolation (STI) process is performed on the isolation region of the p-type semiconductor substrate 31 to form the isolation layer 33 defining the active region 32.

Here, the active region 32 defined by the device isolation layer 33 is arranged in an I type while being spaced apart from the semiconductor substrate 31 by a predetermined interval in the horizontal axis direction, and is arranged so as to deviate from neighboring columns.

3B and 4B, the gate oxide layer 35 is grown on the semiconductor substrate 31 by a thermal oxidation process, and then a first polycrystalline silicon layer is formed on the gate oxide layer 35. In this case, instead of the first polycrystalline silicon layer, a tungsten (W) layer or an aluminum (Al) layer may be formed of a conductor used as an electrode material in a semiconductor device manufacturing process.

The first polycrystalline silicon layer is etched by the photolithography process using a mask for a gate electrode to form a first gate electrode 37, and the gate oxide layer 35 is etched. In this case, the first gate electrode 37 is formed in an I type which is formed only in the channel region of the active region 32 and not in the line type.

Subsequently, n-type impurity ions are ion-implanted on the entire surface with the first gate electrode 37 as a mask, and drive-in diffused to form a surface of the semiconductor substrate 31 on both sides of the first gate electrode 37. Source / drain regions 39 are formed.

An interlayer insulating layer 41 is formed on the entire surface including the first gate electrode 37. In this case, the interlayer insulating layer 41 may be formed in a semiconductor device manufacturing process, such as an oxide film such as a nitride film, a boron phosphosilicate glass (BPSG) layer, a low pressure-tetra ethyl ortho silicate (LP-TEOS) layer, or a high density plasma (HDP) layer. It is formed with all the insulating films normally used.

After that, the entire surface of the interlayer insulating layer 41 and the first gate electrode 37 is etched to planarize the entire surface. In this case, the front etching process may be performed by a dry etching process, a wet etching process or a chemical mechanical polishing process.

3C and 4C, a second polycrystalline silicon layer 43 is formed on the first gate electrode 37 and the interlayer insulating layer 41. In this case, instead of the second polycrystalline silicon layer 43, a tungsten (W) layer, an aluminum (Al) layer, or the like may be formed of a conductor used as an electrode material in a semiconductor device manufacturing process.

3D and 4D, the second polycrystalline silicon layer 43 is etched by a photolithography process using a mask for a word line to form a line type second gate electrode 43a on the first gate electrode 37. ).

Here, a word line formed of the first and second gate electrodes 37 and 43a is formed, and the word lines are arranged on the semiconductor substrate 31 at a predetermined interval in the horizontal axis direction, and the active regions ( 32) and two places crossed.

In the word line forming method of the semiconductor device of the present invention, the first gate electrode of the I type is formed on the semiconductor substrate in the channel region, and then the second gate electrode of the line type is formed on the first gate electrode. By forming a word line formed of the second gate electrode, the word line does not overlap with the end of the active region other than the channel region, thereby preventing GIDL generated at the end of the active region, thereby increasing the refresh characteristics. Since the word line is formed by dividing the first and second gate electrodes, an etching target is lower than in the etching process for forming a word line, thereby improving the characteristics, yield, and reliability of the device. There is.

Claims (5)

Forming a first gate electrode of an I type via a gate insulating film on the first conductive semiconductor substrate including the device isolation film; Forming a source / drain region on the semiconductor substrate at both sides of the first gate electrode; Forming an interlayer insulating film on the entire surface including the first gate electrode; Etching an entire surface of the upper portion of the interlayer insulating layer and the first gate electrode to planarize it; Forming a line type word line including the first and second gate electrodes by forming a second gate electrode connected to the first gate electrode on the interlayer insulating layer and the first gate electrode; Method for forming word lines of devices. The method of claim 1, Wherein the first and second gate electrodes are formed of one or two or more stacked structures selected from the group consisting of a polycrystalline silicon layer, a tungsten (W) layer, and an aluminum (Al) layer. . The method of claim 1, And forming a nitride film or an oxide film from the interlayer insulating film. The method of claim 1, The front surface etching process is a word line forming method of a semiconductor device, characterized in that performed by dry etching or wet etching. The method of claim 1, And the front surface etching process is performed by a chemical mechanical polishing process.

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