KR100866682B1 - Method for forming mask in semiconductor manufacturingprocess - Google Patents

Method for forming mask in semiconductor manufacturingprocess Download PDF

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Publication number
KR100866682B1
KR100866682B1 KR1020070062147A KR20070062147A KR100866682B1 KR 100866682 B1 KR100866682 B1 KR 100866682B1 KR 1020070062147 A KR1020070062147 A KR 1020070062147A KR 20070062147 A KR20070062147 A KR 20070062147A KR 100866682 B1 KR100866682 B1 KR 100866682B1
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KR
South Korea
Prior art keywords
layout
mask
pattern
recipe
opc
Prior art date
Application number
KR1020070062147A
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Korean (ko)
Inventor
도문회
Original Assignee
주식회사 동부하이텍
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Priority to KR1020070062147A priority Critical patent/KR100866682B1/en
Application granted granted Critical
Publication of KR100866682B1 publication Critical patent/KR100866682B1/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/66—Containers specially adapted for masks, mask blanks or pellicles; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

The method of making mask in the process of manufacturing semiconductor is provided to enhance the pattern fidelity in 90nm or less by applying recipe according to each layout. Desection is performed in consideration of pitch distance(the distance in which layout and spacer are added). Desection is performed on the edge portion in a state that each layout(200,210,220,230) is irregularly arranged. Besides, desection is performed in consideration of 360nm which is two times of the pitch distance.

Description

Mask manufacturing method in semiconductor manufacturing process {METHOD FOR FORMING MASK IN SEMICONDUCTOR MANUFACTURINGPROCESS}

1 shows a chip having several types of layouts,

2A to 2C are views illustrating patterns having various shapes for each region.

3A to 3B illustrate a method of manufacturing a mask in a semiconductor manufacturing process according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100, 110, 120, 130: Layout 140, 240: Section

150, 250: spacer 200, 210, 220, 230: layout

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a mask in a semiconductor manufacturing process, and more particularly, to applying pattern recipes that can match each characteristic according to the layout of different characteristics formed on a chip. It is related with the mask manufacturing method in the semiconductor manufacturing process which can raise.

In general, the OPC refers to a pattern for correcting the deformation value by calculating a value to be deformed in advance when the mask pattern is projected onto the substrate, and is also referred to as "proximity effect correction" and "optical proximity compensation".

When the OPC is described in more detail, an image of a layout pattern, which is a circuit pattern projected on a substrate, is different from the shape of an actual mask pattern when performing an exposure process using light diffraction. In particular, when the spacing of adjacent patterns on the mask is close, they affect each other, which causes a lot of difference from the design value. This phenomenon is called an optical proximity effect (OPE). Therefore, in order to correct the optical proximity effect, it is necessary to reinforce the size of the pattern or the edge of the mask to approximate the data of the mask through additional simulation to the CAD data for design.

In the early days of OPC, only the function of increasing or decreasing the line width of one-dimensional circuit patterns was possible, but now two-dimensional OPC is possible with shorter edges of the circuit patterns. Recently, Full Chip OPC that uses OPC to the periphery and core area as well as the repetitive cell pattern is widely used.

OPC is divided into the case of presenting rule by pattern size (hereinafter referred to as "Rule based OPC") and the simulation based OPC (hereinafter referred to as "Model based OPC"). In the case of rule based OPC, OPC is easy. On the other hand, the accuracy is low, and in the case of Model-based OPC, the accuracy is high, but the data production is not easy, so the mask production is not easy. Generally, it is better to apply Rule based OPC because of the simple and repetitive circuit pattern in DRAM. In the case of LOGIC, Model based OPC method is recommended.

Referring to the illustrated conventional drawings, FIG. 1 illustrates a chip having various types of layouts, and in FIGS. 2A to 2C, patterns of various shapes are present for each region.

As shown in FIG. 1, 10 represents an SRAM region, 20 represents a flash memory, 30 represents a general logic region, and 40 represents an area of a digital to analog converter (DAC) or an analog to digital converter (ADC).

Each of the regions 10, 20, 30, and 40 has a pattern having various shapes as shown in FIGS. 2A to 2C.

However, conventionally, in the case of a multi-chip such as an SOC (System On Chip), OPC is performed using only one model and one recipe. This has a limit in increasing pattern fidelity with only one recipe.

For reference, the recipe described here requires simulation through modeling and a desection process to apply correction values calculated through the simulation. Applying the correction value to this desected pattern is OPC.

Therefore, as a section having a single section rule, it is possible to proceed to a certain degree of loss of pattern fidelity up to 130 nm, but below 90 nm, there is a problem of causing serious problems during the photo and etching process.

The present invention has been devised to solve the above-mentioned drawbacks, and by applying the recipe to each layout, the pattern fidelity can be increased even at 90 nm or less, and the elapsed time required to manufacture the mask with more efficient recipe management is further improved. It is an object of the present invention to provide a method for manufacturing a mask in a semiconductor manufacturing process that can be reduced.

The present invention for achieving the above object is a method of manufacturing a mask in a semiconductor manufacturing process using a recipe that can match each characteristic in a layout having different characteristics, the multiple of the pitch on the edge of the layout or layout It provides a mask manufacturing method in a semiconductor manufacturing process, characterized in that the recipe is made in proportion to the distance.

Here, the recipe is simulated through modeling, and the section for applying the correction value calculated through the simulation is made on the layout in proportion to the multiple distance of the pitch according to the influence of the surrounding pattern.

In addition, in the simple pattern, the recipe is performed only at the corner side of the layout according to the pitch distance formed between the layout and the spacer, and the recipe is performed considering the pitch distance twice or three times for each type due to the influence of the surroundings. It features.

Hereinafter, the present invention will be described in detail with reference to the most preferred embodiment of the present invention in order to explain in detail a person skilled in the art to easily implement the technical idea of the present invention.

 3A to 3B illustrate a method of manufacturing a mask in a semiconductor manufacturing process according to an embodiment of the present invention.

According to FIG. 3A according to an exemplary embodiment, in the layouts 100, 110, 120, and 130, which are simply vertically arranged at regular intervals, the effects on each other are similar. Therefore, each section 140 for the recipe may be implemented only at the corners.

That is, when the layouts 100, 110, 120, 130 are 90 nm, and the spacers 150 are 90 nm, the pitch is determined in consideration of the pitch distance of up to 180 nm in which one layout 100 and the spacer 150 are added. Section 140 is implemented.

In addition, in another embodiment of FIG. 3B, each layout 200, 210, 220, 230 has one or two sections as well as a section 240 at the corners in a state where the layouts 200, 210, 220, 230 are not irregularly arranged. The desection 240 is performed in consideration of 360 nm, which is a double pitch distance in which the spacers 250 are added to the two layouts.

Accordingly, when the sections 140 implemented in the layouts 100, 110, 120, and 130 of FIG. 3A are applied to each of the layouts 200, 210, 220, and 230 of FIG. 3B. However, even if modeling is correct, it may show an incorrect OPC result of the section 140.

On the other hand, the section 240 of FIG. 3B is applied to the layouts 100, 110, 120, 130 of FIG. 3A to align the layouts 200, 210, 220, 230 of FIG. 3B. In this case, excessive desection is made in the layouts 100, 110, 120, and 130, so that the amount of correction is increased to increase the elapsed time required to manufacture the mask.

Therefore, in the present invention, pattern fidelity can be increased by applying a recipe (section) suitable for each layout.

What has been described above is only one embodiment for carrying out the method of manufacturing the mask in the semiconductor manufacturing process according to the present invention, the present invention is not limited to the above embodiment, as claimed in the following claims Without departing from the gist of the present invention, any person having ordinary knowledge in the field of the present invention will have the technical spirit of the present invention to the extent that various modifications can be made.

As described above, in the method of manufacturing a mask in the semiconductor manufacturing process of the present invention, by applying the recipe to each layout, the pattern fidelity can be increased even at 90 nm or less, and the elapsed time required for mask production by more efficient recipe management. This shortens the ability to attract more customers, resulting in more benefits.

Claims (2)

As a mask manufacturing method in a semiconductor manufacturing process using a recipe that can match each characteristic in a layout having different characteristics, A method of fabricating a mask in a semiconductor manufacturing process, characterized in that a recipe is made in proportion to a drainage distance of a pitch on the corner of the layout or the layout. delete
KR1020070062147A 2007-06-25 2007-06-25 Method for forming mask in semiconductor manufacturingprocess KR100866682B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070062147A KR100866682B1 (en) 2007-06-25 2007-06-25 Method for forming mask in semiconductor manufacturingprocess

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070062147A KR100866682B1 (en) 2007-06-25 2007-06-25 Method for forming mask in semiconductor manufacturingprocess

Publications (1)

Publication Number Publication Date
KR100866682B1 true KR100866682B1 (en) 2008-11-04

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050063410A (en) * 2003-12-22 2005-06-28 주식회사 하이닉스반도체 Method for fabrication of semiconductor device
KR20060036385A (en) * 2003-05-20 2006-04-28 페어차일드 세미컨덕터 코포레이션 Structure and method for forming a trench mosfet having self-aligned features

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060036385A (en) * 2003-05-20 2006-04-28 페어차일드 세미컨덕터 코포레이션 Structure and method for forming a trench mosfet having self-aligned features
KR20050063410A (en) * 2003-12-22 2005-06-28 주식회사 하이닉스반도체 Method for fabrication of semiconductor device

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