CN108931883B - Method for optimizing mask layout - Google Patents
Method for optimizing mask layout Download PDFInfo
- Publication number
- CN108931883B CN108931883B CN201710351038.7A CN201710351038A CN108931883B CN 108931883 B CN108931883 B CN 108931883B CN 201710351038 A CN201710351038 A CN 201710351038A CN 108931883 B CN108931883 B CN 108931883B
- Authority
- CN
- China
- Prior art keywords
- sub
- resolution auxiliary
- mask layout
- region
- resolution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000009826 distribution Methods 0.000 claims abstract description 19
- 238000002834 transmittance Methods 0.000 claims abstract description 18
- 238000005286 illumination Methods 0.000 claims description 9
- 238000001459 lithography Methods 0.000 claims description 7
- 239000013589 supplement Substances 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 14
- 230000008569 process Effects 0.000 description 13
- 238000005457 optimization Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004847 absorption spectroscopy Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007619 statistical method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
The invention provides a method for optimizing a mask layout, which comprises the following steps of S1: providing a mask layout of laid chip design patterns, wherein the mask layout comprises a first main pattern, a plurality of first sub-resolution auxiliary patterns arranged around the first main pattern, a second main pattern and a plurality of second sub-resolution auxiliary patterns arranged around the second main pattern, and the first sub-resolution auxiliary patterns and the second sub-resolution auxiliary patterns define a conflict region; step S2: intercepting the conflict region on a mask layout, acquiring a light transmittance distribution gray scale map of the conflict region, and setting a priority for the sub-resolution auxiliary graph in the conflict region according to the gray scale value statistic of the light transmittance distribution gray scale map; step S3: and removing the sub-resolution auxiliary graph with low priority to obtain the optimized mask layout. The invention can effectively supplement the spatial frequency around the main pattern.
Description
[ technical field ] A
The invention relates to the technical field of photoetching resolution enhancement, in particular to a method for optimizing a mask layout.
[ background of the invention ]
With the continuous reduction of chip manufacturing technology nodes, the difference of process windows of dense lines and sparse lines on a mask plate is more and more obvious, and the process window of the sparse lines is smaller, so that the photoetching process window of the whole mask plate can be greatly restricted.
In order to solve the above problem, Sub Resolution Assist Features (SRAFs), also called Scattering Bars (SB), may be added around the sparse Features of the mask layout corresponding to the mask, so that the mask may be more dense, and the spatial frequency around the main Features may be supplemented. The most critical point for placing the scattering bars is to increase the process window as much as possible, but to ensure that the scattering bars are not transferred to the photoresist after exposure.
SRAFs are typically inserted in the form of scattering bars around the sparse pattern of Contact layers (Contact layers) and Metal layers (Metal layers) to ensure uniformity of resolution and lithographic process window across the entire chip.
In general, there are two ways to insert auxiliary patterns, namely model-based SRAF (MB-SRAF) and rule-based SRAF (RB-SRAF).
MB-SRAF computationally inserts scattering bars around the pattern according to a strict optical model. The method is too long in time consumption and is not beneficial to the production and the manufacture of the chip.
The RB-SRAF is set with a series of rules according to the position of the main pattern or the target pattern, and the SRAF is placed according to the rules, and the effectiveness and coverage rate thereof depend on the knowledge and experience of the engineer on the process. The method has low coverage rate, is not suitable for relatively complex graph distribution, and has the advantage of short time consumption.
Adding SRAF to sparse graphics is an important method of Resolution Enhancement Technology (RET). Especially, the effective placement of the SRAF can enlarge the process window and improve the resolution of the graph when the process is below the 45nm node.
The SRAFs must be placed at certain positions around the main pattern or target pattern to be sufficiently effective, and the width of the SRAFs, the distance between the SRAFs and the main pattern or target pattern, and the distance between adjacent SRAFs are all critical parameters in determining the effectiveness of the SRAFs and the manufacturability of the chip. In actual production, a part of a representative Test Pattern (Test Pattern) is usually designed, scattering bars are added to the part of the Pattern by using MB-SRAF (multi-layer-sequential absorption spectroscopy) or inverse lithography, and then a set of rules are summarized by combining the results of model or inverse lithography, and the rules are applied to mass production. This combines the two methods to provide SRAFs with considerable accuracy and also to reduce the loss in time to a great extent. However, the RB-SRAF method itself has room for optimization, for example, two main patterns are very close together, and the SRAFs added to them can be very close to each other or very close to each other, which makes the mask manufacturing difficult, and therefore it is also necessary to clean them after the SRAFs are added to ensure that no conflict exists finally.
For RB-SRAFs, priorities are set for them at the time of placement, so that the order of placement of SRAFs can be determined according to the priorities, and when two SRAFs conflict with each other, a trade-off can be made according to the priorities.
The priority of the sub-resolution assist feature (SRAF) within the mask layout in the prior art is set according to its area size and location from the main feature. Therefore, the area is inevitably smaller, but the SRAF which can effectively supplement the spatial frequency around the main pattern and increase the process window is abandoned, so that the process window of chip manufacturing is reduced, and the production yield is reduced.
[ summary of the invention ]
In order to overcome the technical problems in the prior art, the invention provides a method for optimizing a mask layout.
The technical solution for solving the technical problem of the present invention is to provide a method for optimizing a mask layout, comprising the following steps, S1: providing a mask layout of laid chip design graphs, wherein the mask layout comprises a first main graph and a plurality of first sub-resolution auxiliary graphs arranged around the first main graph, the mask layout further comprises a second main graph and a plurality of second sub-resolution auxiliary graphs arranged around the second main graph, the first sub-resolution auxiliary graphs and the second sub-resolution auxiliary graphs define a conflict region, and the first sub-resolution auxiliary graphs and the second sub-resolution auxiliary graphs in the conflict region conflict with each other; step S2: intercepting the conflict region on a mask layout, acquiring a light transmittance distribution gray scale map of the conflict region, and setting priority for the sub-resolution auxiliary graph in the conflict region according to the gray scale value statistic of the light transmittance distribution gray scale map; step S3: and removing the sub-resolution auxiliary graph with low priority to obtain the optimized mask layout.
Preferably, in step S2, a light transmittance distribution gray scale map of the collision region is obtained by a lithography machine, and the illumination condition of the lithography machine is dark field or bright field.
Preferably, the sub-resolution auxiliary pattern gray value statistic is used as the priority in the dark field, and the absolute value of the difference between the maximum gray value minus the sub-resolution auxiliary pattern gray value statistic is used as the priority in the bright field.
Preferably, the gray value statistic may be an average gray value of the region, a peak gray value of the region, or a weighted average of the average gray value and the peak gray value of the region in proportion.
Preferably, the area has a ratio of the average gray scale value to the gray peak weight of 1: 1.
Compared with the traditional mask layout optimization method, the mask layout optimized by the method provided by the invention can effectively improve the depth of focus, thereby improving the photoetching resolution, so that the process window of chip manufacturing is enlarged, and the production yield is improved.
[ description of the drawings ]
FIG. 1 is a flow chart of a method of optimizing a mask layout of the present invention.
FIG. 2 is a schematic diagram of a partial layout of a sub-resolution auxiliary pattern having conflicts on a mask layout according to a method for optimizing the mask layout of the present invention.
Fig. 3 is an enlarged schematic view of the structure of fig. 2 at a.
Fig. 4 is a gray scale diagram of the mask transmittance distribution corresponding to fig. 2.
FIG. 5 is a mask transmittance distribution gray scale diagram of a main pattern under a bright field condition according to a method for optimizing a mask layout of the present invention.
FIG. 6 is a mask transmittance distribution gray scale diagram of a main pattern under a dark field condition according to a method for optimizing a mask layout of the present invention.
[ detailed description ] embodiments
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the present invention provides a method for optimizing a mask layout, which includes the following steps.
Step S1: providing a mask layout of laid chip design patterns, wherein the mask layout comprises a first main pattern and a plurality of first sub-resolution auxiliary patterns arranged around the first main pattern, the mask layout further comprises a second main pattern and a plurality of second sub-resolution auxiliary patterns arranged around the second main pattern, and the first sub-resolution auxiliary patterns and the second sub-resolution auxiliary patterns define a conflict region.
Specifically, a design graph of a target chip is provided, a mask layout corresponding to the design graph of the target chip is designed on a mask according to the design graph of the target chip, and the mask layout is arranged according to the photoetching requirement of the design graph of the target chip. The mask layout comprises a plurality of main graphs, when the sub-resolution auxiliary graphs are placed around different main graphs on the basis of rules, conflicts inevitably exist, and the conflict sub-resolution auxiliary graphs need to be accepted or rejected to ensure that the exposed graphs are consistent with target graphs, namely more diffraction orders carrying spatial modulation information are ensured to participate in imaging, a process window is enlarged, and the resolution of the graphs is improved.
Referring to fig. 2 and 3, since the layout on the reticle includes a plurality of main patterns with close distances, when sub-resolution auxiliary patterns are placed around different main patterns based on rules, the conflicting sub-resolution auxiliary patterns need to be chosen to ensure the exposure accuracy of the main patterns. The conflict between the sub-resolution auxiliary patterns of different main patterns means that the sub-resolution auxiliary patterns of adjacent main patterns are too close to each other, and the condition of violating Mask Rule Check (MRC) is not aimed at the condition of overlapping SRAFs.
Referring to fig. 2, an area S where there is a conflict between sub-resolution auxiliary patterns is cut out from the mask layout, where the area S includes four main patterns 101a, 101b, 101c, and 101d and a plurality of sub-resolution auxiliary patterns 103 arranged around each main pattern, where two main patterns 101b and 101c located in the middle have an area a between the two main patterns 101b and 101 c.
Referring to FIG. 3, the area A has two conflicting sub-resolution auxiliary graphics, respectively designated 103a and 103 b. The two sub-resolution auxiliary patterns 103a of the region a belong to the main pattern 101b, and the sub-resolution auxiliary pattern 103b is a sub-resolution auxiliary pattern of the main pattern 101 c.
A plurality of sub-resolution auxiliary pattern rings are arranged around the main pattern 101b and the main pattern 101c, and the sub-resolution auxiliary pattern rings are circumferentially distributed on the main pattern by taking the main pattern as a circle center. The different sub-resolution auxiliary pattern circles are not equidistant from the same main pattern. The sub-resolution auxiliary graph circle closest to the main graph is called a first circle of sub-resolution auxiliary graph, the sub-resolution auxiliary graph circle closest to the main graph is called a second circle of sub-resolution auxiliary graph, and the same reasoning is repeated.
Wherein the sub-resolution auxiliary pattern 103a is a first turn of sub-resolution auxiliary pattern of the main pattern 101b, and the sub-resolution auxiliary pattern 103b is a third turn of sub-resolution auxiliary pattern of the main pattern 101 c. The distance from the sub-resolution auxiliary pattern 103a to the main pattern 101a is smaller than the distance from the sub-resolution auxiliary pattern 103b to the same edge of the main pattern 101 b.
The sub-resolution auxiliary pattern 103a has a length D1, a width W1, and a length D1 of 80nm, and a width W1 of 20 nm. The sub-resolution auxiliary pattern 103b has a length D2, D2 equal to 120, a width W2, and W2 equal to 20. Wherein D2> D1, W1 ═ W2. The distance between the sub-resolution auxiliary pattern 103a and the sub-resolution auxiliary pattern 103b is W3, and the value of W3 is smaller than the distance threshold, so that there is a conflict between the sub-resolution auxiliary pattern 103a and the sub-resolution auxiliary pattern 103b, and according to the reticle preparation rule, one of them needs to be removed, while according to the existing rule, the sub-resolution auxiliary pattern 103b with a larger area has a higher priority and is finally retained, and the sub-resolution auxiliary pattern 103a with a smaller area is removed. However, the sub-resolution auxiliary pattern 103a as the first sub-resolution auxiliary pattern of the main pattern 101b may increase the depth of focus more, thereby increasing the resolution of the main pattern to a greater extent, so that the sub-resolution auxiliary pattern that should be remained is removed conventionally.
In this embodiment, the number of the main patterns is four but not limited to four, and may be two, three or five, which is not described again. The number of the sub-resolution auxiliary patterns in which the conflict exists is two, but is not limited to two, and may be two or more.
Step S2: and intercepting the conflict region on the mask layout, acquiring a light transmittance distribution gray scale map of the conflict region, and setting priority for the sub-resolution auxiliary graph in the conflict region according to the gray scale value statistic of the light transmittance distribution gray scale map.
Referring to fig. 4, a mask optimization is performed on the region S in the mask blank map in fig. 2, a mask transmittance distribution gray scale map of the optimized region is obtained through simulation, and meanwhile, the gray scale value statistic of the mask transmittance distribution gray scale map of the region is obtained. In this embodiment, the statistical amount of the gray-scale values is preferably the average gray-scale value of the region S.
The simulation used an NXT1950i lithography machine with a numerical aperture NA of 1.35, a wavelength of 193nm, ring illumination, and bright field illumination conditions.
The mean gray scale values of the regions contained in 103a and 103b are calculated and are denoted as
And setting priority for the sub-resolution auxiliary graph according to the gray value of the obtained gray map. The gray scale value is the depth of the dot color in the black-and-white image, and generally ranges from 0 to 255, black is 0, and white is 255. After the mask light transmittance distribution gray level image is converted into a gray level image, if the gray level image is formed by m multiplied by n pixel points, m and n are natural numbers, the information of each pixel point of the image is represented by a matrix with m rows and n columns, and is marked as GmnElement g thereofijAnd expressing the gray value of the pixel point at the corresponding position in the gray map. The average gray value of the image is all the elements gijThe average value of (A) is recorded as
The calculation formula is as follows.
When the illumination condition is bright field, defining the priority of the sub-resolution auxiliary graph as
The embodiment calculates the priority P of 103a by using MTALB programming A111, 103b has an average gray value of PB＝65，PA＞PBI.e., 103a has a higher priority than 103 b.
That is, when the illumination condition is a bright field, as shown in fig. 5, only the mask transmittance distribution gray scale of the main pattern in the bright field is shown, and under this condition, the sub-resolution auxiliary pattern priority level is defined as
When the lighting condition is dark field, as shown in FIG. 6, the mask transmittance distribution gray scale pattern of the main pattern in the dark field is only shown, and in this condition, the sub-resolution auxiliary pattern priority is defined as
It is to be understood that as a variation, the sub-resolution auxiliary graphic priority size P may be when the illumination condition is a bright field
Where a is the maximum gray value.
Step S3: and removing the sub-resolution auxiliary graph with low priority to obtain the optimized mask layout.
Specifically, as can be seen from step S2, since the priority of 103a should be retained, 103b should be cleared, that is, the sub-resolution auxiliary pattern 103b with the lower priority is removed, and the optimized mask layout is obtained. If the sub-resolution auxiliary patterns of the plurality of regions in the mask layout conflict, optimizing the sub-resolution auxiliary patterns in the plurality of regions, removing the sub-resolution auxiliary patterns with low priority, and acquiring the optimized mask layout so as to be used for manufacturing the mask of the chip.
If the priorities of the conflicting sub-resolution auxiliary graphs are the same, the sub-resolution auxiliary graph with the larger area is reserved. This also facilitates the manufacture of the reticle.
The present invention provides a second embodiment, which is different from the first embodiment in that the statistic of the gradation value of the region S in step S2 is the peak value of the gradation value included in the region S.
Specifically, the Peak values of the gray values of the areas included in the sub-resolution auxiliary patterns 103a and 103b are calculated and are respectively denoted as PeakaAnd PeakbAnd setting priority for the sub-resolution auxiliary graph according to the obtained peak value, wherein the calculation formula is as follows:
Peak＝max{gij}
when the lighting condition is a bright field, as shown in fig. 5, the sub-resolution auxiliary graphic priority size is defined as P ═ 255-Peak under this condition. When the lighting condition is dark field, as shown in fig. 6, the sub-resolution auxiliary pattern priority size is defined as P ═ Peak under this condition.
The embodiment calculates the priority P of 103a by using MTALB programmingaThe average gray value of 86 and 103b is Pb 49, PaPb, i.e., 103a is higher priority than 103 b. And removing the sub-resolution auxiliary graph with low priority to obtain the optimized mask layout.
It is to be understood that as a variation, the sub-resolution auxiliary graphic priority size P may be when the illumination condition is a bright field
Where a is the maximum gray value.
The present invention provides a third embodiment, which is different from the first embodiment in that the statistic of the gradation value of the region S in step S2 is an average of the average gradation value and the gradation peak value in the region S weighted by a certain weight.
Specifically, the average gray value and the peak gray value in the sub-resolution auxiliary patterns 103a and 103b included region are weighted and averaged according to a certain weight, and are respectively denoted as WaAnd WbAnd setting priority for the sub-resolution auxiliary graph according to the obtained weighted average value, wherein the calculation formula is as follows:
wherein, w1、w2Are respectively as
And the weight of Peak, and w1+w2In this embodiment, take w1＝w20.5. When the lighting condition is bright field, as shown in fig. 5, the sub-resolution auxiliary graphic priority size is defined as P ═ 255-W under this condition. When the lighting condition is dark field, as shown in fig. 6, the sub-resolution auxiliary pattern priority size is defined as P ═ W under such condition.
The embodiment utilizes MTALB programming to calculate the priority of 103a as WaThe mean gray value of 98.5 and 103b is Wb＝57，PA＞PBI.e., 103a has a higher priority than 103 b. And removing the sub-resolution auxiliary graph with low priority to obtain the optimized mask layout.
It is to be understood that as a variation, the sub-resolution auxiliary graphic priority size P may be when the illumination condition is a bright field
Where a is the maximum gray value.
Specifically, as can be seen from step S2, in all of the 3 statistical methods, the sub-resolution auxiliary patterns 103a have a higher priority than 103b, and 103a should be retained. Further, in order to verify the advancement of the optimization method for optimizing the mask layout provided by the present invention, the mask layout conflict regions of 103a and 103b are respectively simulated, and the simulation results of the depth of focus and the exposure latitude are obtained, as shown in table 1.
Table 1:
| reserved SRAF | Depth of focus | Latitude of |
| 103a | 123.6 | 30.99 |
| 103b | 98.12 | 29.63 |
The result shows that compared with the traditional mask layout optimization method, the mask layout optimized by the method provided by the invention can effectively improve the depth of focus, thereby improving the photoetching resolution, so that the process window of chip manufacturing is enlarged, and the production yield is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit of the present invention are intended to be included within the scope of the present invention.
Claims (5)
1. A method of optimizing a mask layout, characterized by: comprises the following steps of (a) preparing a solution,
step S1: providing a mask layout of laid chip design graphs, wherein the mask layout comprises a first main graph and a plurality of first sub-resolution auxiliary graphs arranged around the first main graph, the mask layout further comprises a second main graph and a plurality of second sub-resolution auxiliary graphs arranged around the second main graph, the first sub-resolution auxiliary graphs and the second sub-resolution auxiliary graphs define a conflict region, and the first sub-resolution auxiliary graphs and the second sub-resolution auxiliary graphs in the conflict region conflict with each other;
step S2: intercepting the conflict region on a mask layout, acquiring a light transmittance distribution gray scale map of the conflict region, and setting priority for the sub-resolution auxiliary graph in the conflict region according to the gray scale value statistic of the light transmittance distribution gray scale map;
step S3: and removing the sub-resolution auxiliary graph with low priority to obtain the optimized mask layout.
2. The method of optimizing a mask layout of claim 1, characterized by: in step S2, a light transmittance distribution gray scale map of the collision region is obtained by a lithography machine, and the illumination condition of the lithography machine is a dark field or a bright field.
3. The method of optimizing a mask layout of claim 2, wherein: in the dark field, the sub-resolution auxiliary pattern gray value statistic is used as priority, and in the bright field, the absolute value of the difference between the maximum gray value and the sub-resolution auxiliary pattern gray value statistic is used as priority.
4. A method of optimizing a mask layout as claimed in claim 3, characterized in that: the gray value statistic may be an average gray value of the region, a peak gray value contained in the region, or a weighted average of the average gray value and the peak gray value of the region in proportion.
5. The method of optimizing a mask layout of claim 4, wherein: the average gray value to gray peak weight ratio for this region is 1: 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710351038.7A CN108931883B (en) | 2017-05-17 | 2017-05-17 | Method for optimizing mask layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710351038.7A CN108931883B (en) | 2017-05-17 | 2017-05-17 | Method for optimizing mask layout |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108931883A CN108931883A (en) | 2018-12-04 |
| CN108931883B true CN108931883B (en) | 2022-06-21 |
Family
ID=64450574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710351038.7A Active CN108931883B (en) | 2017-05-17 | 2017-05-17 | Method for optimizing mask layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108931883B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110058485B (en) * | 2019-05-09 | 2022-04-22 | 上海华力微电子有限公司 | OPC correction method and OPC correction system |
| CN110765724B (en) * | 2019-10-26 | 2023-04-18 | 东方晶源微电子科技（北京）有限公司 | Mask optimization method and electronic equipment |
| CN112099319B (en) * | 2020-09-17 | 2023-10-03 | 中国科学院微电子研究所 | Sub-resolution auxiliary graph adding method and device and computer readable storage medium |
| CN117454831B (en) * | 2023-12-05 | 2024-04-02 | 武汉宇微光学软件有限公司 | Mask pattern optimization method and system and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1612606A2 (en) * | 2001-02-23 | 2006-01-04 | ASML Netherlands B.V. | Illumination optimization for specific mask patterns |
| CN101305320A (en) * | 2005-09-09 | 2008-11-12 | 睿初科技公司 | System and method for mask verification using an individual mask error model |
| CN102096909A (en) * | 2010-12-30 | 2011-06-15 | 东北大学 | Improved unsharp masking image reinforcing method based on logarithm image processing model |
| CN102129166A (en) * | 2010-01-12 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Method for setting sub-resolution assistance feature and method for producing photoetching mask plate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100585469B1 (en) * | 2001-02-27 | 2006-06-02 | 에이에스엠엘 네델란즈 비.브이. | An Optical Proximity Correction Method Utilizing Gray Bars As Sub-Resolution Assist Features |
| TWI225965B (en) * | 2003-05-14 | 2005-01-01 | United Microelectronics Corp | Photomask pattern |
-
2017
- 2017-05-17 CN CN201710351038.7A patent/CN108931883B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1612606A2 (en) * | 2001-02-23 | 2006-01-04 | ASML Netherlands B.V. | Illumination optimization for specific mask patterns |
| CN101305320A (en) * | 2005-09-09 | 2008-11-12 | 睿初科技公司 | System and method for mask verification using an individual mask error model |
| CN102129166A (en) * | 2010-01-12 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Method for setting sub-resolution assistance feature and method for producing photoetching mask plate |
| CN102096909A (en) * | 2010-12-30 | 2011-06-15 | 东北大学 | Improved unsharp masking image reinforcing method based on logarithm image processing model |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108931883A (en) | 2018-12-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108931883B (en) | Method for optimizing mask layout | |
| CN100520597C (en) | Method and system for optical proximity correction | |
| US8732625B2 (en) | Methods for performing model-based lithography guided layout design | |
| KR100731233B1 (en) | Method of creating mask pattern, method of manufacturing photomask and method of manufacturing semiconductor device | |
| US20060200790A1 (en) | Model-based SRAF insertion | |
| US8843859B2 (en) | Layout content analysis for source mask optimization acceleration | |
| TWI806863B (en) | Method for generating a photomask that includs sub-resolution assist features for target features | |
| CN110426914B (en) | Correction method of sub-resolution auxiliary graph and electronic equipment | |
| CN101228478A (en) | Method for generating photo mask graphic data, photo mask generated by the data and manufacturing method of semiconductor device using the photo mask | |
| US20160162623A1 (en) | Method, computer readable storage medium and computer system for creating a layout of a photomask | |
| US20110065027A1 (en) | Flare correction method, method for manufacturing mask for lithography, and method for manufacturing semiconductor device | |
| US9779186B2 (en) | Methods for performing model-based lithography guided layout design | |
| CN110597023B (en) | Photoetching process resolution enhancement method and device based on multi-objective optimization | |
| CN105045946B (en) | Method for IC manufacturing | |
| CN113589643B (en) | Curve type reverse photoetching method for synthesizing mask pattern based on superposition of modulation blocks | |
| KR20120069542A (en) | Recording medium recording program for generating mask data, method for manufacturing mask, and exposure method | |
| CN117148665A (en) | Rule-based exposure auxiliary graph adding method | |
| CN111812940A (en) | Method for optimizing exposure auxiliary graph in optical proximity effect correction | |
| US20140146311A1 (en) | Method of determining mask pattern and exposure condition, storage medium, and computer | |
| US9465907B2 (en) | Multi-polygon constraint decomposition techniques for use in double patterning applications | |
| CN107490932A (en) | The modification method of mask plate patterns | |
| CN113589644A (en) | Curve type reverse photoetching method based on sub-resolution auxiliary graph seed insertion | |
| KR102556509B1 (en) | Method for rasterization of mask layout and method of fabricating photomask using the same | |
| US7026078B2 (en) | Method of manufacturing photomask | |
| CN115576169A (en) | Scattering strip adding method and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100176 building 12, yard 156, Jinghai 4th Road, Beijing Economic and Technological Development Zone, Daxing District, Beijing Patentee after: Dongfang Jingyuan Microelectronics Technology (Beijing) Co.,Ltd. Patentee after: SHENZHEN JINGYUAN INFORMATION TECHNOLOGY Co.,Ltd. Address before: 100176 building 12, yard 156, Jinghai 4th Road, Beijing Economic and Technological Development Zone, Daxing District, Beijing Patentee before: DONGFANG JINGYUAN ELECTRON Ltd. Patentee before: SHENZHEN JINGYUAN INFORMATION TECHNOLOGY Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |