KR100864931B1 - Method of forming a gate oxide in semiconductor device - Google Patents

Method of forming a gate oxide in semiconductor device Download PDF

Info

Publication number
KR100864931B1
KR100864931B1 KR1020070059852A KR20070059852A KR100864931B1 KR 100864931 B1 KR100864931 B1 KR 100864931B1 KR 1020070059852 A KR1020070059852 A KR 1020070059852A KR 20070059852 A KR20070059852 A KR 20070059852A KR 100864931 B1 KR100864931 B1 KR 100864931B1
Authority
KR
South Korea
Prior art keywords
region
gate oxide
ions
oxide film
substrate
Prior art date
Application number
KR1020070059852A
Other languages
Korean (ko)
Inventor
임현주
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020070059852A priority Critical patent/KR100864931B1/en
Application granted granted Critical
Publication of KR100864931B1 publication Critical patent/KR100864931B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A method for forming a gate oxide layer of a semiconductor device is provided to obtain a desired threshold voltage in both of an NMOS region and a PMOS region by forming a gate oxide layer of the NMOS region including only nitrogen ions and a gate oxide layer of the PMOS region including the nitrogen ions and fluoric ions. A gate oxide layer(13b,13c,13d) is formed on a substrate including a first region and a second region. A first ion implantation process is performed to implant first ions only onto the gate oxide layer of the first region of the substrate including the gate oxide layer. A second ion implantation process is performed to implant second ions only onto the gate oxide layer of the second region of the substrate onto which the first ions are implanted. A plasma process using nitrogen ions for the gate oxide layer including the first and second ions is performed.

Description

Method of forming a gate oxide in semiconductor device

1 to 5 are process flowcharts showing a method of forming a gate oxide film of a semiconductor device according to the present invention.

<Description of the code | symbol about the principal part of drawing>

10: semiconductor substrate 12: device isolation film

13a, 13b, and 13c: gate oxide films 15 and 16: photoresist pattern

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate oxide film of a semiconductor device.

As the size of the current CMOSFET device is gradually reduced, various processes for forming the gate oxide film of the device have emerged.

Among them, there is a method of forming a gate oxide film through a plasma treatment process using nitrogen ions. In order to effectively reduce the electrical oxide thickness (E.O.T), only the gate ion film should contain nitrogen ions.

However, if a plasma treatment process using nitrogen ions is performed, an appropriate threshold voltage value can be obtained by nitrogen ions in the NMOS region of the device, while Fermi level pinning is performed by nitrogen ions in the PMOS region of the device. By the phenomenon, a threshold voltage higher than an appropriate threshold voltage value can be obtained.

Therefore, there is a problem that a device that does not have a desired threshold voltage (Vt) in the PMOS region is implemented.

An object of the present invention for solving the above problems is to provide a method for forming a gate oxide film of a semiconductor device such that the device having a desired threshold voltage (Vt) in both the NMOS region and PMOS is implemented.

According to another aspect of the present invention, there is provided a method of forming a gate oxide film of a semiconductor device, the method including forming a gate oxide film on a substrate divided into a first region and a second region, and forming a gate oxide film on the substrate on which the first gate oxide film is formed. Implanting first ions only into the gate oxide film of the first region, implanting second ions only into the gate oxide film of the second region of the substrate implanted with the first ions, and And performing a plasma treatment on the implanted gate oxide film.

The first region is a PMOS region, the second region is an NMOS region, the first ion implanted in the PMOS region is fluorine ion, and the ion implanted in the NMOS region is nitrogen ion.

The first region is an NMOS region, the second region is a PMOS region, the first ions implanted in the NMOS region are nitrogen ions, and the ions implanted in the PMOS region are fluorine ions.

The concentration of the injected fluorine ion is 4.0E14, the concentration of the nitrogen ion is injected is about 5.0E15.

The plasma processing step is a plasma processing step using nitrogen ions.

After the step of implanting the second ion, further comprising the step of performing an annealing process, the annealing process is performed at a temperature of about 750 ~ 850 ℃.

And forming a device isolation layer for defining the field region and the active region before forming the first gate oxide layer.

Implanting first ions only into a gate oxide layer of a first region of the substrate on which the first gate oxide layer is formed, forming a photoresist pattern exposing only the first region on the substrate on which the first gate oxide layer is formed; Performing an ion implantation process using the photoresist pattern as a mask for ion implantation, and removing the photoresist pattern.

Implanting second ions only into the gate oxide layer of the second region of the substrate on which the first gate oxide layer is formed comprises forming a photoresist pattern exposing only the second region on the substrate on which the first gate oxide layer is formed; Performing an ion implantation process using the photoresist pattern as a mask for ion implantation, and removing the photoresist pattern.

An embodiment of a method of forming a gate oxide film of a semiconductor device according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

1 to 5 are process flowcharts illustrating a method of forming a gate oxide film of a semiconductor device according to the present invention.

First, as shown in FIG. 1, a gate oxide layer 13 is formed on a substrate 10 divided into a peripheral region I in which a peripheral circuit is formed and a cell region II in which a memory cell is formed.

The peripheral region I is divided into a PMOS region (PMOS) in which a PMOS transistor is formed and an NMOS (NMOS) region in which an NMOS transistor is formed. Before the gate oxide layer 13a is formed, the device isolation layer 12 is formed in the field region on the substrate defined as the peripheral region and the cell region to define an active region in which a transistor such as a PMOS transistor or an NMOS transistor is formed. do.

As shown in FIG. 2, the first photoresist pattern 15 is formed on the PMOS region PMOS of the substrate 10 on which the gate oxide layer 13a is formed to form the gate oxide layer 13a of the NMOS region NMOS. To expose.

Subsequently, an ion implantation process of injecting nitrogen ions into the exposed gate oxide layer 13a of the NMOS region NMOS is performed to form a gate oxide layer 13b implanted with nitrogen ions. At this time, the concentration of nitrogen ions in the ion implantation process performed in the NMOS region (NMOS) is about 5.0E15.

As shown in FIG. 3, the first photoresist pattern 15 is removed by performing an ashing process on the substrate 10 on which the gate oxide film 13b into which the nitrogen ions are implanted is formed.

Subsequently, a second photoresist pattern 16 is formed on the NMOS region NMOS of the substrate from which the first photoresist pattern 15 is removed to expose the gate oxide layer 13a of the PMOS region PMOS.

Subsequently, an ion implantation process of implanting fluorine ions into the gate oxide layer 13a of the exposed PMOS region PMOS is performed to form a gate oxide layer 13c implanted with fluorine ions. At this time, the concentration of fluorine ions in the ion implantation process performed in the PMOS region (PMOS) is about 4.0E14.

Next, as shown in FIG. 4, the second photoresist pattern 15 is removed by performing an ashing process on the substrate 10 on which the gate oxide film 13c into which the fluorine ion is implanted is formed. Subsequently, an annealing process is performed on the entire surface of the substrate on which the gate oxide film 13c into which the fluorine ion is injected and the gate oxide film 13b into which the nitrogen ion is implanted is formed. Compensates for damage to the substrate.

The annealing process is performed at a temperature of about 750 ~ 850 ℃.

Next, as shown in FIG. 5, the gate oxide film 13a formed in the cell region II of the substrate 10 on which the annealing process is performed is removed, and the memory is stored in the cell region II of the substrate 10. A cell gate oxide film 13d is formed. Next, a plasma treatment process using nitrogen ions is performed on the entire surface of the substrate 10 on which the gate oxide film 13d for the memory cell is formed. ), Nitrogen ions are implanted into the memory oxide gate oxide film 13d. At this time, by the plasma treatment step using the nitrogen ions, each gate oxide film 13b, 13c, 13d has a nitrogen ion content of about 10%.

On the other hand, after the ion implantation process for injecting nitrogen ions into the NMOS region, the ion implantation process for injecting fluorine ions into the PMOS region is performed in the above embodiment, but the ion implanted fluorine ion in the PMOS region After the implantation process, an ion implantation process for implanting nitrogen ions into the NMOS region may be performed.

Therefore, the gate oxide film of the NMOS region containing only nitrogen ions and the gate oxide film of the PMOS region containing nitrogen and fluorine ions are formed, thereby realizing a device having a desired threshold voltage (Vt) in both the NMOS region and the PMOS.

While specific embodiments of the invention have been described and illustrated above, it will be apparent that the invention may be embodied in various modifications by those skilled in the art. Such modified embodiments should not be understood individually from the technical spirit or point of view of the present invention and such modified embodiments should fall within the scope of the appended claims of the present invention.

As described above, the gate oxide film forming method of the semiconductor device according to the present invention is formed by forming the gate oxide film of the NMOS region containing only nitrogen ions and the gate oxide film of the PMOS region containing nitrogen and fluorine ions. Both PMOSs have an effect of implementing a device having a desired threshold voltage Vt.

Claims (9)

Forming a gate oxide film on the substrate divided into a first region and a second region; Implanting first ions only into the gate oxide film of the first region of the substrate on which the gate oxide film is formed; Implanting second ions only into a gate oxide film of a second region of the substrate implanted with the first ions; And performing a plasma treatment process using nitrogen ions on the gate oxide film implanted with the first ions and the second ions. The method of claim 1, wherein the first region is a PMOS region, and the second region is an NMOS region. The method of claim 2, wherein the first ion implanted into the PMOS region is fluorine ion and the ion implanted into the NMOS region is nitrogen ion. The method of claim 1, wherein the first region is an NMOS region, and the second region is a PMOS region. The method of claim 4, wherein the first ions implanted into the NMOS region are nitrogen ions, and the ions implanted into the PMOS region are fluorine ions. The method of claim 1, further comprising performing an annealing process after the implanting of the second ions. According to claim 1, Forming a device isolation film for defining a field region and an active region before forming the gate oxide film. The method of claim 1, wherein injecting the first ions only into the gate oxide layer of the first region of the substrate on which the gate oxide layer is formed. Forming a photoresist pattern exposing only a first region on the substrate on which the gate oxide film is formed; Performing an ion implantation process using the photoresist pattern with an ion implantation mask; And removing the photoresist pattern. The method of claim 1, wherein the implanting of the second ions only into the gate oxide film of the second region of the substrate on which the gate oxide film is formed is performed. Forming a photoresist pattern exposing only a second region on the substrate on which the gate oxide film is formed; Performing an ion implantation process using the photoresist pattern with an ion implantation mask; And removing the photoresist pattern.
KR1020070059852A 2007-06-19 2007-06-19 Method of forming a gate oxide in semiconductor device KR100864931B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070059852A KR100864931B1 (en) 2007-06-19 2007-06-19 Method of forming a gate oxide in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070059852A KR100864931B1 (en) 2007-06-19 2007-06-19 Method of forming a gate oxide in semiconductor device

Publications (1)

Publication Number Publication Date
KR100864931B1 true KR100864931B1 (en) 2008-10-22

Family

ID=40177461

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070059852A KR100864931B1 (en) 2007-06-19 2007-06-19 Method of forming a gate oxide in semiconductor device

Country Status (1)

Country Link
KR (1) KR100864931B1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07161978A (en) * 1993-12-07 1995-06-23 Sony Corp Buried channel mos transistor and its manufacture
KR20000056495A (en) * 1999-02-22 2000-09-15 김영환 Method for forming gate oxide film of semiconductor device
KR20020054644A (en) * 2000-12-28 2002-07-08 박종섭 Manufacturing method for semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07161978A (en) * 1993-12-07 1995-06-23 Sony Corp Buried channel mos transistor and its manufacture
KR20000056495A (en) * 1999-02-22 2000-09-15 김영환 Method for forming gate oxide film of semiconductor device
KR20020054644A (en) * 2000-12-28 2002-07-08 박종섭 Manufacturing method for semiconductor device

Similar Documents

Publication Publication Date Title
JP3194370B2 (en) Semiconductor device and manufacturing method thereof
US6492218B1 (en) Use of a hard mask in the manufacture of a semiconductor device
KR100427469B1 (en) Method for fabricating semiconductor device
KR100864931B1 (en) Method of forming a gate oxide in semiconductor device
US7351627B2 (en) Method of manufacturing semiconductor device using gate-through ion implantation
JP2003068667A (en) Production method for semiconductor device
US9219013B2 (en) Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages
US6440809B1 (en) Method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide
KR100891248B1 (en) Method for forming triple gate oxide film
CN110783340B (en) Manufacturing method, circuit and application of floating gate type NOR flash memory
US20040266149A1 (en) Method of manufacturing semiconductor device
KR101096909B1 (en) Transistor of semiconductor device and method of fabricating the same
KR20070066023A (en) Method for fabricating dual gate of semiconductor device
CN103337458A (en) Method for improving electrical parameters of semiconductor devices
KR100261185B1 (en) Method for manufacturing semiconductor device
KR100600244B1 (en) Method for fabricating the multi-gate of semiconductor device
KR100420082B1 (en) Method for fabricating mos transistor of semiconductor device
KR100913324B1 (en) Method for forming a silicide layer in a semiconductor device
US20040266114A1 (en) Method for fabricating dual-gate semiconductor device
KR20030060438A (en) Method for fabricating semiconductor device with dual gate oxide
KR101026377B1 (en) INWE supression method of PMOSFET threshold voltage
KR101195269B1 (en) Method of fabricating semiconductor device having low contact resistance
KR100571424B1 (en) Method for forming stable transistor by double step source/drain implantion
CN103346125A (en) Method for improving uniformity of electrical parameters of GP CMOS components
KR20080060315A (en) Method for fabricating semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110920

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20120926

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee