KR100859634B1 - Semicondutor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided to suppress an erosion effect and to define an alignment mark by increasing a thickness of conductive material deposited in a dummy region. A chip region and a dummy region are defined on a substrate(10). An insulating layer is formed on the substrate. A plurality of via-holes(30) are formed in the insulating layer corresponding to the chip region. The via-holes are filled with conductive material. A recess(40) is formed on the insulating layer corresponding to the dummy region. The recess is filled with conductive material(50). The thickness of the conductive material filled in the recess is 1.5 to 3 times to the width of the via hole.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1A to 1F are cross-sectional views schematically illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.

2A to 2B are cross-sectional views schematically illustrating a manufacturing process of a semiconductor device according to a conventional structure.

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BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device employing a structure in which an alignment mark is normally defined by employing an improved structure and a method of manufacturing the same.

Recently, more than 10 ⁹ devices are integrated in one semiconductor chip. As the semiconductor chip becomes smaller and smaller, the device structure becomes more complicated, and the number of layers of the multilayer wiring increases, the surface of the chip increases irregularities. Therefore, planarization technology is becoming more important. Especially, chemical mechanical polishing (CMP) process is one of the semiconductor processes that are essentially introduced to meet the planarization demands of the size reduction and integration of semiconductor devices.

The CMP is a process of polishing a surface of a wafer mounted on a spindle by contacting a polishing pad on a surface of a rotating table while flowing a slurry of a liquid including silica particles. In particular, when a via hole is formed in an insulating film formed on a semiconductor substrate and a conductive material such as tungsten is buried in the via hole, the conductive material further deposited on and around the via hole is removed by CMP. At this time, using a slurry having a large selectivity of tungsten and oxide to prevent tungsten from remaining on the surface of the oxide. However, in the process of polishing the dissimilar materials, erosion occurs necessarily due to the characteristics of the CMP.

In recent years, as the size of semiconductor elements decreases, the amount of this erosion also decreases. However, even if the line width of the device is reduced, the alignment marks formed in the dummy area often use the existing mask having a wide line width as it is, so that the dummy area still causes extensive erosion by CMP. Therefore, a problem arises in that the alignment mark is not defined normally, which leads to a problem of the post process progress.

2A to 2B are cross-sectional views schematically illustrating a manufacturing process of a semiconductor device according to a conventional structure.

Referring to FIG. 2A, because the size of the recess 4 formed in the dummy region on the substrate 1 is relatively larger than the width of the via hole 3 formed in the chip region on the substrate 1, While the stents 5 are all buried and are further deposited on top, the tungsten 5 is not properly filled in the dummy region and still forms a recessed recess 4 in the form of a dent. Therefore, referring to FIG. 2B, the dummy region is further removed to the insulating film 2 while the tungsten 5 on the chip region is polished during CMP. Therefore, there is a problem that the alignment mark is not properly defined during the subsequent process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and provides a semiconductor device and a method of manufacturing the same, in which an alignment mark is clearly defined by employing an improved structure.

According to an exemplary embodiment of the present invention, a semiconductor device includes a substrate having a chip region and a dummy region defined therein, an insulating film formed on the substrate, a plurality of via holes formed in an insulating film of a region corresponding to the chip region, and filled with a conductive material; And a recess formed in the insulating layer corresponding to the dummy region and filled with the conductive material, wherein the thickness of the conductive material filled in the recess is greater than the width of the via hole.

In this case, the thickness of the conductive material filled in the recess may be 1.5 to 3 times larger than the width of the via hole.

In addition, an uppermost height of the conductive material filled in the recess may be substantially the same as that of the insulating layer.

In addition, the top of the conductive material filled in the recess may be formed substantially horizontally.

In addition, the conductive material may include tungsten.

 Meanwhile, the method of manufacturing a semiconductor device according to the present invention includes depositing an insulating film on a substrate, defining a chip region and a dummy region on the insulating layer, forming a plurality of via holes in the chip region, and recessing the dummy region. Forming, a first deposition step of depositing a conductive material on the insulating film on which the plurality of via holes and recesses are formed, a second deposition step of further depositing the conductive material on the deposited conductive material, and the deposited conductive And planarizing a material, wherein deposition rates in the first deposition step and the second deposition step may be different from each other.

In this case, the deposition rate in the second deposition step may be greater than the deposition rate in the first deposition step.

In addition, the deposition time in the first deposition step and the second deposition step may be formed to be substantially the same.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art can easily understand, the embodiments described below may be modified in various forms without departing from the spirit and scope of the present invention. Wherever possible the same or similar parts are represented with the same reference numbers in the drawings.

In addition, all terms including technical terms and scientific terms used below have the same meaning as commonly understood by one of ordinary skill in the art. Terms defined in advance are further interpreted to have a meaning consistent with the related technical literature and the presently disclosed contents, and are not interpreted in an ideal or very formal sense unless defined.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail.

1A to 1E are process diagrams schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. In FIGS. 1A to 1E, the size and thickness of the semiconductor substrate 10 and the insulating film 20 are somewhat exaggerated for clarity, but the present disclosure is not limited to those illustrated in the drawings.

First, as illustrated in FIG. 1A, an insulating film 20 is deposited on a substrate 10 in which chip regions and dummy regions are defined. The substrate 10 may be a silicon substrate, a compound semiconductor substrate, or an equivalent thereof, but is not limited thereto. The insulating film 20 is formed by growing a silicon oxide film on the surface of the semiconductor substrate 10 by reacting silicon and oxygen in a steam atmosphere of about 900 ° C. Although not shown, a silicon nitride film may be further formed on the insulating film by reacting silane (SiH 4) and ammonia (NH 3) gas at a high temperature through a vapor phase growth method or the like.

Next, as shown in FIG. 1B, a plurality of via holes 30 are formed in the insulating film 20 ′ in the chip region, and a recess 40 is formed in the insulating film 20 in the dummy region. The via hole 30 and the recess 40 may be formed by applying a photoresist on the insulating film 20, exposing the photoresist, and then etching the photo to form a photoresist pattern, and performing an etching process using the photoresist pattern as a mask. . On the other hand, each recess 40 region is scribed and separated into each chip in a subsequent die separating process.

Next, as shown in FIG. 1C, the conductive material 40 is filled in the plurality of via holes 30 and the recesses 40. This conductive material may be made of a material containing tungsten. First, the plurality of via holes 30 and the recesses 40 are buried at a deposition rate that is commonly used to prevent the formation of voids of the conductive material 50 filled in the plurality of via holes 30. 1 deposition step). In this case, the conductive material 50 is filled in the portion where the via hole 30 is formed in the chip region, but the conductive material 50 is not filled in the entire recess 40 of the relatively wide dummy region. Thus, as shown, the recess 40 is still formed.

Next, as illustrated in FIG. 1D, the conductive material 50 is deposited at a faster deposition rate than the above-described first deposition step (second deposition step). At this time, although the deposition time in the first deposition step and the second deposition step is substantially the same, since the deposition rate in the second deposition step is faster than the first deposition step, the conductive material 50 is deposited in the first deposition step. It is deposited in bulk on the conductive material 50. In this case, the conductive material 50 is further deposited in the portion where the via hole 30 is formed in the chip region to have a convex shape upward, and the thickness of the conductive material 50 deposited in the recess 40 in the dummy region is further increased. Is increased. As such, after the conductive material 50 is embedded in the via hole 30, the conductive material 50 is further buried in the upper portion of the via hole 30 and the recess 40 at a faster deposition rate. The thickness T of the conductive material 50 formed in the 40 may be larger than the width t of the via hole. More specifically, the thickness of the conductive material 50 formed in the recess 40 may be formed to be 1.5 to 3 times the via hole width t by controlling the deposition rate in the second deposition step.

Next, as illustrated in FIG. 1E, a chemical mechanical polishing (CMP) process is performed. The surface on which the conductive material 50 is deposited by CMP is brought into contact with the surface of the polishing pad 60 while supplying a slurry to chemically react the surface on which the conductive material is deposited. In addition, by relatively moving the carrier (not shown) to physically polish the surface on which the conductive material 50 is deposited, the surface planarization is realized as shown in FIG. 1F.

In this case, a slurry having a large selectivity of the conductive material and the oxide is used to prevent the conductive material from remaining on the oxide surface. That is, the formation of the via bridge must be prevented. However, in the present embodiment, since the thickness T of the conductive material deposited on the recess 40 formed in the dummy region during CMP is formed to be thicker than the thickness t of the via hole 30 formed in the chip region, In addition to preventing the formation of bridges, it also prevents erosion of the dummy region. That is, if the thickness T of the conductive material 50 formed in the recess 40 of the dummy region is equal to the thickness t of the conductive material formed in the via hole during the polishing of the conductive material during CMP, the via hole 30 may be used. While the pattern of the via hole is polished after the top and periphery of the conductive material 50 has been removed by polishing, the conductive material 50 formed over the recess in the dummy region is already eroded and the portion of the insulating film 20 'that is not desired to be removed. This is further eroded.

Therefore, in the present embodiment, the thickness T of the conductive material formed in the recess 40 is formed to be larger than the width t of the via hole to prevent erosion of the recess insulating insulating film 20 ′. In this case, as described above, the thickness of the conductive material 50 formed in the recess 40 may be formed in a range of 1.5 times to 3 times the width of the via hole. When the thickness T of the conductive material 50 formed in the recess 40 is 1.5 times or less than the width t of the via hole 30, the erosion degree of the insulating film is large, which completely prevents the formation of the via bridge, but properly aligns the mark. This is because it is not defined, and if it is 3 times or more, it undesirably deposits a lot of conductive material, which is contrary to economic efficiency.

In addition, in the present embodiment, since the conductive material is further deposited by the second deposition step as described above, the portion higher than the top height of the insulating film 20 ′ adjacent to the conductive material 50 embedded in the recess 40. Only the polishing is performed, and the insulating film 20 'in the portion located below the top height of the insulating film 20' is not polished. Thus, the top height of the conductive material filled in the recess 40 is formed substantially the same as the height of the insulating film. In addition, since the insulating film below the uppermost height of the insulating film is not polished, the uppermost portion of the conductive material formed in the recess is formed substantially horizontally.

As described above, since the semiconductor device 100 having the above configuration prevents erosion of the conductive material 50 formed along the recess 40 in the dummy region, the alignment mark is always clearly defined. Therefore, since the metal pattern is properly defined in the subsequent photolithography process, it is possible to prevent product defects and to significantly improve the yield.

Hereinafter, the present invention will be described in more detail according to the experimental example of the present invention. This experimental example is only for illustrating the present invention and the present invention is not limited thereto.

Experimental Example

In the present experimental example, deposition was performed on the insulating film under the first and second conditions using tungsten (W) as the conductive material. The first condition and the second condition are as follows.

Condition SiH4 (sccm) WF6 (sccm) Chamber pressure (mtorr) Deposition time (sec) First condition 25-35 50-60 800-900 30-50 Second condition 10-20 70-80 800-900 30-50

First, the via hole and the recess are buried in tungsten (first deposition step) under a first condition that is a deposition rate that suppresses the generation of voids in the via hole (first deposition step), and the second condition is 1.5 to 3 times faster than the first condition. Tungsten was deposited in bulk under (second deposition step). At this time, the deposition time was such that the first condition and the second condition were substantially the same. Under the second condition, the thickness of tungsten formed in the recess was formed 1.5 to 3 times the thickness of the via hole. In this case, when the CMP, which is a subsequent process, was performed, the insulating layer under the recess could be prevented from eroding.

Therefore, the phenomenon in which the alignment marks are defined indefinitely can be prevented so that the metal pattern can be accurately defined in the subsequent process of the photolithography process.

What has been described above is only one embodiment or experimental example according to the present invention, and the present invention is not limited to the above-described examples or experimental examples, and the scope of the present invention as claimed in the following claims is outside the scope of the present invention. Without this, anyone skilled in the art to which the present invention pertains will have the technical spirit of the present invention to the extent that various modifications can be made.

The present invention suppresses erosion by increasing the thickness of the conductive material deposited in the dummy region, so that the alignment mark is clearly defined.

In addition, the alignment marks are clearly defined so that the metal pattern can be clearly defined in the subsequent photolithography process.

In addition, it is possible to prevent the failure of the product in advance to significantly improve the yield.

Claims (8)

A substrate in which a chip region and a dummy region are defined, An insulating film formed on the substrate, A plurality of via holes formed in an insulating film in a region corresponding to the chip region and filled with a conductive material; A recess formed in the insulating layer corresponding to the dummy region and filled with the conductive material Including, And a thickness of the conductive material filled in the recess is 1.5 to 3 times greater than the width of the via hole. delete The method of claim 1, And a top height of the conductive material filled in the recess is substantially equal to a height of the insulating film. The method of claim 3, And a top portion of the conductive material filled in the recess is substantially horizontal. The method of claim 1, And the conductive material comprises tungsten. Depositing an insulating film on the substrate, Defining a chip region and a dummy region on the insulating layer, forming a plurality of via holes in the chip region, and forming a recess in the dummy region; A first deposition step of depositing a conductive material on the insulating film on which the plurality of via holes and recesses are formed; A second deposition step of further depositing the conductive material on the deposited conductive material, and Planarizing the deposited conductive material Including, And a deposition rate in the first deposition step and the second deposition step is different from each other. The method of claim 6, And the deposition rate in the second deposition step is greater than the deposition rate in the first deposition step. The method of claim 7, wherein And a deposition time in the first deposition step and the second deposition step is substantially the same.

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