KR100859243B1 - Apparatus for generating wordline driving signals in semiconductor memory device - Google Patents

Abstract

Disclosure of Invention The present invention provides a driving circuit that can solve a timing mismatch between a normal path and a redundancy path while driving a semiconductor memory, and at the same time reduce the wasted space due to signal sharing. Delay the pulse transition point of the signal bsenp to resolve the timing mismatch between the word line of the normal path and the redundancy path, or delay the pulse transition point of the redundancy word line selection signal Xhit to prevent the word of the normal path and the redundancy pass. The mismatch between lines is solved, and at the same time, the bank selection signal bsenp is externally applied to reduce waste space due to signal sharing in the conventional structure.

Redundancy Wordline, Normal Wordline, SDRAM, Timing Mismatch

Description

Apparatus for generating wordline driving signals in semiconductor memory device

1 is a block diagram schematically illustrating a semiconductor memory device for explaining a repair operation.

2 is a circuit diagram illustrating a word line driving signal generator of a semiconductor memory device according to the prior art.

3 is a circuit diagram illustrating each of the first to eighth fuse circuits 12a to 12h of FIG. 2 in detail.

FIG. 4A is a timing diagram of a driving signal during normal operation in the word line driving signal generator of the semiconductor memory device having the structure of FIG. 2.

FIG. 4B is a timing diagram of a driving signal during a repair operation in the word line driving signal generator of the semiconductor memory device having the structure of FIG. 2.

5A is a circuit diagram illustrating a word line driving signal generator of a semiconductor memory device according to a first embodiment of the present invention.

5B is a circuit diagram illustrating a word line driving signal generator of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6A is a timing diagram of a driving signal during normal operation in the first embodiment having the structures of FIGS. 5A and 5B.

FIG. 6B is a timing diagram of a drive signal illustrating a method of resolving a timing mismatch of a drive signal during a repair operation in the first embodiment having the structure of FIG. 5A.

FIG. 6C is a timing diagram of a drive signal illustrating a method of resolving a timing mismatch of a drive signal during a repair operation in the second embodiment having the structure of FIG. 5B.

* Explanation of symbols for main parts of the drawings

10a to 10d: Cell array 12a to 12h: Fuse circuit

20: word line driver

21 <a> to 21 <p>: redundancy word line driver

30, 300: control circuit section 31a, 31b, 310a, 310b, 310c: bus line

32a to 32d, 320a to 320d: buffer circuit

33a to 33g, 330a to 330j: NAND gate

34a, 34b, 340: Noah gate 101: voltage pull-up part

102: fuse unit 103: voltage holding unit

104: fuse signal output unit 350, 360a to 360d: delay unit

rwl <0: 3>: Redundancy word line wl <0: n>: Normal word line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a word line driving signal generator for resolving a timing mismatch between a normal path and a redundancy path when a semiconductor memory is driven.

In general, when a defect occurs in any cell in the cell array, the semiconductor memory device includes a redundancy circuit that compensates the defect by replacing the defective cell with a redundant memory cell. Specifically, when an address for selecting a defective memory cell is specified, the redundancy circuit enables the word line connected to the redundant memory cell instead of the defective memory cell.

1 is a block diagram schematically illustrating a semiconductor memory device for explaining a repair operation.

As shown in FIG. 1, the semiconductor memory device includes cell arrays 10a to 10d and a fuse circuit 12. In this case, each of the cell arrays 10a to 10d includes normal cells and a repair cell, the normal cells are connected to normal word lines wl <0> to wl <n>, and the repair cells are connected to the redundancy word line rwl <. 0: 3>). The fuse circuit 12 is formed to correspond to the redundancy word lines rwl <0: 3>, respectively.

When the semiconductor memory device is configured in such a manner that an address corresponding to a bad memory cell is programmed in a fuse cutting method in a fuse circuit, the fuse circuit 12 programmed in place of the original word line at the input of the address corresponding to the bad cell may be used. ), The redundancy word lines rwl <0: 3> are selected.

2 is a circuit diagram illustrating a word line driving signal generator of a semiconductor memory device according to the prior art.

Referring to FIG. 2, each of the first to eighth fuse circuits 12a to 12h programs an address corresponding to a defect in a normal cell. A pre-coded input address Baxij and a word line disable signal wlcb applied from the first and second bus lines 31a and 31b are input to output a fuse signal. In addition, each of the first to fourth buffer circuits 32a to 32d may have a pre-coded input address Baxij applied to the first bus line 31a and an input address signal bsenp for selecting a block. ) And the word line disable signal wlcb applied from the second bus line 31b are buffered and output.

The first and fourth fuse circuits 12a to 12h receive the fuse signals output from the first to fourth NAND gates 33a to 33d as pairs of neighboring fuse signals and perform NAND logic operations to perform the first to fourth operations. The redundancy word line selection signals Xhit1 to Xhit4 are output. That is, the first NAND gate 33a receives the fuse signals output from the first and second fuse circuits 12a and 12b, respectively, and performs a NAND logic operation to output the first redundancy word line selection signal Xhit1. The second to fourth redundancy word line selection signals Xhit2 to Xhit4 are also generated by the second to fourth NAND gates 33b to 33d similarly to the first redundancy word line selection signal Xhit1.

The first to fourth redundancy word line selection signals Xhit1 to Xhit4 are output from the first and second NOR gates 34a and 34b in pairs, respectively, and are NOR logically operated. That is, the first NOR gate 34a receives the first redundancy word line selection signal Xhit1 and the second redundancy word line selection signal Xhit2 and performs NOR logic operation. The second NOR gate 34b receives a third redundancy word line selection signal Xhit3 and a fourth redundancy word line selection signal Xhit4 and performs NOR logic operation.

Subsequently, the output signals logically operated by the first and second NOR gates 34a and 34b are inputted from the fifth and sixth NAND gates 33e and 33f, respectively, and are output by performing NAND logic operations to output the fifth and sixth NAND gates. An output signal logically operated at (33e) (33f) is input from the seventh NAND gate 33g to perform NAND logic operation to output the coded signal nre.

Then, the input address Baxij and the word line disable signal wlcb output from the first to fourth buffer circuits 32a to 32d and the coding signal nre output from the seventh NAND gate 33g are then output. ) Are input to the first to fourth normal word line drivers 22a to 22d, respectively. Thus, the first to fourth normal word line drivers 22a to 22d generate driving signals for driving the normal word lines wl <0: n>.

That is, the first normal word line driver 22a disables the precoded input address Baxij and word line outputted through the coding signal nre of the seventh NAND gate 33g and the first buffer circuit 32a. A signal for driving the first cell array 10a is output according to the signal wlcb. Similarly to the first normal word line driver 22a, the second to fourth normal word line drivers 22b to 22d may also include the coded signal nre and the second to fourth buffer circuits of the seventh NAND gate 33g. Signals for driving the second to fourth cell arrays 10b to 10d are respectively output according to the precoded input address Baxij and the wordline disable signal wlcb output through the 32b to 32d.

Further, a precoded input address signal bsenp for selecting a block output from the first to fourth buffer circuits 32a to 32d, and a first output from the first to fourth NAND gates 33a to 33d. The fourth to fourth redundancy word line selection signals Xhit1 to Xhit4 are input to the first to fourth redundancy word line drivers 21 <a> to 21 <0>, respectively. Thus, the first to fourth redundancy word line drivers 21 <a> to 21 <0> generate driving signals for driving the redundancy word lines rwl <0: 3>.

That is, the first redundancy word line drivers 21 <a> to 21 <d> are output from the first redundancy word line selection signal Xhit1 and the first buffer circuit 32a output from the first NAND gate 33a. A signal for driving the redundancy word lines rwl <0: 3> is output according to the precoded input address bsenp and the word line disable signal wlcb for selecting a block to be used. The second to fourth redundancy word line drivers 21 <e> to 21 <0> are also similar to the first redundancy word line drivers 21 <a> to 21 <d>, and the second to fourth NAND gates 33b. To the second to fourth redundancy word line selection signals Xhit2 to Xhit4 output from the second to fourth signals, and the precoded input address bsenp for selecting the blocks output from the second to fourth buffer circuits 32b to 32d. And a signal for driving the redundancy word lines rwl <0: 3> according to the word line disable signal wlcb.

3 is a circuit diagram illustrating each of the first to eighth fuse circuits 12a to 12h of FIG. 2 in detail.

Referring to FIG. 3, each of the first to eighth fuse circuits 12a to 12h may include a voltage pull-up unit 101, a fuse unit 102, a voltage holding unit 103, and a fuse signal output unit 104. Include.

The voltage pull-up unit 101 is connected between the power supply voltage VDD and the node Q1 and implemented as a PMOS transistor that pulls up the voltage of the node Q1 at the time of precharging in response to the bank active signal BACK. The fuse 102 is turned on in response to the plurality of fuses F1 to F22 connected in series between the node Q1 and the ground voltage VSS and the address signal Baxij, respectively. It includes a plurality of NMOS transistors (N1 to N22) for pulling down or maintaining the voltage of the node q1 according to the state of (F1 to F22). The voltage holding unit 103 is connected between the node Q1 and the power supply voltage VDD and responds to the output signal of the inverter I1 inverting the signal of the node Q1 and the power supply voltage ( And a PMOS transistor P1 for connecting or disconnecting VDD). The fuse signal output unit 104 performs a NAND logic operation on a signal TS based on the signal of the node Q2 and the test signal TM_XYRST, and outputs a NAND gate ND1 for outputting a fuse signal, and the test signal TM_XYRST. A plurality of inverters I2 to I4 for inverting and outputting the signal TS to the NAND gate ND1 are included.

As such, the first to eighth fuse circuits 12a to 12h cut the fuses corresponding to the specific address to be repaired, and output the low level fuse signal only when the corresponding address is applied.

The operation of the word line driving signal generator of the semiconductor memory device according to the related art constructed as described above is as follows. The word line disable signal wlcb becomes high by the active signal and becomes low by the precharge signal.

4A is a timing diagram of a driving signal during normal operation in the word line driving signal generator of the semiconductor memory device having the structure of FIG. 2, and FIG. 4B is a word line driving signal of the semiconductor memory device having the structure of FIG. 2. A timing diagram of a drive signal during a repair operation in the generator.

In the normal operation, as shown in FIG. 4A, when the input address Baxij precoded by the active signal becomes high, the output signal nre of the seventh NAND gate 33g serving as a repair detection signal is repaired. Becomes high. Accordingly, as the first to fourth normal word line driving circuits 22a to 22d are driven, the normal word lines wl <0: n> of the cell arrays 10a to 10d are enabled and redundancy word lines are provided. (rwl <0: 3>) will be disabled.

In addition, during the repair operation, as shown in FIG. 4B, the precoded address signal bsenp for block selection precoded by the active signal becomes high, and in response to the wordline disable signal wlcb, the precoded address signal bsenp becomes high. The output signal Xhit of the first to fourth NAND gates 33a to 33d becomes high. Accordingly, the normal word lines wl <0: n> of the cell arrays 10a to 10d are disabled and the redundancy word lines rwl <0: 3> are enabled so that the redundancy word lines rwl <0. The sense amplifier array 38 corresponding to (3>) is operated.

However, as shown in FIGS. 4A and 4B, there is a difference between a pass step in which normal word lines in the normal operation are enabled and a pass step in which redundancy word lines in the repair operation are enabled.

That is, in the normal operation, when the active signal is applied, first respond to the word line disable signal wlcb, and then respond to the input address Baxij obtained by precoding and the address signal bsenp for block selection. Next, the normal word lines wl <0: n> are enabled in response to the repair status detection signal nre.

On the other hand, in the case of a repair operation, when an active signal is applied, first, in response to the word line disable signal wlcb, the redundancy is immediately performed in response to the coding signal Xhit obtained by coding the fuse signal output through the fuse circuit. Word lines rwl <0: 3> are enabled.

In addition, as shown in FIG. 2, the coding signal Xhit for enabling the redundancy word lines rwl <0: 3> is generated at a fast time in response to the word line disable signal wlcb, but is normal. The repair status detection signal nre for enabling the word lines wl <0: n> is generated after many logic operations.

Accordingly, in the case of a memory device, when a defective memory cell is generated and some of the normal word lines are selected and some of the redundancy word lines are selected, the timing at which data is loaded on the word lines may be different from each other. The problem of mismatches with each other arises.

Furthermore, in the case of the graphic memory, each bank is divided so that circuits for selecting the divided banks are divided separately. In this case, data of each bank is placed on the next word line. Can show a greater difference in timing, with greater room for mismatch.

Therefore, in order to solve this problem, the timing of each other has been adjusted by referring to the normal word line in the neighboring position where there is no defect, but for this purpose, it is necessary to share each signal, and thus enable signals generated from each fuse. A circuit for is added, which causes various problems in the fabrication of the device.

As a result, the latest devices eliminate waste of resources caused by sharing signals between neighboring normal cells and unnecessary space waste due to device miniaturization in areas where bottlenecks of net die issues are caused. What is needed is a way to reduce as much as possible.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a device for generating a word line driving signal of a semiconductor memory device capable of resolving a timing mismatch between a path during a normal operation and a path during a repair operation.

Another object of the present invention is to provide a device for generating a word line driving signal of a semiconductor memory device capable of reducing a space due to signal sharing generated to solve a timing mismatch between a path during a normal operation and a path during a repair operation.

A feature of a word line driving signal generator of a semiconductor memory device according to the present invention for achieving the above object is to receive a precoded input address Baxij and a word line disable signal wlcb to output a fuse signal. A plurality of fuse circuits and a redundancy word line selection signal Xhit generated by logically combining the fuse signals are output to a redundancy word line driver, and a repair detection signal nxe generated by logically combining the fuse signals is normal. And a first delay unit for outputting the logical combination unit to the word line driver and a redundancy word line driver to delay the input address signal bsenp for block selection for a predetermined time.
The method may further include a plurality of buffer circuits configured to buffer the precoded input address Baxij and the word line disable signal wlcb and output the buffers to the normal word line driver and the redundancy word line driver.

Preferably, the logic combination unit generates a redundancy word line selection signal Xhit and outputs the redundancy word line driver to the redundancy word line driver, and generates the repair presence detection signal nxe to output the redundancy word line selection signal Xhit to the normal word line driver. It characterized in that it comprises a second logic circuit portion.

Preferably, the first delay unit delays the input address signal bsenp for the block selection until after the repair status detection signal nxe pulses from low to high.

Another feature of the word line driving signal generator of a semiconductor memory device according to the present invention for achieving the above object is to output a fuse signal by receiving the pre-coded input address (Baxij) and the word line disable signal (wlcb) And a plurality of fuse circuits to generate a redundancy word line selection signal Xhit by logically combining the fuse signals and outputting a repair status detection signal nxe generated by logically combining the fuse signals to a normal word line driver. And a logic delay unit and a second delay unit which delays the generated redundancy word line selection signal Xhit by a predetermined time and supplies the redundancy word line driver.
The method may further include a plurality of buffer circuits configured to buffer the precoded input address Baxij and the word line disable signal wlcb and output the buffers to the normal word line driver and the redundancy word line driver.

Preferably, the logic combining unit generates the redundancy word line selection signal Xhit and outputs the redundancy word line selection signal Xhit to the second delay unit, and generates the repair status detection signal nxe and outputs the repaired word detection signal nxe to the normal word line driver. And a second logic circuit portion.

Preferably, the second delay unit delays the redundancy word line selection signal Xhit until the repair status detection signal nxe is pulsed from low to high.

delete

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of a word line driving signal generator of a semiconductor memory device for solving timing mismatches between a normal pass and a redundancy pass according to the present invention will be described with reference to the accompanying drawings. Prior to this, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only the present embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art the true scope of the invention, the true technical protection scope of the present invention in the technical spirit of the claims Should be decided by

First Example

5A is a circuit diagram illustrating a word line driving signal generator of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 5A, the semiconductor memory device according to the first embodiment may include cell arrays having a plurality of normal word lines wl <0: n> and redundancy word lines rwl <0: 3>. 10a to 10d, the normal word line drivers 22a to 22d for driving the plurality of normal word lines wl <0: n>, and the driving of the plurality of redundancy word lines rwl <0: 3>. The redundancy word line drivers 21 <a> to 21 <p> and the redundancy word line drivers 21 <a> to 21 <p> by delaying the pulse conversion timing of the address signal bsenp for block selection. It includes a control circuit unit 300 for controlling the operation.

In this case, the cell arrays 10a to 10d and the word line driver 20 are the same as the conventional configuration described with reference to FIG. 2. Therefore, the same reference numerals are used, and a description thereof will be omitted.

The control circuit unit 300 includes first to eighth fuse circuits 12a to 12h, first to fourth buffer circuits 320a to 320d, a plurality of NAND gates 330a to 330j, and a noah gate 340. ) And a first delay unit 350. In addition, the control circuit unit 300 includes first to third bus lines 310a to 310c, and a pre-coded input address Baxij is applied to the first bus line 310a. A word line disable signal wlcb is applied to the second bus line 310b, and an input address bsenp for selecting a block is applied to the third busline 310c.

Each of the first to eighth fuse circuits 12a to 12h programs an address corresponding to a failure of the normal cell. A pre-coded input address Baxij and a word line disable signal wlcb applied from the first and second bus lines 31a and 31b are input to output a fuse signal. In addition, the first to fourth buffer circuits 320a to 320d may have pre-coded input addresses Baxij and wordline disable applied from the first and second bus lines 310a and 310b. ) Signal wlcb is buffered to the input and output.

Then, the first to fourth NAND gates 330a to 330d form two consecutive fuse circuits for each of the cell arrays, and receive NAND logic operations of the fuse signals of the connected fuse circuits, respectively, to perform the first to fourth operations. The redundancy word line selection signals Xhit1 to Xhit4 are output.

That is, the first NAND gate 330a performs NAND logic operation on the fuse signal of the first fuse circuit 12a and the fuse signal of the second fuse circuit 12b to output the first redundancy word line selection signal Xhit1. The second NAND gate 330b performs a NAND logic operation on the fuse signal of the third fuse circuit 12c and the fuse signal of the fourth fuse circuit 12d to output the second redundancy word line selection signal Xhit2. The third NAND gate 330c performs a NAND logic operation on the fuse signal of the fifth fuse circuit 12e and the fuse signal of the sixth fuse circuit 12f to output a third redundancy word line selection signal Xhit3. The fourth NAND gate 330d performs a NAND logic operation on the fuse signal of the seventh fuse circuit 12g and the fuse signal of the eighth fuse circuit 12h.

Subsequently, the fifth to eighth NAND gates 330e to 330h configure two even or odd-numbered fuse circuits for each of the cell arrays, and receive NAND logic operations by receiving fuse signals of the connected fuse circuits.

That is, the fifth NAND gate 330e performs NAND logic operation on the fuse signal of the first fuse circuit 12a and the fuse signal of the third fuse circuit 12c. The sixth NAND gate 330f performs NAND logic operation on the fuse signal of the second fuse circuit 12b and the fuse signal of the fourth fuse circuit 12d. The seventh NAND gate 330g performs NAND logic operation on the fuse signal of the fifth fuse circuit 12e and the fuse signal of the seventh fuse circuit 12g. The eighth NAND gate 330h performs a NAND logic operation on the fuse signal of the sixth fuse circuit 12f and the fuse signal of the eighth fuse circuit 12h.

Next, the ninth NAND gate 330i performs a logic operation on the output signals of even-numbered fuse circuits among the fifth to eighth NAND gates as inputs. That is, NAND logic operation is performed on the output signal of the fifth NAND gate 330e and the output signal of the seventh NAND gate 330g.

Subsequently, the tenth NAND gate 330j performs logic operation on the output signals of odd-numbered fuse circuits among the fifth to eighth NAND gates as inputs. That is, NAND logic operation is performed on the output signal of the sixth NAND gate 330f and the output signal of the eighth NAND gate 330h.

The NOR gate 340 logically operates the output signals of the ninth NAND gate 330i and the tenth NAND gate 330j as inputs, and outputs a coded signal nxe.

In addition, the first delay unit 350 outputs an input address signal bsenp 'delayed by a predetermined time from the input address signal bsenp for selecting a block applied to the third bus line 310c.

Then, the normal word line drivers 22a to 22d may include the input address Baxij and the word line disable signal wlcb buffered in the buffer circuits 320a to 320d in the control circuit unit 300, and the control circuit unit ( The coded signal nxe output from the NOR gate 340 in the 300 is input to output a driving signal for driving the plurality of normal word lines wl <0: n>.

That is, the first normal word line driver 22a is connected to the input address Baxij and the word line disable signal wlcb buffered through the output signal nxe of the NOR gate 340 and the first buffer circuit 320a. Accordingly, a signal for driving the first cell array 10a is output. Similarly to the first normal word line driver 22a, the second to fourth normal word line drivers 22b to 22d may also output the output signal of the NOR gate 340 and the second to fourth buffer circuits 320b to 320d. A signal for driving the second to fourth cell arrays 10b to 10d is output based on the buffered input address Baxij and the word line disable signal wlcb.

In addition, the redundancy word line drivers 21 <a> to 21 <p> may include a word line disable signal wlcb buffered by the buffer circuits 320a to 320d in the control circuit unit 300, and first to fourth NAND gates. The first to fourth redundancy word line selection signals Xhit1 to Xhit4 output from 330a to 330d and the delayed input address signal bsenp 'for selecting a block output from the first delay unit 350 are input. And outputs a driving signal for driving a plurality of redundancy word lines rwl <0: 3>.

That is, the first redundancy word line driver 21 <a> to 21 <d> is buffered through the first redundancy word line selection signal Xhit1 and the first buffer circuit 320a of the first NAND gate 330a. The redundancy word line rwl <included in the first cell array 10a according to the selected word line disable signal wlcb and an input address bsenp 'for selecting a block output from the first delay unit 350. 0: 3>) to output a signal to drive. The second to fourth redundancy word line drivers 21 <e> to 21 <0> are also similar to the first redundancy word line drivers 21 <a> to 21 <d>, and the second to fourth NAND gates 330b. Through the second to fourth redundancy word line selection signals Xhit2 to Xhit4, the second to fourth buffer circuits 320b to 320d, and the first delay unit 350 buffered through the second to fourth buffer circuits 320b to 320d. Outputs a signal for driving the redundancy word lines rwl <0: 3> included in the second to fourth cell arrays 10b to 10d according to an input address bsenp 'for selecting a block output from do.

Each of the first to eighth fuse circuits 12a to 12h in the control circuit unit 300 includes a voltage pull-up unit 101, a fuse unit 102, a voltage holding unit 103, and a fuse signal output as shown in FIG. 3. The fuse 104 may include a fuse corresponding to a specific address to be repaired and output a low level fuse signal only when the corresponding address is applied. Detailed description of the fuse circuit having such a structure and operation has been described above, and thus will be omitted. In addition, the structure of such a fuse circuit is not limited to this structure as one embodiment.

Referring to the operation of the word line driving signal generator of the semiconductor memory device according to an embodiment of the present invention configured as described above are as follows. In this case, the word line disable signal wlcb becomes high by the active signal and becomes low by the precharge signal.

6A is a timing diagram of a driving signal during normal operation in a word line driving signal generator of the semiconductor memory device having the structure of FIG. 5A, and FIG. 6B is a repair diagram in the first embodiment having the structure of FIG. 5A. ) Is a timing diagram of a drive signal showing a method of solving a timing mismatch of a drive signal during operation.

First, in the normal operation, as shown in FIG. 6A, when the input address Baxij precoded by the active signal becomes high, the output signal nxe of the noah gate 340 which is a repair detection signal is changed. Goes high. Accordingly, as the first to fourth normal word line driving circuits 22a to 22d are driven, the normal word lines wl <0: n> of the cell arrays 10a to 10d are enabled and redundancy word lines are provided. (rwl <0: 3>) will be disabled.

In addition, in the repair operation, as shown in FIG. 6B, the word line disable signal wlcb becomes high due to the active signal, and in response to the redundancy word line selection of the first to fourth NAND gates 330a to 330d. The signal Xhit goes high. In addition, an address signal bsenp for selecting a block applied high by the active signal is applied as a signal bsenp 'delayed by a predetermined time A through the delay unit 350. The redundancy word lines rwl <0: 3> are enabled in response to the time when the delayed signal bsenp 'is applied from low to high. Meanwhile, normal word lines wl <0: n> of the cell arrays 10a to 10d are disabled.

Thus, by delaying the pulse conversion time point at which the address signal bsenp for block selection for word line driving is changed from low to high through the first delay unit 350, the predetermined time A is delayed. The mismatch between the word line pass and the redundancy word line pass is resolved. At this time, the delay time A of the pulse conversion through the first delay unit 350 is a pulse conversion from low to high when the repair detection signal nxe output from the Noah gate 340 of FIG. 5A is normal. It is desirable to delay until after that point.

In addition, by delaying the pulse conversion time of the address signal bsenp for block selection by a predetermined time A, the timing mismatch between the word line of the normal path and the redundancy path is solved, and the bank selection signal bsenp is converted into a word. By directly applying to the line driver 20, the waste space according to the signal sharing of the conventional structure is solved.

2nd Example

5B is a circuit diagram illustrating a word line driving signal generator of a semiconductor memory device according to a second embodiment of the present invention.

Referring to FIG. 5B, the semiconductor memory device according to the second embodiment may include cell arrays having a plurality of normal word lines wl <0: n> and redundancy word lines rwl <0: 3>. 10a to 10d, the normal word line drivers 22a to 22d for driving the plurality of normal word lines wl <0: n>, and the driving of the plurality of redundancy word lines rwl <0: 3>. The control circuit unit 300 for controlling the operation of the word line driver 20 by delaying the pulse conversion timing of the redundancy word line driver 21 <a> to 21 <p> and the redundancy word line selection signal Xhit. It includes.

In this case, since the cell arrays 10a to 10d and the word line driver 20 are the same as those of the conventional configuration described with reference to FIG. 2, detailed description thereof will be omitted with the same reference numerals.

The control circuit unit 300 includes first to eighth fuse circuits 12a to 12h, first to fourth buffer circuits 320a to 320d, a plurality of NAND gates 330a to 330j, and a noah gate 340. ) And second to fifth delay units 360a to 360d. In addition, the control circuit unit 300 includes first to third bus lines, and the first bus line is supplied with a pre-coded input address Baxij, and the second bus line is word line disabled. (disable) signal wlcb is applied, and the third bus line is applied with an input address bsenp for selecting a block.

Thus, the first to eighth fuse circuits 12a to 12h program an address corresponding to a defect in the normal cell. A pre-coded input address Baxij and a word line disable signal wlcb applied from the first and second bus lines 31a and 31b are input to output a fuse signal. In addition, the first to fourth buffer circuits 320a to 320d may have pre-coded input addresses Baxij and wordline disable applied from the first and second bus lines 310a and 310b. ) Signal wlcb is buffered to the input and output.

Then, the first to fourth NAND gates 330a to 330d constitute two continuous fuse circuits for each of the cell arrays 10a to 10d, and receive NAND logic operations by inputting fuse signals of the connected fuse circuits, respectively. The first to fourth redundancy word line selection signals Xhit1 to Xhit4 are output. The second to fifth delay units 360a to 360d receive the output first to fourth redundancy word line selection signals Xhit1 to Xhit4, respectively, and the fifth to eighth redundancy word line selection signals Xhit1 that are delayed by a predetermined time. 'To Xhit4').

That is, the first NAND gate 330a performs a NAND logic operation on the fuse signal of the first fuse circuit 12a and the fuse signal of the second fuse circuit 12b, and then delays the predetermined time through the second delay unit 360a. The fifth redundancy word line selection signal Xhit1 'is output. The second NAND gate 330b performs a NAND logic operation on the fuse signal of the third fuse circuit 12c and the fuse signal of the fourth fuse circuit 12d and then delays the predetermined time by a third delay unit 360b. 6 The redundancy word line selection signal Xhit2 'is output. The third NAND gate 330c performs a NAND logic operation on the fuse signal of the fifth fuse circuit 12e and the fuse signal of the sixth fuse circuit 12f, and then delays the predetermined time by the fourth delay unit 360c. 7 The redundancy word line select signal Xhit3 'is output. The fourth NAND gate 330d performs a NAND logic operation on the fuse signal of the seventh fuse circuit 12g and the fuse signal of the eighth fuse circuit 12h, and then delays the predetermined time by the fifth delay unit 360d. 8 A redundancy word line select signal Xhit4 'is output.

Subsequently, the fifth to eighth NAND gates 330e to 330h configure two even or odd-numbered fuse circuits for each of the cell arrays, and receive NAND logic operations by receiving fuse signals of the connected fuse circuits.

That is, the fifth NAND gate 330e performs NAND logic operation on the fuse signal of the first fuse circuit 12a and the fuse signal of the third fuse circuit 12c. The sixth NAND gate 330f performs NAND logic operation on the fuse signal of the second fuse circuit 12b and the fuse signal of the fourth fuse circuit 12d. The seventh NAND gate 330g performs a NAND logic operation on the fuse signal of the fifth fuse circuit 12e and the fuse signal of the seventh fuse circuit 12g. The eighth NAND gate 330h performs a NAND logic operation on the fuse signal of the sixth fuse circuit 12f and the fuse signal of the eighth fuse circuit 12h.

Next, the ninth NAND gate 330i performs logical operation on the output signals of the even-numbered fuse circuits among the fifth to eighth NAND gates 330e to 330h as inputs. That is, NAND logic operation is performed on the output signal of the fifth NAND gate 330e and the output signal of the seventh NAND gate 330g.

Subsequently, the tenth NAND gate 330j performs logic operation on the output signals of the odd-numbered fuse circuits among the fifth to eighth NAND gates 330e to 330h as inputs. That is, NAND logic operation is performed on the output signal of the sixth NAND gate 330f and the output signal of the eighth NAND gate 330h.

The NOR gate 340 logically operates the output signals of the ninth NAND gate 330i and the tenth NAND gate 330j as inputs, and outputs a coded signal nxe.

Then, the normal word line drivers 22a to 22d may include the input address Baxij and the word line disable signal wlcb buffered in the buffer circuits 320a to 320d in the control circuit unit 300, and the control circuit unit ( The coded signal nxe output from the NOR gate 340 in the 300 is input to output a driving signal for driving the plurality of normal word lines wl <0: n>.

That is, the first normal word line driver 22a may include the input address Baxij and the word line disable signal wlcb buffered through the coding signal nxe of the NOR gate 340 and the first buffer circuit 320a. As a result, a signal for driving the first cell array 10a is output. Similarly to the first normal word line driver 22a, the second to fourth normal word line drivers 22b to 22d also have a coding signal nxe and a second to fourth buffer circuit 320b to the noah gate 340. A signal for driving the second to fourth cell arrays 10b to 10d is output according to the buffered input address Baxij and the word line disable signal wlcb through 320d.

In addition, the redundancy word line drivers 21 <a> to 21 <p> may include a word line disable signal wlcb buffered by the buffer circuits 320a to 320d in the control circuit unit 300, and second to fifth delay units. A plurality of redundant word lines are received by receiving the delayed redundancy word line selection signal Xhit 'output from 360a to 360d and an input address signal bsenp for selecting a block applied to the third bus line 310c. rwl <0: 3> is outputted.

That is, the first redundancy word line drivers 21 <a> to 21 <d> may include a delayed fifth redundancy word line selection signal Xhit1 'which is an output signal of the second delay unit 360a, and a first buffer circuit. The cell included in the first cell array 10a according to the word line disable signal wlcb buffered through 320a and the input address signal bsenp for selecting a block applied to the third bus line 310c. A signal for driving the redundancy word lines rwl <0: 3> is output. The second to fourth redundancy word line drivers 21 <e> to 21 <0> are also similar to the first redundancy word line drivers 21 <a> to 21 <d>, and the third to fifth delay units (eg Delayed fifth to eighth redundancy word line selection signals Xhit2 'to Xhit4', which are output signals of 360b to 360d, and wordline disable signals buffered through second to fourth buffer circuits 320b to 320d. The redundancy word line rwl <0 included in the second to fourth cell arrays 10b to 10d according to wlcb and an input address signal bsenp for selecting a block applied to the third bus line 310c. : 3>) outputs a signal to drive.

Each of the first to eighth fuse circuits 12a to 12h in the control circuit unit 300 includes a voltage pull-up unit 101, a fuse unit 102, a voltage holding unit 103, and a fuse signal output as shown in FIG. 3. The fuse 104 may include a fuse corresponding to a specific address to be repaired and output a low level fuse signal only when the corresponding address is applied. Detailed description of the fuse circuit having such a structure and operation has been described above, and thus will be omitted. In addition, the structure of such a fuse circuit is not limited to this structure as one embodiment.

Referring to the operation of the word line driving signal generator of the semiconductor memory device according to an embodiment of the present invention configured as described above are as follows. In this case, the word line disable signal wlcb becomes high by the active signal and becomes low by the precharge signal.

FIG. 6A is a timing diagram of a driving signal during normal operation in the word line driving signal generator of the semiconductor memory device having the structure of FIG. 5B, and FIG. 6C is a repair diagram of the second embodiment having the structure of FIG. 5B. This is a timing diagram of a drive signal showing a method of solving a timing mismatch of a drive signal during a repair operation.

First, in the normal operation, as shown in FIG. 6A, when the input address Baxij precoded by the active signal becomes high, the output signal nxe of the noah gate 340 which is a repair detection signal is changed. Goes high. Therefore, as the first to fourth normal word line driving circuits 22a to 22d are driven, the normal word lines wl <0: n> of the cell arrays 10a to 10d are enabled and the redundancy word lines ( rwl <0: 3>) will be disabled.

In the repair operation, as shown in FIG. 6B, the address signal bsenp for block selection is made high by the active signal, and the first to fourth NAND gates in response to the word line disable signal wlcb are performed. The redundancy word line select signal Xhit of 330a to 330d becomes high. In addition, the redundancy word line selection signal X delay of the redundancy word line selection signals Xhit of the first to fourth NAND gates 330a to 330d is delayed by a predetermined time (A) through the first to fourth delay units 360a to 360d. Xhit ') is output to the redundancy word lines rwl <0: 3>.

Therefore, normal word lines wl <0: n> of the cell arrays 10a to 10d are disabled, and the redundancy word lines rwl <0: 3> are first through fourth delay units 360a through. It is enabled after the redundancy word line selection signal Xhit 'which is delayed by a predetermined time A through 360d. Meanwhile, normal word lines wl <0: n> of the cell arrays 10a to 10d are disabled.

As such, the delay time of the pulse conversion time at which the redundancy word line selection signal Xhit is changed from low to high is delayed by the delay unit 350 to thereby delay the word lines of the normal pass and the redundancy pass. It is trying to solve the mismatch between the livers. At this time, the delay time A of the pulse conversion through the first to fourth delay units 360a to 360d is low when the repair detection signal nxe output from the Noah gate 340 of FIG. 5A is normal. It is desirable to delay until after the time of the pulse conversion from to high.

In addition, by delaying the pulse conversion time of the redundancy word line selection signal Xhit by a predetermined time A, the timing mismatch between the normal path and the word line of the redundancy pass is solved, and the bank selection signal bsenp is converted into a word. By directly applying to the line driver 20, the waste space according to the signal sharing of the conventional structure is solved.

The apparatus for driving a word line according to the present invention as described above has the following effects.

First, there is an effect of reducing the mismatch between the normal word line pass and the repair word line pass, and at the same time reducing the wasted space due to signal sharing.

Second, since it can be widely used in all products above SDRAM, it is unnecessary because of waste of resources and signal miniaturization due to signal sharing in the area where bottleneck of all applicable net die issues is a bottleneck. The space waste can be reduced as much as possible.

Claims (8)

A plurality of fuse circuits that receive the precoded input address Baxij and the word line disable signal wlcb and output a fuse signal; The redundancy word line selection signal Xhit generated by the logical combination of the fuse signals is output to the redundancy word line driver, and the repair condition detection signal nxe generated by the logical combination of the fuse signals is output to the normal word line driver. Logical combination, A first delay unit delaying an input address signal bsenp for block selection by a predetermined time and outputting the redundancy word line driver to the redundancy word line driver; And a plurality of buffer circuits for buffering the precoded input address Baxij and wordline disable signal wlcb and outputting the buffers to the normal wordline driver and the redundancy wordline driver. Line drive signal generator. delete The logic circuit of claim 1, wherein the logic combination unit generates a redundancy word line selection signal Xhit and outputs the redundancy word line selection signal to the redundancy word line driver. And a second logic circuit configured to generate the repair detection signal (nxe) and output the repaired detection signal (nxe) to the normal word line driver. The method of claim 1, Wherein the first delay unit delays the input address signal bsenp for the block selection until after the repair detection signal nxe is pulse-transformed from low to high. Device. A plurality of fuse circuits that receive the precoded input address Baxij and the word line disable signal wlcb and output a fuse signal; A logic combination unit generating a redundancy word line selection signal Xhit by logically combining the fuse signals and outputting a repair detection signal nxe generated by logically combining the fuse signals to a normal word line driver; A second delay unit which delays the generated redundancy word line selection signal Xhit by a predetermined time and supplies the redundancy word line driver to the redundancy word line driver; And a plurality of buffer circuits for buffering the precoded input address Baxij and wordline disable signal wlcb and outputting the buffers to the normal wordline driver and the redundancy wordline driver. Line drive signal generator. delete 6. The logic circuit of claim 5, wherein the logic combiner comprises: a first logic circuit unit configured to generate the redundancy word line select signal Xhit and to output the second delay unit; And a second logic circuit configured to generate the repair detection signal (nxe) and output the repaired detection signal (nxe) to the normal word line driver. The method of claim 5, And the second delay unit delays the redundancy word line selection signal (Xhit) until after the repair status detection signal (nxe) is pulsed from low to high.

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