KR100855425B1 - Semiconductor laser device, and fabrication method of the device - Google Patents

Abstract

 On the semiconductor substrate 102, for trapping light in the horizontal and horizontal directions with the cladding layer 103 of the first conductivity type, the active layer 104, the first cladding layer 105 of the second conductivity type, and the like. In the cross-section perpendicular to the stripe direction of the ridge having a second cladding layer 108 of the second conductivity type of the ridge stripe shape and a current block layer 107 formed except at least a portion on the ridge, A first surface 118 extending downwardly from the top of the ridge substantially perpendicular to the surface of the semiconductor substrate, and substantially straight inclined downwardly toward the outside of the ridge at the ridge edge; It has the 2nd surface 119 which consists of an edge part inclined surface, The 1st surface and the 2nd surface are directly connected, or are connected through the 3rd intermediate surface, and the 2nd surface comprises the said 2nd cladding layer. The ridge stripe type semiconductor laser device that is a semiconductor (111) is exposed. In the present invention, a high output semiconductor laser device having a high kink level and a low operating current can be provided.

Description

Semiconductor laser device and its manufacturing method {SEMICONDUCTOR LASER DEVICE, AND FABRICATION METHOD OF THE DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser device used as a light source for an optical disk device, an information processing device and the like and a manufacturing method thereof.

With the progress of high-density recording of optical discs such as DVDs, not only playback but also DVD drives for recording such as DVD-RAM and DVD-RW have been commercialized. And the speed of recording is on the rise in speed.

In response to such a high recording speed of recording DVD drives, the demand for higher output power of semiconductor lasers used as the light sources is increasing. Various proposals have been made as a means for increasing the output power of a semiconductor laser. One of the effective means is to form a ridge stripe having high verticality and symmetry by processing the cladding layer on the active layer. On the other hand, the high verticality and symmetry means that the angle formed by the ridge sidewall surface (side surface) in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge is almost perpendicular to the surface of the semiconductor substrate and has high symmetry. This means that the cross-sectional shape of the ridge is good symmetry. In addition, in this invention, the cross section perpendicular | vertical with respect to the ridge stripe direction means the cross section of the direction which traverses a ridge length direction at right angles.

The kink level, which becomes a problem of high output, is improved by improving the verticality and symmetry of the ridge shape in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge and making the current distribution shape and the light distribution shape equal. You can. In addition, by making the ridge top dimension almost equal to the bottom dimension, the thermal resistance at the time of current injection can be reduced and a low operating current can be realized.

However, for example, in the case of a visible light semiconductor laser having an oscillation wavelength of 650 nm, in order to suppress the formation of a natural superlattice (ordered structure) of the GaInP layer, an off angle in which the substrate orientation is inclined by about 10 ° from the (100) plane is used. It is common to use a semiconductor substrate having a ridge, and when a ridge stripe is formed using a wet etching technique, the ridge shape in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge becomes asymmetrical to the left and right reflecting the substrate off angle. . In the wet etching method, since the side etching amount of the cladding layer with respect to the etching mask is large, the ridge shape in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge becomes a trapezoidal shape having low verticality of the wall surface. In view of the above, it is very difficult to improve the asymmetry of the ridge shape and the verticality in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge.

In recent years, a technique has been proposed in which dry etching and wet etching are used together to form a ridge stripe, and the verticality and symmetry of the ridge shape in a cross section perpendicular to the longitudinal direction (stripe direction) of the ridge have been proposed (for example, See Japanese Laid-Open Patent Publication No. 2003-69154). Since dry etching is anisotropically etched, a ridge shape having improved verticality and symmetry in a cross section perpendicular to the longitudinal direction (stripe direction) of the ridge compared to the case of forming a re-terrain stripe by wet etching alone. Obtained. In addition, the damage layer formed by the plasma at the time of dry etching is removed by the wet etching after dry etching.

Moreover, in order to improve the perpendicularity and symmetry of the ridge shape in the cross section perpendicular | vertical to the longitudinal direction (stripe direction) of a ridge, the technique of forming a ridge stripe only by dry etching is proposed (for example, Unexamined-Japanese-Patent No. JP-A). 2000-294877). By this technique, a ridge shape having more improved symmetry and verticality in a cross section perpendicular to the longitudinal direction (stripe direction) of the ridge is obtained as compared with the case of forming a ridge stripe by using dry etching and wet etching together. Lose.

Here, the semiconductor laser device in the prior art shown in Examples 1 and 3 of JP 2003-69154 A and a manufacturing method thereof will be described with reference to FIGS. 3 and 4. 3 is a sectional view of the structure of the semiconductor laser devices of Examples 1 and 3 of JP-A-2003-69154, and FIG. 4 is a cross sectional view of the fabrication process, all of which show the manufacturing process, in a direction perpendicular to the longitudinal direction of the ridge stripe.

3 and 4A, an n-type AlGaAs cladding layer 303, an active layer 304 of a quantum well structure, a p-type AlGaAs cladding layer 305, and a p-type AlGaAs are formed on an n-type GaAs substrate 301. The etching stop layer 306, the p-type AlGaAs cladding layer 307, and the p-type GaAs cap layer 309 are sequentially epitaxially grown by the organometallic vapor phase growth method (hereinafter referred to as MOCVD method). The illustration of the layers corresponding to the n-type GaAs substrate 301, the n-type AlGaAs cladding layer 303, and the active layer 304 of the quantum well structure is omitted. Thereafter, a photoresist is applied on the surface of the p-type GaAs cap layer 309, and a ridge stripe pattern 313 of the photoresist is formed by photolithography technique.

Here, when fabricating an AlGaInP system red semiconductor laser device, a p-type intermediate layer (for example, a p-type GaInP intermediate layer) is deposited between the p-type cladding layer 307 and the p-type GaAs cap layer 309 (not shown).

The ridge stripe pattern 313 is made of a photoresist, but a dielectric such as Si0 ₂ may be used.

Next, as shown in FIG. 4B, the p-type GaAs cap layer 309 and the p-type cladding layer 307 are formed under the p-type cladding layer 307 using a dry etching technique. 306) to a position of 50 nm to 350 nm.

Next, as shown in FIG. 4C, wet etching is performed until the p-type etch stop layer 306 is reached, and the ridge stripe formed of the p-type AlGaAs cladding layer 307 and the p-type GaAs cap layer 309 is formed. Form.

Next, as shown in FIG. 4D, after removing the photoresist 313, the n-type current block layer 310 is deposited by MOCVD, and the p-type GaAs cap layer 309 of the current injection region by wet etching. ) Remove the current block layer on the surface. After that, the p-type GaAs contact layer 311 is again formed by MOCVD to complete the semiconductor laser wafer (see FIG. 3 for finished product).

Ridge shape with relatively improved verticality and symmetry in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge with respect to the AlGaAs infrared semiconductor laser device and the AlGaInP system red semiconductor laser device by the above-described manufacturing method. Is obtained. In addition, the etching depth control and the removal of the plasma damage layer during the dry etching can be achieved by wet etching.

Next, the semiconductor laser device in the prior art shown in Example 2 of Unexamined-Japanese-Patent No. 2003-69154, and its manufacturing method are demonstrated using FIG. 5, FIG. Fig. 5 is a structure of the semiconductor laser device according to Example 2 of JP-A-2003-69154, and Fig. 6 is a sectional view seen from a direction perpendicular to the longitudinal direction of each ridge stripe showing the manufacturing process.

5 and 6A, an n-type AlGaAs cladding layer 503, an active layer 504 having a quantum well structure, a p-type AlGaAs cladding layer 505, and p-type etching are formed on an n-type GaAs substrate 501. The stop layer 506, the p-type AlGaAs cladding layer 507, and the p-type GaAs cap layer 509 are sequentially epitaxially grown by the MOVPE method (in FIG. 6, the n-type GaAs substrate 501 of FIG. 5 and n). The illustration of the layer corresponding to the type AlGaAs cladding layer 503 and the active layer 504 of the quantum well structure is omitted). Thereafter, a dielectric such as Al ₂ O ₃ is deposited on the surface of the p-type GaAs cap layer 509, and a ridge stripe pattern 513 made of the dielectric such as Al ₂ O ₃ is used as a mask by photolithography. Form.

Here, the p-type etch stop layer 506 is a layer containing In having a band gap that does not absorb laser light, or a layer containing In having a layer thickness designed to obtain a quantum effect, for example, AlGaInP or GaInP. .

Next, as shown in FIG. 6B, dry etching is performed until the p-type AlGaAs clad layer 507 and the p-type GaAs cap layer 509 reach the p-type etch stop layer 506.

In dry etching, an inductively coupled plasma method (ICP method) is used. Since the p-type etching stop layer 506 uses a layer containing In, the etching rate is p-type AlGaAs cladding. Compared with the layer 507 and the p-type GaAs cap layer 509, it is significantly lowered. Therefore, in dry etching, it is supposed that the etching can be stopped by the etching stop layer 506.

Next, as shown in FIG. 6C, the mask of the ridge stripe pattern 513 made of a dielectric such as Al ₂ O ₃ is removed with a chemical solution containing fluoric acid as a main component, and then the current block layer 510 is removed by MOCVD. ). Subsequently, an unnecessary portion of the current block layer 510 grown on the ridge stripe is removed by a photolithography technique using a photoresist, and then the p-type GaAs contact layer 511 by the organometallic chemical vapor phase epitaxy method (hereinafter referred to as MOVPE method). ), And the semiconductor laser wafer is completed (refer to FIG. 5 for the finished product).

In dry etching, sputter, which is a physical phenomenon, is mainly used. Therefore, it is difficult to secure a sufficiently large selectivity that a sufficient difference in etching rate occurs depending on the material. However, in the above manufacturing method, dry etching is performed by using an etching stop layer containing In. It is said that the selectivity of is secured. As a result, the formation of ridges having high verticality and high symmetry only by dry etching.

Next, a semiconductor laser device and its manufacturing method in the prior art shown in Japanese Unexamined Patent Publication No. 2000-294877 will be described with reference to FIGS. Fig. 7 is a structure of the semiconductor laser device described in Japanese Laid-Open Patent Publication No. 2000-294877, and Fig. 8 is a sectional view seen from a direction perpendicular to the longitudinal direction of each of the ridge stripe showing the manufacturing process.

As shown in FIG. 7 and FIG. 8A, an n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P clad layer 703 and a GaInP / AlGaInP multi-quantum well structure on the n-type GaAs substrate 702 by MOCVD method. The active layer 704, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P cladding layer 707, the p-type GaInP hetero buffer layer 708, and the p-type GaAs cap layer 709 are sequentially epitaxially grown. Thereafter, a SiO ₂ film is formed over the entire surface of the substrate and the SiO ₂ stripe 713 is formed by photolithography.

Next, as shown in FIG. 8B, using a Si0 ₂ stripe 713 as a mask, p-type GaAs cap layer 709, p-type GaInP hetero buffer layer 708, and p-type (Al _0.7 ) using a dry etching technique. A portion of Ga _0.3 ) _0.5 In _0.5 P cladding layer 707 is etched to form a ridge stripe.

Next, as shown in FIG. 8C, the n-type AlInP current block layer 705 and the n-type GaAs current block layer 706 are sequentially epitaxially grown using the SiO ₂ stripe 713 as a mask by MOCVD.

Next, as shown in FIG. 8D, the SiO ₂ stripe 713 is removed, and the p-type GaAs contact layer 710 is grown on the entire substrate by MOCVD. Finally, the p-side electrode 711 and the n-side electrode 701 are formed to manufacture a semiconductor laser device.

By the above manufacturing method, a ridge stripe can be formed only by dry etching, and a ridge shape having high symmetry and verticality in a cross section perpendicular to the longitudinal direction (stripe direction) of the ridge is obtained.

To improve the kink level, the ridge shape in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge is required to be symmetrical with the semiconductor substrate facing downward. As a result, the difference between the carrier distribution shape and the light distribution shape is reduced, the hole burning phenomenon is suppressed, and the instability of the transverse mode due to the asymmetry of the ridge shape in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge is Resolved.

In addition, in the high power semiconductor laser device, the shape of the ridge sidewall surface is required to be perpendicular to the surface of the semiconductor substrate and to be a higher ridge stripe of ridge height. When the ridge height is low, the laser light widened from the active layer is absorbed by the p-type cap layer or the like, and therefore is likely to be connected to a decrease in characteristics such as an increase in the threshold current and a decrease in the differential quantum efficiency. Since the width of the ridge bottom portion not only regulates the current passage width but also the intensity of light confinement, the ridge stripe type semiconductor laser device is usually designed based on the width of the ridge bottom portion. If the ridge shape perpendicularity decreases, if the ridge height is increased while maintaining the width of the ridge bottom as designed, the width of the top surface of the ridge becomes narrow. That is, in the conventional process, since the ridge bottom surface has the same dimensions and becomes a trapezoidal shape (net mesa shape) in which the ridge top dimension is narrowed, the ridge top dimension is decreased, and the contact resistance with the p-side electrode is increased, and the threshold value is increased. This tends to lower the characteristics of the back. Therefore, in the high power semiconductor laser having a large expansion of light from the active layer, in order to avoid these problems, formation of a ridge stripe in which the width of the ridge top surface does not become narrow even with a high ridge height is required.

In addition, in order to improve the reliability, it is required to remove the damaged layer by plasma during dry etching. This is because if the damage caused by the plasma remains on the substrate, crystal defects are newly generated by the heat generated during the operation of the semiconductor laser and lead to element deterioration.

In the manufacturing methods described in Examples 1 and 3 of JP-A-2003-69154 shown in Figs. 3 and 4, the manufacturing method described in Figs. 3 and 4 is perpendicular to the longitudinal direction (stripe direction) of the ridge, as compared with the case formed only by the wet etching technique. In the cross section, a ridge shape having improved verticality and symmetry is obtained, but by wet etching for the purpose of etching depth control and plasma damage layer removal, side etching occurs in the ridge top portion, thereby degrading the verticality. In particular, in the AlGaInP-based red semiconductor laser device, since a semiconductor substrate having an off angle, specifically, a (100) plane whose surface is inclined in the direction, is used, as shown in FIG. The symmetry of the ridge shape in the cross section perpendicular to the longitudinal direction (stripe direction) is lowered.

In addition, the wet etching chemicals used in most cases etch only the p-type cladding layer 307 without etching the p-type GaAs cap layer 309. The p-type cladding layer 307 is made of AlGaAs for an AlGaAs infrared semiconductor laser device, and AlGaInP for an AlGaInP-based red semiconductor laser device. Therefore, as shown in FIG. 4C, only the ridge side surface of the p-type cladding layer 307 is selectively etched, and the upper portion of the p-type cladding layer 307 directly below the P-type GaAs cap layer 309 has a desired ridge top dimension. It becomes narrower and the overhang-shaped overhang in which the p-type GaAs cap layer 309 protruded is formed in the both sides of the ridge top part.

In the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge, when the n-type current block layer 310 is formed on the substrate having such a ridge shape, epitaxial growth that is overhanging is not completely completed, and a cavity is formed. In the subsequent steps, the cavity does not disappear but remains in the completed semiconductor laser device.

Such a cavity scatters oscillation light in a laser device, causes waveguide loss, and adversely affects device characteristics such as lowering of differential quantum efficiency and increasing threshold current or operating current.

In addition, in the production methods described in Examples 1 and 3 of JP-A-2003-69154, since the ridge top dimension is secured to a certain size, it is not possible to perform additional wet etching sufficient to expose a stable crystal plane. Therefore, since the ridge sidewall surface at the ridge edge is not exposed to a single crystal type that is stable like the (100) plane, but is exposed to a plurality of types of crystal planes, the curved surface of which the inclination angle is continuously changed as a whole becomes The ridge bottom dimension is increased with respect to the mask dimension. In the case of using a current block layer made of a semiconductor layer such as n-type AlInP, when epitaxially grown, the crystallinity of the n-type AlInP current block layer epitaxially grown is reduced at the ridge edge where the plurality of types of crystal planes are exposed. . The increase in the ridge dimension with respect to the mask dimension, the lowering of the crystallinity of the n-type AlInP current block layer, deteriorate device characteristics such as unevenness in the horizontal radiation angle of the laser light and an increase in the threshold current or the operating current.

Further, in the manufacturing methods described in Examples 1 and 3 of JP-A-2003-69154, the variation of the wet etching rate between the wafer surface and the wafer surface is large, so that a plurality of semiconductor laser devices are provided within one wafer surface. In the case of fabrication, and furthermore, the uniformity of the ridge dimensions between the semiconductor laser devices formed even among a plurality of wafers is difficult and causes a decrease in yield.

Subsequently, in the manufacturing method described in Example 2 of JP-A-2003-69154 shown in Figs. 5 and 6, since the ridge is formed only by dry etching, a ridge shape having high verticality and symmetry can be realized. Moreover, the controllability of etching depth is improved by using the etching stop layer containing In.

However, the removal of the damage layer by plasma during dry etching is not performed, and the problem of premature element deterioration due to damage residual by plasma is not improved. In addition, when the angle between the ridge side surface and the substrate surface is increased, when a dielectric film such as SiN or SiO _{2 is used} as the current block layer, a raw material for forming a dielectric film such as SiN or SiO _{2 at the} ridge edge by plasma CVD method or the like Since the gas is insufficient in supply and the deposition rate is locally decreased, the coverage of the current block layer at the ridge edge is reduced. On the other hand, when a semiconductor layer such as n-type AlInP is used as the current block layer, since a plurality of types of crystal surfaces are exposed on the ridge sidewall surface formed by anisotropic dry etching, epitaxial growth cannot be satisfactorily crystallized and the current block layer The crystallinity of is lowered. The near coverage of the emission position and the decrease in coverage of the SiN current block layer at the edge of the ridge which most affects the oscillation light, and the crystallinity deterioration of the n-type AlInP current block layer result in unevenness in the horizontal radiation angle of the laser light, It is connected to deterioration of device characteristics such as an increase in operating current.

In addition, when stress is generated between the current block layer and the semiconductor substrate, when the angle formed between the ridge side and the substrate surface at the lower end of the ridge is close to 90 degrees, the ridge side and the etching stop due to the impact applied when the laser chip is closed and opened. Stress is concentrated in the vicinity of the junction line of a layer, and a crack may arise in a ridge edge part from this part as a starting point. In connection with this, there exists a possibility that the performance of a laser element may fall.

In addition, the above manufacturing method is limited to the AlGaAs-based infrared semiconductor laser device, and cannot be applied to the AlGaInP-based red semiconductor laser device. In addition, when the GaInP etching stop layer of a thin film is crystal-grown on an AlGaAs cladding layer, control of composition, film thickness, lattice irregularity, and crystallinity fall are difficult, and stable production is difficult.

Subsequently, in the manufacturing method described in JP 2000-294877 shown in Figs. 7 and 8, in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge, only the dry etching is used for high vertical and high symmetry ridge. Although the shape is realized, the damage layer by plasma at the time of dry etching is not removed.

In addition, since the etching stop layer is not provided, the dry etching depth cannot be controlled, for example, when a plurality of semiconductor laser devices are produced in the wafer surface, or between a plurality of wafers on which semiconductor laser devices are formed. Ridge height uniformity between laser devices is lowered.

In addition, as in Example 2 of JP-A-2003-69154, the angle between the ridge sidewall surface and the substrate surface increases, so that when a dielectric film such as SiN or SiO _{2 is} applied to the current block layer, the ridge edge is similar to the above. In the case where a dielectric film such as SiN or SiO _{2 is} formed by plasma CVD or the like, the supply gas becomes insufficient and the film formation speed is locally decreased. Therefore, the coverage of the current block layer at the ridge edge is reduced and at the ridge edge There is a possibility that current leakage occurs. In addition, when a semiconductor layer such as n-type AlInP is used as the current block layer, a plurality of crystal surfaces are exposed on the ridge sidewall surface formed by anisotropic dry etching, so that epitaxial growth cannot be satisfactorily crystallized, and Crystallinity is lowered.

In addition, as in Example 2 of JP-A-2003-69154, the angle formed between the ridge sidewall surface and the substrate surface is large, and there is a risk of cracking at the ridge edge.

SUMMARY OF THE INVENTION In view of the above conventional problems, an object of the present invention is to provide a ridge stripe type semiconductor laser device having a ridge formation excellent in verticality and symmetry and having an improved output having a high kink level, and a method of manufacturing the same. In particular, the present invention provides a method for forming a ridge stripe using both dry etching and wet etching, wherein the sidewall protective layer is formed on the ridge sidewall after dry etching, and dry etching is performed by suppressing side etching of the ridge top during subsequent wet etching. It succeeds in realizing the formation of a highly vertical and highly symmetrical ridge without a damage layer by plasma at the same time, and the present invention also reduces the number of crystal surfaces exposed at the edge of the ridge during wet etching, thereby reducing the inclined surface of almost linear shape. By forming, stable stability of the ridge with small dimensional deviation, improvement of coverage at the ridge edge of the current block layer made of a dielectric film such as SiN or SiO ₂ , crystal at the ridge edge of the current block layer made of a semiconductor layer such as n-type AlInP Kink has high ridge formation superior in perpendicularity and symmetry by improving the property An object of the present invention is to provide a ridge stripe type semiconductor laser device having an improved output having a level and a method of manufacturing the same. Moreover, this invention adjusts the thickness of the side wall protective layer formed in the ridge side wall surface, and the side etching amount at the time of a wet etching, and manufactures several semiconductor laser apparatuses in one wafer surface, Furthermore, between several wafers An object of the present invention is to provide a manufacturing method for uniformly forming ridge dimensions between semiconductor laser devices to be formed without variation.

In order to achieve the above object, a ridge stripe type semiconductor laser device of the present invention comprises a cladding layer of a first conductivity type, an active layer, a first cladding layer of a second conductivity type, and an etching stop layer on a compound semiconductor substrate. A semiconductor laser device comprising a second cladding layer of a second conductivity type formed on a stripe ridge and a current block layer formed by excluding at least a portion of the ridge, in a cross-sectional shape perpendicular to the stripe direction of the ridge. A first surface extending downwardly from the top of the ridge as being substantially perpendicular to a surface of the semiconductor substrate, and a substantially straight edge inclined downwardly obliquely toward the outside of the ridge at the ridge edge; Has a second surface consisting of a partial inclined surface,

The first surface and the second surface,

(a) is directly connected,

(b) the first surface and the second surface are connected via a third intermediate surface, and the third intermediate surface is

(b1) a substantially straight step step surface that is substantially parallel to the surface of the semiconductor substrate and protrudes outside the ridge and has a length of 0.2 μm or less in the cross section;

or,

(b2) it is connected through a curved inclined intermediate surface protruding outwardly from the ridge obliquely downward and protruding in the ridge inward direction,

The second surface is a ridge stripe type semiconductor laser device in which the (111) surface of the semiconductor constituting the second clad layer is exposed.

Here, each of said 1st surface and 2nd surface is a substantially linear shape in ridge side shape. In other words, each of the two inclined surfaces is an inclined surface that is formed of a substantially flat surface, and when these first and second surfaces are directly connected, the connection portion between these two surfaces has a refractive point in the cross-sectional shape. In addition, when the first surface and the second surface are connected via the intermediate surface (step difference surface in this case), which is the third surface as in the above (b1), and the third surface is linear in the (b2). Also in the case of an inclined surface, each connection part has a refraction point in the said cross-sectional shape, and even when the 3rd surface is curved in (b2), the said 1st surface and the 2nd surface are linear flat surfaces. Therefore, the curved surface where the inclination of the inclined surface continuously changes as a whole, for example, the curved surface whose cross-sectional shape such as the side wall surface of the cladding layer 307 of FIG. 4C or 4D becomes a continuous curve is excluded.

In the ridge stripe type semiconductor laser device of the present invention, the (111) plane is preferably exposed to at least 50% or more of the second surfaces. In this way, the current block layer and the like can be epitaxially grown with good crystallinity, which is preferable.

Further, in the ridge stripe type semiconductor laser device of the present invention, in the cross-sectional shape perpendicular to the ridge stripe direction, the angle formed between the first surface and the surface of the semiconductor substrate is preferably 85 ° or more and 95 ° or less. In this case, in the cross-sectional shape perpendicular to the stripe direction of the ridge, the width of the vicinity of the ridge upper end portion is not too small compared with the width of the vicinity of the ridge lower end portion in the first surface, so that the contact resistance with the p-side electrode is increased. It can prevent that it raises, or the characteristics, such as a threshold value, fall. In addition, since the ridge height can be increased, the increase in the threshold current, the decrease in the differential quantum efficiency, and the like are prevented, and a high output semiconductor laser having a large expansion of light from the active layer is obtained.

Further, in the ridge stripe type semiconductor laser device of the present invention, in the cross-sectional shape perpendicular to the stripe direction of the ridge, the step step surface of (bl) in which the third intermediate surface protrudes outside the ridge is provided. When it has, it is preferable that the length of the step step surface substantially parallel to the said semiconductor substrate surface is below the layer thickness of the said current block layer. In this way, even when a method having poor coverage, for example, a sputtering method, is used when forming the current block layer, the coverage of the current block layer at the edge of the ridge does not significantly decrease, and current leakage in this portion can be prevented. It is preferable because of that.

In the ridge stripe type semiconductor laser device of the present invention, it is preferable that the surface orientation of the surface of the semiconductor substrate is a surface orientation inclined by a predetermined angle from the (100) plane. In this case, it is particularly preferable that the inclination direction of the (100) plane is the direction.

By doing in this way, formation of a natural superlattice can be suppressed and it is preferable.

On the other hand, the predetermined angle means an angle at which the natural superlattice is not formed when the first cladding layer is epitaxially grown on the semiconductor substrate (to grow the substrate and the crystal axis evenly), and is usually 5 ° or more and 20 °. The following is preferable.

Next, the manufacturing method of the ridge stripe type semiconductor laser device of the present invention includes a cladding layer of a first conductivity type, an active layer, a first cladding layer of a second conductivity type, an etching stop layer, and a compound semiconductor substrate. The second cladding layer of the second conductivity type is etched to the middle using a dry etching technique except for a step of sequentially forming a second cladding layer of the second conductivity type and a part of forming a stripe ridge. And a step of forming at least one sidewall protective layer on the ridge side formed by the dry etching, and when the second clad layer of the second conductivity type reaches the etching stop layer by using a wet etching technique. Further etching to form a stripe ridge having a ridge side formed by the dry etching and a ridge side formed by the wet etching, and removing the sidewall protective layer. And a step of forming a current block layer except at least a portion on the ridge, and the (111) plane of the semiconductor constituting the second clad layer on at least a portion of the ridge side in the wet etching process. It is a manufacturing method of the ridge stripe type semiconductor laser apparatus which is etched so that it may expose.

In the method of manufacturing the ridge stripe type semiconductor laser device of the present invention, in the wet etching step, the (111) plane is preferably exposed to at least 50% or more of the ridge side surfaces formed by the wet etching.

In this case, the side etching rate in the wet etching is lowered and stabilized by exposing the (111) surface by 50% or more, so that the variation in the etching rate due to the variation in the concentration or temperature of the chemical liquid used for the wet etching can be suppressed. This is preferable because the shape control of the ridge edge becomes easy.

On the other hand, in this case, it is preferable to wet-etch until the second surface becomes almost straight in cross-sectional shape so that the (111) surface is exposed almost to the entire surface of the second surface.

Moreover, in the manufacturing method of the ridge stripe type semiconductor laser device of this invention, in the cross section perpendicular | vertical to the stripe direction of the said ridge, (thickness of the said side wall protective layer) ≥ (the said 2nd conductivity type in the said wet etching process) Side etching amount of the second cladding layer). By specifying as described above, it is preferable because a high output semiconductor laser device having a large area of light from the active layer can be obtained because the resistance can be prevented from being etched to the inside of the ridge during wet etching to narrow the current path.

Moreover, in the manufacturing method of the ridge stripe type semiconductor laser device of this invention, it is preferable that the surface orientation of the surface of the said semiconductor substrate is the surface orientation inclined by predetermined angle from the (100) plane. In this case, it is particularly preferable that the inclination direction of the (100) plane is the direction.

By doing in this way, formation of a natural superlattice can be suppressed and it is preferable.

On the other hand, the predetermined angle means an angle at which the natural superlattice is not formed when the first cladding layer is epitaxially grown on the semiconductor substrate (to grow the substrate and the crystal axis evenly), and is usually 5 ° or more and 20 °. The following is preferable. The above reason will be described, for example, by epitaxially growing an AlGaInP-based semiconductor layer (AlP, GaP, InP mixed crystal semiconductor) in the form of a GaAs (100) substrate. A structure in which (AlP) and InP are periodically laminated is formed. When the natural superlattice is formed, the energy gap is reduced than in the normal state, and a problem such as that the wavelength of 650 nm of the red laser light oscillating becomes 685 nm occurs. In the mixed crystal semiconductor, the energy gap can be changed according to the composition ratio of components constituting the semiconductor. However, when a natural superlattice structure is formed, the energy gap change due to the crystal structure is predominant, and the composition ratio is changed. Even if you want to control the desired energy gap, that is, the desired oscillation wavelength, there is a drawback. Therefore, in order to prevent the formation of the natural superlattice, it is particularly preferable to use a substrate of the (100) plane in which the surface of the semiconductor substrate is inclined at a predetermined angle in the [011] direction.

In addition, the method of manufacturing the ridge stripe type semiconductor laser device of the present invention includes a clad layer of the first conductivity type, an active layer, and a compound semiconductor substrate having a surface orientation inclined at a predetermined angle from the (100) plane. Using a dry etching technique except for a step of sequentially forming a first cladding layer of the second conductivity type, an etching stop layer, and a second cladding layer of the second conductivity type, and a portion of forming a stripe ridge. And etching the second cladding layer of the second conductivity type to the middle thereof, and forming one or more layers of sidewall protective layers having different film thicknesses on both sides of the ridge on the ridge side of the ridge portion formed by the dry etching. And further etching the second cladding layer of the second conductivity type until reaching the etching stop layer by using a wet etching technique, and the ridge side formed by the dry etching and the wet side. A ridge stripe semiconductor comprising a step of forming a stripe ridge having a ridge side surface formed by etching, a step of removing the sidewall protective layer, and a step of forming a current block layer except at least a portion on the ridge. The manufacturing method of a laser device is mentioned.

Thus, by using the compound semiconductor substrate which makes surface orientation inclined a predetermined angle from the (100) plane, the formation of a natural superlattice can be suppressed, and it is preferable.

Further, in the method for manufacturing the ridge stripe type semiconductor laser device, in a cross section perpendicular to the stripe direction of the ridge, both sides of the ridge when the ridge is viewed from the direction of the ridge downward. It is preferable that the thickness of the side wall protective layer formed on the right side of the ridge is smaller than the thickness of the side wall protective layer formed on the left side of the ridge among the two side wall protective layers formed on the ridge.

By these methods, even if an inclined substrate having an off angle is used, the intermediate stepped step surface is made small, or the film thickness of the sidewall protective layer on both sides of the ridge is appropriately adjusted to the same thickness as the side etching amount by wet etching on each side. As a result, a ridge stripe in which no intermediate step step surface is formed can be formed. As a result, the change of the refractive index occurring in the vicinity of the junction between the intermediate step step surface and the second surface is suppressed, and the disturbance of the distribution of the laser light (NFP) which guides the inside of the resonator is small and the radiation shape of the laser light is reduced. It is preferable to be able to manufacture a stable ridge stripe type semiconductor laser device.

In the method for manufacturing the ridge stripe type semiconductor laser device, it is preferable to etch such that the (111) plane of the semiconductor constituting the second clad layer is exposed on at least a part of the side of the ridge in the wet etching step. .

In this case, since the side etching rate in wet etching decreases and stabilizes by exposing the (111) plane, the variation in etching rate due to the variation in the concentration or temperature of the chemical liquid used for wet etching can be suppressed, and the ridge It is preferable because the shape control of the edge portion becomes easy.

In the method for manufacturing the ridge stripe type semiconductor laser device, in the wet etching step, the (111) plane is preferably exposed to at least 50% or more of the ridge side surfaces formed by the wet etching.

In this case, since the side etching rate in wet etching is lowered and stabilized by exposing the (111) surface by 50% or more, the variation in etching rate due to the variation in the concentration or temperature of the chemical liquid used for wet etching can be suppressed. And the shape control of the ridge edge becomes easy.

In the method for manufacturing the ridge stripe type semiconductor laser device, in the cross section perpendicular to the stripe direction of the ridge, (the thickness of the thinner layer thickness among the two sidewall protective layers) ≥ (in the wet etching step) Side etching amount of the second cladding layer of the second conductivity type).

By doing so, the surface shape of the stepped step surface, which is substantially parallel to the surface of the semiconductor substrate and protrudes outside the ridge, can be stably formed in the wafer surface, or the layer thickness of the sidewall protective layer is thin. The shape (the shape which a 1st surface and a 2nd surface directly connect) in which the 3rd surface did not generate | occur | produce in the side wall side of the thickness side of the side can be stably formed in a wafer surface. In other words, it is preferable because the formation of a shape in which a substantially straight stepped step surface penetrates into the ridge can be prevented. The shape of the stepped stepped into the ridge inside is particularly prone to recesses in the ridge, which results in a narrow current path, an increase in resistance during laser operation, and the like.

In the method for manufacturing the ridge stripe type semiconductor laser device, it is preferable that the inclination direction of the (100) plane is the direction.

By doing in this way, formation of a natural superlattice can be suppressed and it is preferable.

According to the present invention as described above, it is possible to provide a ridge stripe-type semiconductor laser device having improved device characteristics such as uniform horizontal radiation angle of laser light, improvement of differential quantum efficiency, improvement of kink level, and a manufacturing method thereof. In addition, since the ridge stripe can be formed uniformly in the wafer surface and between the wafers, the yield can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows the structure of one Embodiment of the ridge stripe-type semiconductor laser apparatus of this invention.

FIG. 2A is a cross-sectional view showing the manufacturing process of the ridge stripe semiconductor laser device shown in FIG. 1 of the present invention. FIG.

FIG. 2B is a process partial view of a cross section perpendicular to the stripe direction of the ridge of the process of various other embodiments of the present invention, corresponding to the process of FIG. 2A (g).

FIG. 2C is a cross-sectional view of another embodiment of the present invention corresponding to the steps of FIGS. 2A to 2F.

FIG. 2D is a partially enlarged view of the ridge and its edge region in the step (c) of FIG. 2A.

FIG. 2E is a cross-sectional view of another embodiment of the present invention corresponding to the process subsequent to FIG. 2A (c).

FIG. 2F is a cross-sectional view of another embodiment of the present invention corresponding to the process subsequent to FIG. 2A (c).

FIG. 2G is a partially enlarged view of the ridge and its edge region in the step (t-1) of FIG. 2E.

FIG. 2H is a partially enlarged view of the ridge and its edge region in the step (u-1) of FIG. 2F.

FIG. 2I is a partially enlarged view of the ridge and its edge region in the step (t-5) of FIG. 2E.

FIG. 2J is a partially enlarged view of the ridge and its edge region in the step (u-5) of FIG. 2F.

FIG. 2K is a cross-sectional view of another embodiment of the present invention corresponding to the process subsequent to FIG. 2A (e).

3 is a cross-sectional view showing the structure of one embodiment of a conventional ridge stripe type semiconductor laser device.

4 is a cross-sectional view showing the manufacturing process of the conventional ridge stripe type semiconductor laser device shown in FIG. 3.

5 is a cross-sectional view showing the structure of one embodiment of a conventional ridge stripe type semiconductor laser device.

FIG. 6 is a cross-sectional view showing the manufacturing process of the conventional ridge stripe type semiconductor laser device shown in FIG.

7 is a cross-sectional view showing the structure of one embodiment of a conventional ridge stripe type semiconductor laser device.

FIG. 8 is a cross-sectional view showing the manufacturing process of the conventional ridge stripe semiconductor laser device shown in FIG.

<Description of the symbols for the main parts of the drawings>

101: n-side electrode

102: n-type GaAs substrate

103: n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P cladding layer

104: Ga _0.5 In _0.5 P active layer

105: p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P first cladding layer

106: p-type Ga _0.5 In _0.5 P Etch Stop Layer

107 n-type Al _0.5 In _0.5 P current block layer

108: p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer

109: p-type Ga _0.5 In _0.5 P intermediate layer

110: p-type GaAs contact layer

111: n-type GaAs cap layer

112: p-side electrode

113: SiO ₂ film

114: Si0 ₂ stripe

115: SiO ₂ film

116: SiO ₂ sidewall protective layer

116α: Si0 ₂ sidewall protective layer

116β: Si0 ₂ sidewall protective layer

116γ: Si0 ₂ sidewall protective layer

117 step step surface

118: first ridge side wall surface

119: second ridge side wall surface

120: angle between the ridge side and the semiconductor substrate

121: sidewall surface after the first dry etching

122: bottom surface after dry etching

123: side wall surface (flat shape) after the third dry etching

124: sidewall surface (curved shape) after the third dry etching

125: area near the ridge edge

126: area near the ridge edge

127: area near the ridge edge

128: Si0 ₂ film

129: SiO ₂ film

130: SiO ₂ sidewall protective layer

131: SiO ₂ sidewall protective layer

132: area near the ridge edge

133: area near the ridge edge

134: step step

135: second ridge side wall surface

136: step step

137: step step

138 n-type AlInP current block layer

139: n-type GaAs cap layer

140: p-side electrode

141: n-side electrode

142: sloped intermediate plane

145: resist pattern

146: first ridge side wall surface

147: second ridge side wall surface

148: n-type Al _0.5 In _0.5 P current block layer

149: n-type GaAs cap layer

150: p-side electrode

151: n-side electrode

152: third intermediate step step surface

301: n-type GaAs substrate

303 n-type cladding layer

304: active layer of quantum well structure

305 p-type first cladding layer

306: p-type etch stop layer

307 p-type cladding layer

309 p-type GaAs cap layer

310: n-type current block layer

311 p-type GaAs contact layer

313: Ridge Stripe Pattern

501 n-type GaAs substrate

503: n-type AlGaAs cladding layer

504: active layer of quantum well structure

505: p-type AlGaAs cladding layer

506 p-type etch stop layer

507 p-type AlGaAs cladding layer

509 p-type GaAs cap layer

510: current block layer

511 p-type GaAs contact layer

513: Ridge stripe pattern

514: SiN current block layer

701: n-side electrode

702: n-type GaAs substrate

703: n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P cladding layer

704 GaInP / AlGaInP multi quantum well structure active layer

705 n-type AlInP current block layer

706 n-type GaAs block layer

707: p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P cladding layer

708: p-type GaInP hetero buffer layer

709: p-type GaAs cap layer

710 p-type GaAs contact layer

711: p-side electrode

713: Si0 ₂ stripe

Next, embodiments of the present invention will be described in detail with reference to the drawings by using an AlGalnP ridge stripe type red semiconductor laser device. However, the following embodiments do not limit the present invention, and the present invention can be easily understood. In order to do so, the embodiment of the present invention is merely illustrated. The present invention is applicable to all ridge stripe type semiconductor laser devices.

(Embodiment 1)

Fig. 1 is a cross sectional view in a direction perpendicular to the stripe longitudinal direction of the ridge of the ridge stripe type semiconductor laser device according to the first embodiment, and Fig. 2A is the same cross sectional view showing the manufacturing process thereof. In the present invention, in the description of the semiconductor laser device, the upper, lower, upper, and lower sides of the semiconductor laser device are, for example, based on FIG. 1, from the lower side to the lower side of the side where the n-side electrode 101 is present. The side where the p-side electrode 112 is present is referred to as the reference from the upper side to the upper side. The same applies to the other drawings, and the upper part of the drawing is the upper side to the upper side in the description of the semiconductor laser device, and the lower side of the drawing is called the lower side to the lower side. In addition, unless otherwise indicated, all other figures are sectional drawing of the ridge perpendicular | vertical direction with respect to the stripe longitudinal direction.

First, as shown in Fig. 1 and Fig. 2A, on the n-type GaAs substrate 102 (400-500 µm in thickness), the n-type (Al ₀ ) is formed by MOCVD (organic metal vapor deposition). _{.7 Ga 0 .3) 0.5 In 0} .5 P cladding layer 103 (thickness _{1~2㎛), Ga 0 .5 In 0} .5 P active layer 104 (thickness 5~6㎚), p-type ( Al _0.7 Ga _0.3 ) _0.5 In _0.5 P first cladding layer 105 ( _{0.1 to 0.3} 탆 thick), p-type Ga _0.5 In _0.5 P etching stop layer 106 (thickness 8 to 12 nm), p Type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P Second cladding layer 108 (layer thickness 0.9-1.7 μm), p-type Ga _0.5 In _0.5 P intermediate layer 109 (thickness 40-60 nm) and p-type GaAs contact The layer 110 (0.1-0.3 micrometers in thickness) is formed one by one. Next, an SiO ₂ film 113 (thickness 0.2 to 0.6 탆) is formed on the p-type GaAs contact layer 110 by the sputtering method.

On the other hand, the n-type GaAs substrate 102 used is, for example, in the case of a visible light semiconductor laser having an oscillation wavelength of 650 nm, in order to suppress the formation of the natural superlattice (order structure) of the Ga _0.5 In _0.5 P layer, in order of 10 ° Although it is common to use the semiconductor substrate which has a so-called off angle which makes the surface of the (100) surface inclined moderately, in this invention, a substrate off angle can be used without a restriction | limiting in particular. That is, in the present invention, even if there is an inclination of the substrate off angle, the lateral symmetry of the ridge shape is almost maintained in the cross section perpendicular to the stripe direction of the ridge as described later. Formation can also be done without a problem.

The active layer 104 may be an active layer having a multi-quantum well structure having GaInP as a well layer and AlGaInP as a barrier layer.

The p-type Ga _0.5 In _0.5 P etching stop layer 106 may be an etching stop layer of a multi-quantum well structure having GaInP as a well layer and AlGaInP as a barrier layer.

In this case, the p-type Ga _0.5 In _0.5 P etching stop layer 106 may be a layer having a band gap that does not absorb laser light, or may be a layer having a layer thickness designed to obtain quantum effects, for example, using AlGaInP. Also good.

Next, the SiO ₂ film 113 of FIG. 2A is formed on the SiO ₂ stripe 114 by photolithography and dry etching techniques as shown in FIG. 2A (b).

Next, as shown in (c) of FIG. 2A, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 and the p-type Ga _0.5 In are formed using the SiO ₂ stripe 114 as a mask. _{The 0.5} P intermediate layer 109 and the p-type GaAs contact layer 110 are dry etched to the middle of the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108.

Here, the amount of dry etching is performed in the range of 65 to 95% of the ridge height, preferably in the range of 80% to 95%. If it is this range, the variation of the side etching amount by wet etching in the ridge edge part mentioned later can be suppressed. When the area of the first surface formed by dry etching is too small, and as a result, the area to be wet etched becomes too large, the etching amount variation greatly depends on the state (concentration, temperature, etc.) of the etching liquid, and the crystal plane described later This is because the influence of is not dominant. In addition, the said numerical range of the amount of dry etching and ridge height shows the relationship of the amount of dry etching in a ridge side part and ridge height here. That is, generally, as shown to (c) of FIG. 2A, the thickness of the part (namely, the edge part which spreads horizontally) remaining in the outer part rather than the remaining ridge of the 2nd cladding layer 108 is ridge. The part away from the side part tends to be thinner than the vicinity of the ridge side. Accordingly, the ridge height as a reference when the amount of dry etching is in the range of 65 to 95% of the ridge height is lower than the bottom (after dry etching bottom surface 122) from the upper end of the side wall surface 121 after the first dry etching. The vertical distance to the contact portion).

Moreover, as a method of obtaining such a desired dry etching amount, etching is performed while time-controlling stops, applying a monochromatic light to the surface of a board | substrate, and calculating etching residual thickness from the relationship of the interference intensity obtained by the reflected light and time, The method of stopping an etching when the desired film thickness reaches is mentioned.

As the dry etching technique suitably employed in the present invention, anisotropic plasma etching may be used. Examples of the dry etching include an inductively coupled plasma (ICP) or an electron cyclotron resonance (hereinafter ECR) plasma. The method etc. are mentioned. As the etching gas, a mixed gas of SiCl ₄ and Ar is used, but instead of the SiCl ₄ gas component, chlorine gas or boron trichloride gas may be used.

On the other hand, the dry etching technique used in Embodiment 1 is an ICP (Inductively Coupled Plasma) method, which uses a mixed gas of SiCl ₄ and Ar as an etching gas. As etching conditions, the volume content of SiCl _{4 in} the mixed gas is 5 to 12%, the temperature of the lower electrode on which the semiconductor substrate is provided is 150 to 200 ° C, the pressure in the chamber is 0.1 to 1 Pa, and the bias power of the lower electrode is Although 50-150W and ICP power are 200-300W, it is not limited to this, What is necessary is just to select suitably.

Next, an SiO ₂ film 115 having a thickness of 60 nm to 400 nm was deposited on the entire surface (including the ridge side view) of the intermediate obtained in FIG. 2A (c) by the plasma CVD method as shown in FIG. 2A (d). To grow.

Here, in the present embodiment 1, the growth of the thickness of the sikyeotjiman 60㎚~400㎚ SiO ₂ film 115 to form the ridge side wall protective layer, the thickness of the SiO ₂ film 115 is not limited thereto In order to remove the Si0 ₂ film 115 in a region other than the ridge sidewall surface in the next step, the amount of side etching caused by the additional etching of dry etching, or a fluoric acid chemical solution appropriately performed for the purpose of surface treatment in each step is used. According to the etching amount at the time of wet etching, the thickness of the SiO ₂ film 115 is not limited to this, but may be appropriately selected.

Note that the SiO ₂ film 115 used in the first embodiment is not limited to this, and as the material which can be used as the sidewall protective layer, it is highly selective to the wet etching chemical solution used in the subsequent step (anti-etching chemical resistance). ), And a material having a property of controlling film thickness at the time of film formation, which does not form an intermediate product with the AlGaInP-based semiconductor layer, may be used. Specific examples include SiN and Al ₂ O _{3 in} addition to the SiO ₂ film. A dielectric film, a semiconductor layer such as GaAs or AlGaAs, a metal film and an organic film having the above properties, and the like can be suitably achieved as a ridge sidewall protective layer.

On the other hand, examples of the means for forming these films include CVD methods (e.g., plasma CVD, atmospheric CVD, MOCVD, etc.) and PVD methods (sputter, vapor deposition, etc.). In this embodiment, high film thickness uniform film formation is possible. Especially, the plasma CVD method which is easy to form into a film is preferable. The CVD method is an abbreviation for chemical vapor deposition, and the PVD method is an abbreviation for physical vapor deposition.

Further, SiO ₂ film 115 used in the first embodiment is a single layer, but, not limited to this, may be composed of a plurality of layers, if necessary.

Next, as shown in (e) of FIG. 2A, the SiO ₂ film 115 in regions other than the ridge sidewall surface is removed by dry etching to form the SiO ₂ sidewall protective layer 116.

As the dry etching, a dry etching method capable of appropriately removing the SiO ₂ film 115 in regions other than the ridge side such as a reactive ion etching method (hereinafter referred to as RIE method), ICP method, and ECR method can be adopted. As the etching gas, CF gas such as a mixed gas of CF ₄ and CHF ₃ is used.

In the first embodiment, the RIE method is adopted, and a mixed gas of CF ₄ , CHF _3, and O ₂ is used as the etching gas. As dry etching conditions, the volume content of CF ₄ and CHF _{3 in} the mixed gas was 1 to 10% and 30 to 50%, the pressure was 40 to 60 Pa, and the stage temperature was 10 to 20 ° C. It can be changed appropriately.

Next, as shown in Fig. 2A (f), a hydrochloric acid-based chemical liquid (volume content of tartaric acid in the chemical solution is 30 to 50% and volume content of hydrochloric acid is 15 to 35%), which is a mixture of tartaric acid, hydrochloric acid and water, is used. The p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 is etched until the p-type Ga _0.5 In _0.5 P etching stop layer 106 is reached. Here, since the p-type Ga _{0 .5 0 .5} In P etching stop layer 106 it is resistant to hydrochloric acid-based chemical solution, the etching in the vertical direction with respect to the stop surface of the substrate by the exposure of that layer.

In addition, determination of the completion of the wet etching in the vertical direction with respect to the substrate surface can be performed by visual observation of the interference fringe in the etching region of the semiconductor substrate surface. When the p-type Ga _0.5 In _0.5 P etching stop layer 106 is exposed, the etching rate in the direction perpendicular to the substrate surface is extremely lowered, and the film thickness uniformity of the substrate surface is improved. The change stops. Therefore, it can be confirmed that the etching in the direction perpendicular to the substrate surface is stopped.

On the other hand, in the present embodiment 1, p-type _{(Al 0.7 Ga 0.3) 0.5 In} 0.5 P-second cladding layer 108, a chemical liquid to a wet etching but using a hydrochloric acid-based chemical liquid, not limited to this, SiO ₂ side wall A chemical liquid having high selectivity with respect to the protective layer 116 and the p-type Ga _0.5 In _0.5 P etching stop layer 106 may be used, for example, a sulfuric acid chemical liquid may be used.

Here, since the SiO ₂ sidewall protective layer 116 is highly resistant to hydrochloric acid-based chemicals, the region in which this layer is formed on the ridge side is not etched, but is side etched on the ridge side top portion (i.e., the portion to be the first side). Does not occur.

On the other hand, as shown in Fig. 2a in (f), it does not have the SiO ₂ side wall protection layer 116 formed on the ridge side region (ridge edge portion) proceeds is isotropically etched.

Here, in the wet etching, immediately after the etching in the vertical direction with respect to the substrate surface is stopped, the ridge side surface of the region where the SiO ₂ sidewall protective layer 116 is not formed is in the shape of a cross section perpendicular to the ridge stripe direction. It becomes a curved slope. Thus, Si0 _2, the side wall protection layer 116, the ridge side of the region is not formed: until the (second ridge-side wall 119, the ridge edges of) the substantially linear shape, it is preferable that as follow-up wet etching Do. Although the wet etching process part performed until the 2nd ridge side wall surface 119 (2nd surface) becomes a substantially linear inclined surface from a cross-sectional shape is called the "additional etching" for easy understanding, the said wet etching It is not necessary to divide into two stages, and wet etching may be performed until the 2nd ridge side wall surface 119 becomes a substantially linear inclined surface from a cross-sectional shape. In addition, what is necessary is just to select such an additional etching amount suitably according to the kind and mixing ratio of a chemical liquid.

Next, as shown in Fig. 2A (g), the SiO ₂ sidewall protective layer 116 is removed using a fluoric acid chemical.

In this embodiment 1, the thickness of the Si0 Si0 ₂ stripe 114 ₂ Since 100-300 nm is set larger than the side wall protective layer 116, only the SiO ₂ side wall protective layer 116 can be removed by stopping the etching by the said fluoroacid chemical by time control.

Here, in the first embodiment, although the wet etching technique is used to remove the Si0 ₂ sidewall protective layer 116, the chemical dry etching method is not limited to wet etching, and appropriately depending on the material constituting the sidewall protective layer (hereinafter, referred to as a wet etching technique). CDE law). Here, an etching technique capable of selectively removing the SiO ₂ sidewall protective layer 116 may be employed depending on the material constituting the sidewall protective layer.

Next, as shown in Fig. 2A (h), the n-type Al _0.5 In _0.5 P current block layer 107 is optionally 0.2 to 0.4 thick by using the SiO ₂ stripe 114 as a mask by the MOCVD method. Grow in 탆. Subsequently, the n-type GaAs cap layer 111 is selectively grown to a thickness of 0.1 to 0.2 탆 using the SiO ₂ stripe 114 as a mask by the MOCVD method.

On the other hand, before growing the n-type Al _0.5 In _0.5 P current block layer 107, the surface treatment is performed with sulfuric acid chemical to remove the damage layer on the ridge sidewall. At this time, the ridge sidewalls are etched in a range of about 15 nm to 40 nm. In addition, the chemical liquid for surface treatment may be a liquid mixture of hydrochloric acid and water.

On the other hand, although the current block layer has a portion expressed as "a current block layer formed except at least a part on the ridge", this is the case where the current block layer is not formed on the upper surface of the ridge, or illustrated Although it is not, it means that the vicinity of both ends of the longitudinal direction may be covered with a current block layer among the upper surfaces of the ridges that are elongated in a stripe shape. The latter case is preferable.

Next, as shown in Fig. 2A (i), after removing the SiO ₂ stripe 114 with a fluoric acid chemical or the like, the p-side electrode 112 and the n-side electrode 101 are formed by evaporation, and the ridge The stripe semiconductor laser wafer is completed. Examples of the material of the p-side electrode 112 include Ti / Pt / Au, and examples of the material of the n-side electrode 101 include AuGe / Ni / Au.

On the other hand, in the first embodiment, although the n-type Al _0.5 In _0.5 P current block layer 107 is used, a dielectric film such as SiN or SiO ₂ may be used. In this case, growth of the n-type GaAs cap layer 111 is unnecessary.

The ridge stripe formed in the first embodiment has high verticality and symmetry, and is formed by the ridge side surface (first ridge sidewall surface 118) close to the upper end of the ridge formed by dry etching and the surface of the n-type GaAs substrate 102. The angle can be in the range of 85 to 95 degrees. In addition, the code | symbol of a 1st surface (1st ridge sidewall surface: 118) and a 2nd surface (2nd ridge sidewall surface: 119) is attached only to (g) of FIG. 2A and (j)-(n) of FIG. 2B. In other drawings, reference numerals are omitted because the drawings become difficult to see. The angle formed between the ridge side surface and the surface of the semiconductor substrate is the angle of the side indicated by reference numeral 120 in FIGS. 2A, 2G, and 2H (in other words, the angle of the semiconductor substrate surface of the ridge side inside the ridge side). Angle formed by the first surface 118 or the second surface 119 and the semiconductor substrate surface, or in the case where a third intermediate surface exists between the first surface and the second surface. This definition also applies to the angle formed between the intermediate surface and the semiconductor substrate surface. In the other drawings, the reference numeral 120 is omitted, but the same definition applies to the angle formed between the ridge side surface and the semiconductor substrate surface. As described above, the angle at which the first surface (first ridge sidewall surface: 118) forms with the surface of the semiconductor substrate 102 is almost vertical, more preferably in the range of 85 to 95 degrees. In other words, when the angle is smaller than 90 degrees, the ridge cross-sectional shape is a net mesa shape. When the angle is larger than 90 degrees, the ridge cross-sectional shape is slightly inverse mesa shape. If the angle between the first ridge sidewall surface 118 and the surface of the semiconductor substrate 102 is substantially perpendicular, it is preferably within the range including both of these ranges.

On the other hand, the angle formed between the ridge inclined surface (second ridge sidewall surface 119) near the lower end of the ridge formed by wet etching and the n-type GaAs substrate 102 surface is in the range of 40 to 65 °. In the case where a semiconductor substrate having an inclined off angle is used, the angle formed between the ridge inclined surface (second surface) near the bottom of the ridge and the surface of the n-type GaAs substrate 102 is different on both sides of the ridge sidewall. For example, when the off angle is about 10 degrees, the angle is in the range of 40 to 50 degrees on one side and 60 to 70 degrees on the other side. This angle is due to the ridge, which is an _{(Al 0 .7 Ga 0 .3)} 0.5 In 0 (111) _.5 P of p-type second cladding layer 108 is exposed at the surface mainly side portions. The reason is explained below.

First, since the p-type second cladding layer 108 is epitaxially grown on the n-type GaAs substrate 102, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 and the n-type The crystal direction of the GaAs substrate 102 is almost straight. When the (100) plane of the GaAs substrate is not inclined, the angle between the (100) plane and the (111) plane is about 50 degrees. In the GaAs or Si single crystal crystal structure (zinc-light structure), the etching rate is the slowest on the (111) plane having the largest number of atomic arrangements, and as the wet etching proceeds at the ridge edge, the etching rate on this surface is increased. Become dominant. In the first embodiment, since the (100) plane is inclined by about 10 ° in the [011] direction, the (111) plane exposed on one side of the ridge is about 40 ° and the (111) plane exposed on the opposite side is about 60 °. It becomes about degree. As described above, in the first embodiment, it can be seen that the second ridge sidewall surface 119 formed by wet etching is mainly a (111) plane.

As described above, the first surface, which is the most of the surfaces of the ridge sidewall surface, is a surface substantially perpendicular to the semiconductor substrate surface, but since the angle with respect to the substrate surface of the second surface of the edge portion in contact with the substrate surface is small and smooth, the case where the dielectric film such as SiN or SiO ₂ as a current blocking layer, even, cover it with the source gas for forming a current blocking layer made of a dielectric film such as SiN or SiO ₂ in the edge ridge thing that is in short supply in the vicinity of the edge The coverage of the current block layer at the edge of the ridge that most affects the oscillation light is improved near the light emitting position. Further, by performing the above additional wet etching, the ridge inclined surface (second ridge sidewall surface 119) near the lower end of the ridge becomes an almost straight slope in a cross-sectional shape perpendicular to the ridge stripe direction. Since the number of exposed crystal surfaces is reduced compared to the curved surfaces, crystallinity at the ridge edge of the n-type Al _0.5 In _0.5 P current block layer 107 epitaxially grown is improved.

In addition, the topbu ridges formed in the present embodiment 1, the p-type Ga _{0 .5 0 .5} P In the intermediate layer 109 and the p-type GaAs contact layer 110 of the overhang is a shade-like protrusion is not formed. Therefore, no cavities are generated when the n-type Al _0.5 In _0.5 P current block layer 107 grows. In a ridge forming method using a conventional wet etching technique, an overhang is formed in the ridge top portion (for example, see FIG. 4C), and when the n-type Al _0.5 In _0.5 P current block layer 107 is formed, the cavity is directly below the overhang. This is formed to adversely affect the device characteristics.

Further, in the first embodiment, the boundary between the ridge sidewall surface formed by dry etching and the ridge sidewall surface formed by wet etching, that is, the boundary between the first ridge sidewall surface 118 and the second ridge sidewall surface 119 , An angle is formed, i.e., the boundary portion is bent to form the first ridge sidewall surface and the second ridge sidewall surface, but the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 is wet-etched. Ridge inclined surface (second ridge sidewall surface 119 near the bottom of the ridge) due to variation in the side etching amount generated under the SiO ₂ sidewall protective layer 116 and the thickness of the Si0 ₂ sidewall protective layer 116. )) And the ridge sidewall surface (first ridge sidewall surface 118) thereon, which is a surface substantially parallel to the surface of the semiconductor substrate, for example, (j) of FIG. 2B or (k) of FIG. Protrudes outside the ridge as shown by reference numeral 117 of the drawing corresponding to the step (g) of step 2a), or It is something that the pagodeun state if the inside, forming a step (step a step surface) of the step shape with a substantially plane parallel to the surface of the semiconductor substrate (such as a step the step surface of the third intermediate above (b1) of the surface). In the case of using a semiconductor substrate having an inclined off angle, the side etching amount (the amount of side etching) differs on both sides of the ridge in the cross-sectional shape perpendicular to the ridge stripe direction. At this time, with the increase in the substrate off angle, the difference in the amount of side etching on both sides of the ridge increases. Therefore, in this case, the stepped step surface as shown in Fig. 2B (l), Fig. 2B (m), or Fig. 2B (n) (all of the drawings corresponding to the step (g) in Fig. 2A). 117 is formed.

Here, as shown to FIG. 2B (j) and FIG. 2B (k), the dimension a-a 'and b-b' of the stepped step surface 117 are so preferable that they are small, 0.2 micrometer or less, and more preferable. Preferably it is 0.1 micrometer or less. On the other hand, in the case of using a semiconductor substrate having an inclined off angle, as shown in Fig. 2B, Fig. 2B, and Fig. 2B, the left and right stepped step surfaces 117 in the drawing. Although the dimensions c-c 'and d-d' of () are different, the smaller the above-mentioned dimension is, the smaller it is, and preferably 0.2 µm or less, more preferably 0.1 µm or less, in any stepped step surface 117.

In the structure shown in the first embodiment, for example, the distribution of the laser light guiding the inside of the resonator with a ridge width (that is, assumed to be the same width as the ridge top surface and the bottom surface) in the design perpendicular to the stripe direction is 1.5 占 퐉. When the maximum strength portion of the (Near Field Pattern, hereinafter abbreviated as NFP) is 100%, the strength of the NFP is about 50% from about 0.2 µm from the lower end of the ridge in design. Therefore, if the length of the stepped step surface is also within this range (0.2 µm or less), the steep change in the refractive index due to the stepped step portion is not greatly affected by the laser light. Here, the "change in refractive index" means the refractive index difference between the p-type second cladding layer 108 and the n-type current block layer 107. In addition, the stepped step surface which is substantially parallel to the surface of the semiconductor substrate and is substantially linear in the cross section, specifically, for example, (j), (k), (l), (m), ((b) of FIG. It means the surface of the step step 117 as shown to n). Hereinafter, such a step step surface may only be called a step step or a step step part.

On the other hand, the stepped step 117 is a stepped step (the length of the left and right stepped steps is the same) protruding to the outside of the ridge side, as shown in (j) of FIG. When used, it occurs when the side etching amount (amount to be side etched) is smaller than the thickness of the sidewall protective layer in the process of wet etching in FIGS. 2A to 2E. The step etching step 117 (the length of the left and right step steps are the same) which is dug into the ridge as shown in k) is the side etching amount in the step of wet etching, when a semiconductor substrate having no inclined off angle is used. Occurs when the amount (side etched) is greater than the thickness of the sidewall protective layer.

On the other hand, in the case of using a semiconductor substrate having an inclined off angle, in the wet etching process, the ridge shape changes as follows depending on the thickness of the sidewall protective layer and the amount of side etching generated on both sides of the ridge. In the ridge shape shown in (l) of FIG. 2B, the side etching amount of the side etching amount in the side etching amount (the side in which the side etching is large) is larger among the side etchings generated on both sides of the ridge in the wet etching process. Occurs when the thickness is smaller than. On the other hand, the ridge shape shown in (m) of FIG. 2B occurs when the amount of side etching respectively generated on both sides of the ridge in the wet etching process is larger than the thickness of the sidewall protective layer. In addition, in the ridge shape shown in (n) of FIG. 2B, one side etching amount (amount of side etching) is greater than the thickness of the sidewall protective layer among the side etchings generated on both sides of the ridge in the wet etching process. It occurs when the larger side and the other side etching amount (side etching amount) are smaller than the thickness of the sidewall protective layer.

In addition, FIG. 2B (j), FIG. 2B (k), FIG. 2B (l), FIG. 2B (m), and FIG. 2B (n) correspond to the process of FIG. 2A (g), respectively. It is sectional drawing of the cross section perpendicular | vertical to the stripe direction of the same ridge as FIG.2A (g) of another aspect in the process to make.

A surface substantially parallel to the surface of the semiconductor substrate, which is protruding outside the ridge or dug into the ridge, in other words, a step step 117 protrudes outside the ridge side, or a step step 117 dug into the ridge In the present invention, the first ridge side wall surface 118 and the second ridge side wall surface 119 are connected to each other through a step step, which is one of the third intermediate surfaces.

Here, from the experiments of the present inventors, in the first embodiment, in the cross section perpendicular to the ridge stripe direction, when viewed from the bottom of the semiconductor substrate surface, the first ridge sidewall surface 118 and the second ridge sidewall surface The knowledge that the side etching amount (amount etched side) at the time of wet etching on the straight line (linear line z in FIG. 2A (f)) substantially parallel to the said semiconductor substrate surface at the position which 119 connects acquires is obtained. lost. As described above, this is due to the fact that the second ridge sidewall surface 119 is aligned with the (111) surface during the wet etching, and the etching rate is constant and stabilized. Therefore, when (side etching amount) ≤ (side wall protective layer thickness), the shape in which the ridge sidewall surface 119 of the second surface protrudes outside the ridge can be stably formed in the wafer surface. On the other hand, when (side etching amount)> (side wall protective layer thickness) is made and the ridge sidewall surface 119 of a 2nd surface is made to penetrate inside a ridge, the ridge as shown in FIG. 2B (k) is formed, for example. . Here, if the wet etching is continued, the position where the lowermost end of the second ridge sidewall surface 119 is in contact with the etch stop layer 106 does not change with increasing etching time, but the position of 119 of FIG. 2B (k) is not changed. The surface extends obliquely upward along the surface so that the stepped step 117 moves in the direction of the ridge top by etching, and as shown in FIG. 2B (k '), the size of the stepped step 117 increases. . That is, when the ridge side wall surface is set to dig into the ridge, the controllability and stability of the ridge dimensions are deteriorated by the variation in the wet etching rate. In particular, since the recess is formed in the ridge, the current passage is narrowed, the resistance during the laser operation increases, and a characteristic deterioration such as an increase in the threshold value is likely to occur. Also, as shown in Fig. 2B (k '), when the recess is present, when the current block layer is formed, there is a fear that the current block layer does not completely fill the recess and a cavity is formed. Therefore, it is required to set (side etching amount) ≤ (side wall protective layer thickness) on both sides of the ridge. In order to do this, wet etching stops for a short time as the distance between the lower end of the sidewall protective layer 116 and the etching stop layer 106 is shorter, and therefore, for example, the sidewall protective layer depends on the thickness of the sidewall protective layer 116. Adjust the distance between the bottom of 116 and the etch stop layer 106, or adjust the thickness of the sidewall protective layer 116 according to the distance between the bottom of the sidewall protection layer 116 and the etch stop layer 106. And the like.

In the case where a dielectric film such as SiN or SiO _{2 is used} as the current block layer, the dimensions a-a ', b-b', c-c ', and d-d' of the stepped step 117 are current blocks on the ridge sidewall surface. It is preferable that it is below layer thickness. The angle formed between the first ridge sidewall surface 118 and the surface almost parallel to the surface of the semiconductor substrate is approximately 90 °, but the step block portion has a large current block layer thickness compared with the size of the step step 117. The supply shortage of the source gas for forming the dielectric film, such as SiN or SiO ₂ , does not occur, and the coverage of the current block layer does not decrease, which is preferable.

As described above, according to the first embodiment, after the stripe-shaped ridges are formed by dry etching so as to leave a part of the second p-type cladding layer, the sidewalls of the ridges are protected by Si0 ₂ or the like, and further, the p-type second cladding is performed. Since the layer was removed by wet etching, a stripe-shaped ridge having high perpendicularity and symmetry can be formed, and the difference between the carrier distribution shape and the light distribution shape of the semiconductor laser device obtained becomes small, and the hole burning phenomenon It is suppressed and a kink level improves. Furthermore, the ridge height can be made high, the laser light is prevented from being absorbed in the GaAs cap layer or the like, and a high output semiconductor laser having a large expansion of light from the active layer is obtained. In addition, the generation of cracks can be prevented by reducing the angle formed between the ridge portion and the lower layer. In wet etching, by setting (side etching amount) ≤ (side wall protective layer thickness), the shape in which the ridge sidewall surface 119 of the second surface protrudes outside the ridge can be stably formed in the wafer surface. As a result, recesses in the ridges can be prevented from increasing in resistance during laser operation, and cavities are formed in the ridge edges, whereby the refractive index can be prevented from significantly changing.

(Embodiment 2)

2E and 2F are sectional views showing the manufacturing process of the ridge stripe semiconductor laser device according to the second embodiment. In the second embodiment, it is an object to suppress the change in the refractive index caused by the step difference step 117 described above, and to stably form the dimensions and the shape of the ridge. In the second embodiment, as shown in Fig. 2A (b), the steps subsequent to the step of forming the SiO ₂ stripe 114 are the same as those in the first embodiment. In addition, it is common with Embodiment 1 also about laminated constitution.

After forming the Si0 ₂ stripe 114, in order to suppress the formation of the refractive index step by the step step 117, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 was subsequently used with the SiO ₂ stripe 114 as a mask. P second cladding layer 108, p-type Ga _0.5 In _0.5 P intermediate layer 109 and p-type GaAs contact layer 110, p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 Dry etching until At this time, the ridge shape generally consists of the sidewall surface 121 after the first dry etching and the bottom surface 122 after the dry etching, as shown in FIG. 2D of the first embodiment. Here, FIG. 2D is an enlarged view of the ridge in the vicinity of FIG. 2A (c) and the edge region 125 thereof. In the case where the sidewall protective film 116 is formed and wet etched as shown in Figs. 2A (d) and (e) by using the shape of this dry etching, the ridge when the surface of the semiconductor substrate is viewed downward If both sides are set to (side etching amount) ≤ (side wall protective layer thickness), and the ridge side wall surface is formed with a ridge that protrudes outside the ridge, side etching occurs under the SiO ₂ side wall protective layer 116, and is dry. After etching, the region under the SiO ₂ sidewall protective layer 116 of the bottom surface 122 becomes a step step 117 (step step surface of (b1) in the third intermediate surface) that is substantially parallel to the semiconductor substrate surface ( See step step 117 in FIG. 2B (j).

In addition, as described above, the smaller the dimension (dimension in the transverse direction toward the drawing) of the stepped step 117 is, the more preferable is 0.2 µm or less, and more preferably 0.1 µm or less. If the step step 117 is 0.2 µm or more, since the refractive index changes abruptly in the region (the intensity is 50% or less) of the low intensity of the laser light guiding in the resonator, the NFP tends to be disturbed under this influence. If the NFP is disturbed, the shape of the distribution of the light (Far Field Pattern, hereinafter referred to as FFP) emitted from the laser element is also deformed. For example, when laser light is focused on an optical disc through an objective lens or the like, the NFP does not become a circular shape, It may cause data reading or data writing error. Here, by setting (side etching amount) = (thickness of the SiO ₂ sidewall protective layer 116), it is possible to perform ridge formation without the step step 117 having a dimension of 0 占 퐉, that is, without the step step 117 (Fig. 2a (f) and (g)), suppressing the formation of the stepped step 117 completely throughout the wafer due to the wet etching rate or the variation in the thickness of the SiO ₂ sidewall protective layer 116 requires fairly precise control. . In the case where a semiconductor substrate having an inclined off angle is used, the dimensions of the stepped step 117 on one side are different because the size of the stepped step 117 is different on both sides of the ridge when the semiconductor substrate surface is viewed downward. Even if it is 0 micrometer, the step | step difference step 117 will necessarily be formed in the other side (refer to (o) and (p) of FIG. 2C).

Therefore, in the second embodiment, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 and the p-type Ga _0.5 In _0.5 P intermediate layer 109 using the SiO ₂ stripe 114 as a mask. , And dry etching the p-type GaAs contact layer 110 to the middle of the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108, the following dry etching conditions are selected, for example, Dry etching is performed so that it may become a ridge shape as shown to FIG. 2E (t-1) and FIG. 2F (u-1). On the other hand, the enlarged view of the part 126 of FIG. 2E (t-1) and the part 127 (ridge and its edge vicinity part) of FIG. 2F (u-1) is shown to FIG. 2G and FIG. 2H, respectively.

In the second embodiment, the ICP method is employed as the dry etching technique, and a mixed gas of SiCl ₄ and Ar is used as the etching gas. As an etching condition in which the shape of the ridge edge becomes Fig. 2E (t-1), the volume content rate of SiCl _{4 in} the mixed gas is 5 to 12%, the temperature of the lower electrode on which the semiconductor substrate is provided is 150 to 200 캜, and the pressure in the chamber. Silver is 0.3 to 0.5 Pa, the bias power of the lower electrode is 50 to 150 W, and the ICP power is 200 to 300 W. However, the present invention is not limited thereto, and dry etching conditions for obtaining a desired shape may be appropriately selected. In addition, as an etching condition of FIG. 2 f (u-1), the volume content rate of SiCl _{4 in} the mixed gas is 5 to 12%, the temperature of the lower electrode on which the semiconductor substrate is provided is 150 to 200 캜, and the pressure in the chamber is 0.1. Although the bias power of -0.3 Pa and the lower electrode was 50-150W, and ICP power was 200-300W, it is not limited to this, What is necessary is just to select the dry etching conditions from which a desired shape is obtained suitably.

FIG. 2G is an enlarged view of the ridge and its edge region neighborhood 126 in FIG. 2E (t-1), but the sidewall surface 121 after the first dry etching and the bottom after the dry etching, which are almost perpendicular to the semiconductor substrate surface. Between the surfaces 122, a dry etch sidewall side surface 123 is formed to be the third inclined intermediate surface. On the other hand, the dry sidewall surface 123 after the dry etching, which becomes the third inclined intermediate surface, may be composed of a plurality of surfaces, and an enlarged view of the ridge and its edge region neighborhood 127 in FIG. 2F (u-1). Like the dry etched sidewall surface 124 which is the third inclined intermediate surface of FIG. 2H, a plurality of small surfaces may be in a shape, that is, a curved surface (curved in cross section). When there are several sidewall surfaces after dry etching which are this 3rd inclination intermediate surface, the angle which the ridge sidewall surface which is this 3rd inclination intermediate surface and the surface of a semiconductor substrate makes is p-type Ga _0.5 In _0.5P etching stop layer 106 The closer to), the smaller the shape. In the case of the curved surface, the angle formed between the ridge sidewall surface and the semiconductor substrate surface becomes smaller as the angle between the tangent line and the semiconductor substrate surface at each position on the curve of the corresponding curve of the cross-sectional view becomes closer to the etching stop layer 106. The losing shape, in other words, this curve is called a convex curve in the ridge inward direction.

Here, the amount of dry etching is performed in the range of 65 to 95% of the ridge height, preferably in the range of 80% to 95%. If it is this range, the variation of the side etching amount by wet etching in the ridge edge part can be suppressed. When the area of the first surface formed by dry etching is too small, and as a result, the area to be wet etched becomes too large, the variation in etching amount is greatly influenced by the state (concentration, temperature, etc.) of the etching liquid, and the second This is because the influence of the crystal face of the face is not dominant. In addition, the said numerical range of the amount of dry etching and ridge height shows the relationship of the amount of dry etching in a ridge side part and ridge height here. That is, in the second embodiment, as shown in FIG. 2G and FIG. 2H, the angle formed between the ridge sidewall surface and the semiconductor substrate surface becomes smaller as the p-type Ga _0.5 In _0.5 P etching stop layer 106 becomes closer. Therefore, the ridge height as a reference when the amount of dry etching for forming the surface almost perpendicular to the semiconductor substrate surface is in the range of 65 to 95% of the ridge height is determined at the sidewall surface 121 after the first dry etching. Was based on the height of. That is, the ridge height serving as a reference when the amount of dry etching is in the range of 65 to 95% of the ridge height is based on the distance of the waterline that extends from the top of the ridge to the surface of the etching stop layer 106.

And dry etching is performed in 65 to 95% of the ridge height. In addition, the said numerical range and the ridge height used as a reference | standard of the quantity of dry etching and ridge height are the same as that of Embodiment 1.

In the second embodiment, as shown in FIG. 2G and FIG. 2H, the angle formed between the ridge sidewall surface and the semiconductor substrate surface becomes smaller as it approaches the p-type Ga _0.5 In _0.5 P etching stop layer 106.

In addition, as a method of obtaining such a desired dry etching amount, etching is performed while controlling the etching by time control, applying the monochromatic light to the surface of the substrate, and calculating the etching residual thickness from the relationship between the interference intensity obtained from the reflected light and time, The method of stopping an etching when the desired film thickness reaches is mentioned.

In the present invention, when the first surface or the third inclined intermediate surface is formed by dry etching, the dry etching technique that can be suitably employed is not limited to the above-described ICP method, and may be anisotropic plasma etching. As an example of dry etching, the method using the electron cyclotron resonance (hereinafter ECR) plasma etc. are mentioned. As the etching gas, a mixed gas of SiCl ₄ and Ar is used, but instead of the SiCl ₄ gas component, chlorine gas or boron trichloride gas may be used.

Subsequently, as shown in FIGS. 2E (t-2) and 2F (u-2), the front surface (including the ridge side) of the intermediate obtained in FIGS. 2E (t-1) and 2F (u-1). Then, SiO ₂ films 128 and 129 having a thickness of 60 nm to 400 nm are grown by plasma CVD.

Here, the thickness of the present embodiment in the form 2, sikyeotjiman grown SiO ₂ film (128 and 129) with a thickness of 60㎚~400㎚ to form the ridge side wall protection layer, SiO ₂ film (128 and 129) is limited to In order to remove the Si0 ₂ films 128 and 129 in regions other than the ridge sidewall surface in the next step, the amount of side etching caused by further etching of dry etching, or for surface treatment in each step The thickness of the SiO ₂ films 128 and 129 is not limited to this, and may be appropriately selected depending on the etching amount during wet etching using a fluoric acid chemical liquid to be appropriately performed.

Note that the SiO ₂ films 128 and 129 used in the second embodiment are not limited thereto, and the materials that can be used as the sidewall protective layer include high selectivity (anti-etching) with respect to the wet etching chemicals used in subsequent steps. Chemical liquid) and a material having a property of having high film thickness controllability during film formation without forming an intermediate product with the AlGaInP-based semiconductor layer may be used. Specific examples include SiN and Al ₂ O in addition to SiO ₂ films. A dielectric film of ₃ , a semiconductor layer of GaAs or AlGaAs, a metal film and an organic film having the above properties, and the like can be appropriately achieved as a ridge sidewall protective layer.

On the other hand, the CVD method and the PVD method may be mentioned as examples of the means for forming these films. In this embodiment, the plasma CVD method is particularly preferable in which film formation with high film thickness uniformity is possible and film formation is easy.

Note that although the SiO ₂ films 128 and 129 used in the second embodiment are single layers, they are not limited to this and may be composed of a plurality of layers as necessary.

Next, as shown in FIGS. 2E (t-3) and 2F (u-3), SiO ₂ films 128 and 129 in regions other than the ridge sidewall surfaces are removed by dry etching, and SiO ₂ sidewalls are removed. Protective layers 130 and 131 are formed.

As dry etching, a dry etching method capable of appropriately removing SiO ₂ films 128 and 129 in regions other than the ridge side such as RIE (Reactive Ion Etching) method, ICP method, and ECR method can be adopted. Do. As the etching gas, CF gas such as a mixed gas of CF ₄ and CHF ₃ is used.

In the second embodiment, on the other hand, the RIE method is employed, and a mixed gas of CF ₄ , CHF _3, and O ₂ is used as the etching gas. As dry etching conditions, the volume content of CF ₄ and CHF _{3 in} the mixed gas was 1 to 10% and 30 to 50%, the pressure was 40 to 60 Pa, and the stage temperature was 10 to 20 ° C. Instead, a dry etching condition capable of appropriately removing the SiO ₂ films 128 and 129 in regions other than the ridge side surfaces can be employed.

Next, as shown in FIGS. 2E (t-4) and 2F (u-4), the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second clad layer 108 is formed using a hydrochloric acid chemical solution. Etching is performed until the p-type Ga _0.5 In _0.5 P etching stop layer 106 is reached. Here, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is resistant to hydrochloric acid chemicals, the etching in the vertical direction with respect to the substrate surface is stopped by the exposure of this layer.

In addition, determination of the completion of the wet etching in the vertical direction with respect to the substrate surface can be performed by visual observation of the interference fringe in the etching region of the semiconductor substrate surface. When the p-type Ga _0.5 In _0.5 P etching layer stop layer 106 is exposed, the etching rate in the direction perpendicular to the substrate surface is extremely lowered, and the film thickness uniformity of the substrate surface is improved. The change stops. Therefore, it can be confirmed that the etching in the direction perpendicular to the substrate surface is stopped.

On the other hand, in the present embodiment 2, p-type _{(Al 0.7 Ga 0.3) 0.5 In} 0.5 P-second cladding layer 108, a chemical liquid to a wet etching but using a hydrochloric acid-based chemical liquid, not limited to this, SiO ₂ side wall A chemical liquid having high selectivity with respect to the protective layers 130 and 131 and the p-type Ga _0.5 In _0.5 P etching stop layer 106 may be used, for example, a sulfuric acid chemical liquid may be used.

Here, since the SiO ₂ sidewall protective layers 130 and 131 are highly resistant to hydrochloric acid-based chemicals, the area where the sidewall protective layer is formed on the ridge side is not etched, but rather on the ridge sidewall top (part that becomes the first surface). Side etching does not occur.

On the other hand, as shown in Figs. 2E (t-4) and 2F (u-4), regions (ridge edge portions) in which the SiO ₂ sidewall protection layers 130 and 131 are not formed on the ridge side are isotropic. The etching proceeds.

At this time, the side etching amount and the thickness of the SiO ₂ sidewall protective layers 130 and 131 are adjusted so that the ridge sidewall surfaces (the second surface and the third intermediate surface) protrude outward from the ridge on both sides of the ridge. Here, if the ridge side wall surface is formed into the ridge, the same ridge shape as in Fig. 2B (k) of Embodiment 1 is obtained.

Here, in the wet etching, immediately after the etching in the vertical direction with respect to the substrate surface is stopped, the ridge side surface of the region in which the SiO ₂ sidewall protective layers 130 and 131 are not formed has a cross section perpendicular to the stripe direction of the ridge. From the shape to the curved slope. Therefore, it is preferable to continue wet etching as it is until the ridge side surfaces (second ridge sidewall surfaces 133 and 135) of the region where the SiO ₂ sidewall protective layers 130 and 131 are not formed are almost straight. Do. Although the wet etching process part performed until the 2nd ridge side wall surfaces 133 and 135 become a substantially linear inclined surface in a cross-sectional shape is called the "additional etching" for easy understanding, this wet etching is dare 2 It is not necessary to divide into steps, and wet etching may be performed until the 2nd ridge side wall surface 135 becomes a substantially linear inclined surface from a cross-sectional shape. In addition, what is necessary is just to select such an additional etching amount suitably according to the kind and mixing ratio of a chemical liquid.

Next, as shown in FIGS. 2E (t-5) and 2F (u-5), the SiO ₂ sidewall protective layers 130 and 131 are removed using a fluoric acid chemical.

In the second embodiment, since the film thickness of the SiO ₂ stripe 114 is set to be 100 to 300 nm larger than the SiO ₂ sidewall protective layers 130 and 131, the etching by the fluoric acid chemical is stopped by time control. As a result, only the SiO ₂ sidewall protective layers 130 and 131 can be removed.

Here, although the wet etching technique was used to remove the SiO ₂ sidewall protective layers 130 and 131 in the second embodiment, it is not limited to wet etching, and the chemical dry etching method is appropriately performed depending on the material constituting the sidewall protective layer. CDE method) should be selected. Here, an etching technique capable of selectively removing the SiO ₂ sidewall protective layers 130 and 131 may be employed depending on the material constituting the sidewall protective layer.

Next, as shown in (t-9) of FIG. 2E or (u-8) of FIG. 2F, the n-type Al _0.5 In _0.5 P is selectively formed using the SiO ₂ stripe 114 as a mask by the MOCVD method. The current block layer 138 is grown in thickness of 0.2 to 0.4 mu m. Subsequently, the n-type GaAs cap layer 139 is selectively grown to a thickness of 0.1 to 0.2 탆 using the SiO ₂ stripe 114 as a mask by the MOCVD method.

On the other hand, before growing the n-type Al _0.5 In _0.5 P current block layer 107, the surface treatment is performed with sulfuric acid chemical to remove the damaged layer on the ridge sidewall. At this time, the ridge sidewall is etched in a range of about 15 nm to 40 nm. In addition, the chemical liquid for surface treatment may be a liquid mixture of hydrochloric acid and water.

On the other hand, although the current block layer has a portion expressed as "current block layer formed by removing at least a portion on the ridge", this is shown when the current block layer is not formed on the upper surface of the ridge, or Although not present, it means that the vicinity of both end portions in the longitudinal direction may be covered with a current block layer among the surfaces of the ridge elongated in a stripe shape, and the latter case is preferable.

Next, as shown in (t-10) of FIG. 2E or (u-9) of FIG. 2F, after removing the SiO ₂ stripe 114 with a fluoric acid chemical or the like, the p-side electrode 140 is formed by vapor deposition. An n-side electrode 141 is formed to complete a ridge stripe type semiconductor laser wafer. Examples of the material of the p-side electrode 140 include Ti / Pt / Au, and examples of the material of the n-side electrode 141 include AuGe / Ni / Au.

In the second embodiment, the n-type Al _0.5 In _0.5 P current block layer 138 is used, but a dielectric film such as SiN or SiO ₂ may be used. In this case, growth of the n-type GaAs cap layer 139 is unnecessary.

In the ridge stripe formed in the second embodiment, as shown in FIGS. 2I and 2J, 134, which is a third inclined intermediate surface, between the first ridge sidewall surface 121 and the second ridge sidewall surface 135. 136 is formed. Here, FIG. 2I is an enlarged view of the ridge and its edge area 132 in FIG. 2E (t-5), and FIG. 2J is an enlarged view of the ridge edge near area 133 in FIG. 2F (u-5). It is also. The 3rd inclined intermediate surface 134 is linear shape, and the 3rd inclined intermediate surface 136 is curved shape (curve shape which protruded toward the ridge inward direction), and inclined downward obliquely toward the ridge outer side, respectively. Therefore, as compared with the step step 117 which is almost parallel to the semiconductor surface in Embodiment 1, it is possible to suppress the steep change of the material at the edge of the ridge in the case of spatial view, that is, the steep change of the refractive index, It is possible to suppress the disorder of the NFP of the laser light and to prevent the deformation of the FFP. In particular, according to the second embodiment, it is possible to exhibit the above effects even when the width of the ridge edge portion exceeds 0.2 µm. Here, the "width of the ridge edge part" means, for example, the horizontal distance from the first ridge sidewall surface 121 shown in FIG. 2I to the portion where the second ridge sidewall surface 135 is in contact with the etching stop layer 106. .

Here, in the second embodiment, the ridge side wall surface protrudes out of the ridge on both sides of the ridge, and the side etching amount and the side wall protective layer thickness are adjusted (the third in the direction parallel to the substrate surface). After dry etching of the surface, it is necessary to set side wall surface dimension) ≥ (sidewall protective layer thickness)-(side etching amount) ≥0. For example, in FIG. 2G of the second embodiment, (the dimension of the sidewall surface 123 after dry etching of the third surface in the direction parallel to the substrate surface, that is, [h-h ']) ≥ (SiO ₂ sidewall protective layer ( 130) Thickness)-(side etching amount)> 0 Further, the smaller the size of the third intermediate plane 134 in the direction parallel to the substrate surface, that is, the j-j 'and kk' dimensions (Fig. 2E (t-5)), the smaller the value is, and preferably 0.2 µm or less, more preferably. Is required to be 0.1 µm or less. It is because the 3rd intermediate | middle surface does not adversely affect oscillation light in it being in this range. On the other hand, when (thickness of the SiO ₂ sidewall protective layer 130)-(side etching amount) ≥ (h-h ') ≥0, the ridge sidewall surface protrudes to the outside of the ridge, but FIG. 2E (t As shown in -6), the stepped step 137 made of a part of the bottom surface 122 after dry etching between the third intermediate surface 134 and the second ridge sidewall surface 135 and substantially parallel to the substrate surface. ) Is formed. If the length of the stepped step 137 exceeds 0.2 µm, there is a risk of causing deformation of the FFP due to the disturbance of the NFP of the laser light as described above. Therefore, the dimension in the direction parallel to the substrate surface of the third inclined intermediate surface and the length of the stepped step 137 are preferably 0.2 µm or less, more preferably 0.1 µm or less. On the other hand, as in FIG. 2E, also in FIG. 2F (see FIG. 2H), (the dimension of the sidewall surface 124 after the second dry etching in the direction parallel to the substrate surface, that is, [i-i ']) ≥ (Si0 ₂ sidewall protective layer 131 thickness)-(side etching amount)> 0. Further, the smaller the size of the third inclined intermediate surface 136 in the direction parallel to the substrate surface, that is, l-1 'and m-m' (see FIG. 2F (u-5) or FIG. 2J), the smaller the value is, It is required that it is .2 micrometers or less, More preferably, it is 0.1 micrometer or less.

In addition, when the semiconductor substrate which has the inclined off angle is used, the side etching amount differs on both sides of the ridge. In consideration of the side etching amount, on both sides of the ridge, (side wall surface dimension after dry etching of the third surface in the direction parallel to the substrate surface) is set to ≥ (side wall protective layer thickness)-(side etching amount) ≥ 0, The ridge side wall surface is required to have a ridge shape that protrudes outside the ridge.

On the other hand, in the first and second embodiments, the n-type GaAs substrate 102 having an off angle in which the substrate orientation is inclined by 10 ° from the (001) plane in the [110] direction is used. However, the present invention relates to the substrate off angle. Can be applied without

(Embodiment 3)

(K-1)-(w-6) of FIG. 2K and (x) of FIG. 2K are sectional drawing which shows the manufacturing process of the ridge stripe type semiconductor laser apparatus in this Embodiment 3. FIG. The third embodiment is limited to the case where the n-type GaAs substrate 102 uses a semiconductor substrate having an off angle in which the substrate orientation is inclined from the (100) plane in the [011] direction. As described in the first embodiment, when the off substrate is used, as shown in (l), (m), (n), and (p) of FIG. 2B, for example, the intermediate step surface 117 is necessarily used. Is formed. Therefore, this Embodiment 3 suppresses the change of the refractive index which arises in the vicinity of the connection part of the intermediate | middle step surface 117 and the 2nd surface 119 by suppressing formation of the intermediate | middle step surface 117 in Embodiment 1, Moreover, it aims at forming ridges with dimensional controllability and reproducibility. In addition, in this Embodiment 3, since it is common to Embodiment 1 until the process of forming the side wall protective layer 116 as shown to FIG. 2A (e), the process after that is demonstrated. The layer structure is also common to the first embodiment.

As shown in Fig. 2A (e), the SiO ₂ film 115 in regions other than the ridge sidewall surface is removed by dry etching, and the SiO ₂ sidewall protective layer 116 is formed. Here, in the cross section perpendicular to the stripe direction of the formed ridge, the ridge of the SiO ₂ sidewall protective layer 116 formed on both sides of the ridge when the substrate is viewed downward and viewed from the [01-1] direction. It is formed at a left side wall to the SiO ₂ protective layer (116α), and is formed at a right side wall of the ridge to the Si0 ₂ protective layer (116β) (see Figure 2k (w-1)).

Next, as shown in FIG. 2K (w-1), a resist pattern 145 is formed by photolithography. Here, the shape of the resist pattern 145 is not limited to this, SiO ₂ of all or of the side wall protection layer (116α) all or SiO ₂ side wall protection layer (116β) to cover a portion closer to the ridge at the bottom of The part near the bottom of the ridge should be exposed.

Next, as shown in (w-2) of FIG. 2K, the SiO ₂ sidewall protective layer 116β is etched by a thickness of 20 nm to 50 nm using a fluoric acid chemical solution to form a thin film, followed by a resist pattern. Remove 145. Here, SiO ₂ sidewall protective layer 116β after thinning by etching is referred to as SiO ₂ sidewall protective layer 116γ.

In Embodiment 3, in order to reduce the thickness of the SiO ₂ sidewall protective layer 116β, the wafer was etched by a thickness of 20 nm to 50 nm. However, the etching amount is not limited to this, but the p-type second step is performed in the next step. When wet etching the remaining portion of the clad layer 108 to the p-type etch stop layer 106, it is formed under the SiO ₂ sidewall protective layers 116α and 116γ, and the n-type GaAs substrate 102 What is necessary is just to change suitably according to the side etching amount determined by a substrate off angle.

In addition, the present embodiment 3,, SiO ₂ with respect to the side wall protection layer (116β), 1 / 2~1 with respect to the chemical solution to be used fluorine-based chemical etching rate is small, for example, when etching the Si0 ₂ stripe 114 / since the use of a chemical solution of a hydrofluoric acid concentration of about 10, without a loss, SiO ₂ side wall protection layer (116γ) by a time control may control the thickness of the SiO ₂ side wall protection layer (116γ). Further, when a portion of the Si0 ₂ stripe 114 that is exposed from the resist pattern 145, than the Si0 ₂ stripe 114 but also the etching, the film thickness of Si0 ₂ protective layer side wall (116β) of the exposed portion 100~ Since 300 nm is set large, the Si0 ₂ stripe 114 of the exposed part is not lost. In addition, although a step is formed in the SiO ₂ stripe 114 by etching with the fluoric acid-based chemical liquid, there is no problem unless the SiO ₂ stripe 114 is lost.

Here, in the third embodiment, although the wet etching technique is used for thinning the SiO ₂ sidewall protective layer 116β, the chemical dry etching method is not limited to wet etching, and is appropriately determined depending on the material constituting the sidewall protective layer (hereinafter, referred to as a wet etching technique). CDE law). In this case, an etching technique capable of selectively etching the SiO ₂ sidewall protective layer 116β may be employed depending on the material constituting the sidewall protective layer.

Next, as shown in (w-3) of FIG. 2K, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is formed by using a hydrochloric acid-based chemical solution, and the second clad layer 108 is p-type Ga _0.5 In _0.5 P. Etch until it reaches the etch stop layer 106. Here, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is resistant to hydrochloric acid chemicals, the etching in the vertical direction with respect to the substrate surface is stopped by the exposure of this layer. Here, in the third embodiment, a mixed solution of tartaric acid, hydrochloric acid and water is used as the hydrochloric acid-based chemical liquid, and the volume content of tartaric acid in the chemical liquid is 30 to 50%, and the volume content of hydrochloric acid is 15 to 35%.

In addition, determination of the completion of the wet etching in the vertical direction with respect to the substrate surface can be performed by visual observation of the interference fringe in the etching region of the semiconductor substrate surface. When the p-type Ga _0.5 In _0.5 P etching stop layer 106 is exposed, the etching rate in the direction perpendicular to the substrate surface is extremely lowered, and the film thickness uniformity of the substrate surface is improved. The change stops. Therefore, it can be confirmed that the etching in the direction perpendicular to the substrate surface is stopped.

On the other hand, in the third embodiment, a p-type _{(Al 0.7 Ga 0.3) 0.5 In} 0.5 P second cladding layer 108, a chemical liquid to a wet etching but using a hydrochloric acid-based chemical liquid is not limited to this, SiO ₂ side wall A chemical liquid having high selectivity with respect to the protective layers 116α and γ and the p-type Ga _0.5 In _0.5 P etching stop layer 106 may be used, for example, a sulfuric acid chemical liquid may be used.

Here, since the SiO ₂ sidewall protective layers 116α and 116γ are largely resistant to hydrochloric acid-based chemicals, the region where the layer is formed on the ridge side is not etched, and the SiO ₂ sidewall protective layers 116α and 116γ are formed. Side etching does not occur in the region (the first ridge sidewall surface 146).

On the other hand, in the region where the SiO ₂ sidewall protective layers 116α and 116γ are not formed on the ridge side, the etching proceeds isotropically.

Here, in the wet etching, immediately after the etching in the vertical direction with respect to the substrate surface is stopped, the ridge side surface of the region where the SiO ₂ sidewall protective layers 116α and 116γ are not formed has a cross section perpendicular to the stripe direction of the ridge. The shape becomes a curved slope. Therefore, it is preferable that as follow-up wet etching until the SiO ₂ side wall protection layer (116α and 116γ) is not formed, the ridge side (second ridge-side wall surface 147) is substantially linear in the region. Although the wet etch process part which performs until the 2nd ridge side wall surface 147 has a cross-sectional inclination of substantially linear shape, ie, the (111) surface as a whole, is called "additional etching" clearly, The wet etching need not be divided into two stages, and the wet etching may be performed until the second ridge sidewall surface 147 becomes an inclined surface that is substantially straight in cross section. In addition, what is necessary is just to select such an additional etching amount suitably according to the kind and mixing ratio of a chemical liquid.

Next, as shown in FIG. 2K (w-4), the SiO ₂ sidewall protective layers 116α and 116γ are removed using a fluoric acid chemical.

Since the present embodiment 3, since the thickness of the SiO ₂ stripe (114) Si0 ₂ sidewall protection layer (116 α and 116γ) than 100~300㎚ set larger, by the time control to stop the etching with the fluorine-based chemical liquid As a result, only the SiO ₂ sidewall protective layers 116α and 116γ can be removed.

Here, in the third embodiment, although the wet etching technique is used to remove the SiO ₂ sidewall protective layers 116α and 116γ, it is not limited to the wet etching, and the CDE method or the like is selected according to the material constituting the sidewall protective layer. Should be. Here, an etching technique capable of selectively removing the SiO ₂ sidewall protective layers 116α and 116γ may be employed depending on the material constituting the sidewall protective layer.

Next, as shown in Fig. 2K (w-5), the n-type Al _0.5 In _0.5 P current block layer 148 is optionally 0.2 in thickness by using the SiO ₂ stripe 114 as a mask by the MOCVD method. It grows to -0.4 micrometer. Subsequently, the n-type GaAs cap layer 149 is selectively grown to a thickness of 0.1 to 0.2 탆 using the SiO ₂ stripe 114 as a mask by the MOCVD method. On the other hand, before growing the n-type Al _0.5 In _0.5 P current block layer 148, surface treatment is performed with sulfuric acid chemical to remove the damaged layer on the ridge sidewall. At this time, the ridge sidewalls are etched in the range of about 15 nm to 40 nm. In addition, the chemical liquid for surface treatment may be a liquid mixture of hydrochloric acid and water.

On the other hand, although the current block layer has a portion expressed as "a current block layer formed by removing at least a part on the ridge", this is the case where the current block layer is not formed on the upper surface of the ridge or is illustrated. Although not, it means that the vicinity of both ends in the longitudinal direction may be covered with a current block layer among the surfaces of the ridge elongated in a stripe shape, and the latter case is preferable.

Next, as shown in FIG. 2K (w-6), after removing the SiO ₂ stripe 114 with a fluoric acid chemical or the like, the p-side electrode 150 and the n-side electrode 151 are formed by vapor deposition. The ridge stripe semiconductor laser wafer is completed. Examples of the material of the p-side electrode 150 include Ti / Pt / Au, and examples of the material of the n-side electrode 151 include AuGe / Ni / Au.

In the third embodiment, although the n-type Al _0.5 In _0.5 P current block layer 148 is used, a dielectric film such as SiN or SiO ₂ may be used. In this case, selective growth of the n-type GaAs cap layer 149 is unnecessary.

The ridge stripe formed in the third embodiment has high verticality and symmetry, and is formed by the angle between the ridge side on the side near the top of the ridge formed by dry etching and the surface of the n-type GaAs substrate 102, and by wet etching. The angle formed by the second ridge inclined surface near the lower end of the formed ridge and the surface of the n-type GaAs substrate 102 becomes equivalent to the ridge stripe formed in the first embodiment.

In this embodiment 3, (SiO ₂ side wall thickness of the protective layer (116α)) = (Si0 ₂ the side wall side etching amount to be raised in the protective layer (116α)), and (SiO ₂ thickness of the side wall protection layer (116γ)) = (Side etching amount generated under the SiO ₂ sidewall protective layer 116γ), the boundary between the ridge sidewall surface formed by dry etching and the ridge sidewall surface formed by wet etching, even though the inclined off substrate is used. A third intermediate step step surface or the like is not formed in the shape, and the first surface and the second surface are directly connected. Here, when the off substrate is used, the amount of side etching generated under the SiO ₂ sidewall protective layers 116α and 116γ when the wet etching of the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 is performed. (Side etching amount generated under the SiO ₂ sidewall protective layer 116α)> (side etching amount generated under the SiO ₂ sidewall protective layer 116γ), and both sides are increased with the increase of the substrate off angle. The difference in etching amount becomes large. Therefore, the thicknesses of the SiO ₂ sidewall protective layers 116α and 116γ may be selected according to the substrate off angle. On the other hand, in the embodiment 3, SiO ₂ side wall protection layer first ridge-side wall surface (146 by the variation in the thickness of the (116α and 116γ) side etching amount and, SiO ₂ side wall protection layer (116α and 116γ) occurring under ) And a third intermediate stepped step surface similar to the first embodiment may be formed between the second ridge sidewall side surface 147 and (Si0 ₂ sidewall protective layers 116α and 116γ) thickness ≥ (side etching amount) If set to (x) in FIG. 2K, the intermediate stepped step surface 152 is formed to protrude outside the ridge, and the third intermediate stepped surface 152 has dimensions nn 'and o-o. 'This small ridge can be formed with good dimensional control and reproducibility.

As described above, according to the present invention, the ridge formation for the purpose of removing the plasma damage layer due to dry etching while suppressing the side etching on the ridge side by the SiO ₂ sidewall protective layers 116, 130 and 131 and 116α and 116γ. In the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge, it is possible to form a ridge shape with uniform left and right symmetry. In addition, since a substantial portion of the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 is dry etched, it is highly vertical in the cross section perpendicular to the longitudinal direction (stripe direction) of the ridge. Highly symmetrical ridge shape is obtained. These effects are connected to the kink level improvement and the yield improvement of the obtained ridge stripe type semiconductor laser device.

In addition, according to the present invention, by wet etching, an almost straight inclined surface (second ridge sidewall surface) is formed near the light emitting position and the ridge edge portion most affecting the oscillation light, that is, the crystal to be exposed. By reducing the number of surfaces (exposed by a plurality of different kinds of crystal planes), the crystallinity of the current block layer composed of a semiconductor layer such as n-type AlInP at the ridge edge can be improved. In addition, in the case of the current block layer formed of dielectric films such as SiN and SiO ₂ , the coverage thereof can be improved. These effects are connected to the improvement of semiconductor laser element characteristics, such as the uniformity of the horizontal radiation angle of a laser beam, reduction of a threshold current or an operating current.

In addition, in this embodiment, although the AlGaInP system red semiconductor laser device was used, it is not limited to this, This invention is applicable to all the ridge stripe type semiconductor laser devices which used the mixed crystal compound semiconductor. On the other hand, in the ridge stripe type semiconductor laser device according to the present invention, not only the type having one stripe ridge, but also the type having a plurality of stripe ridges on the same substrate, and the type of emitting laser light of different wavelengths among them, It goes without saying that a laser device of the type which emits infrared light and red light, for example, is included.

Example 1

Next, referring to FIGS. 1 and 2A (a) to (e) used in Embodiment 1, and FIGS. 2C to (r) of the subsequent steps, the understanding of the present invention will be further facilitated. The present invention will be described in more detail with reference to Examples. However, the present invention is not limited to the following Examples, and can be applied to any ridge stripe type semiconductor laser device. On the other hand, (o)-(r) of FIG. 2C is sectional drawing which shows the process corresponded to (f)-(i) of FIG. 2A when using the semiconductor substrate which has the inclined specific off angle as a semiconductor substrate, FIG. Since the process before (o) of 2c is the same as the process shown to (a)-(e) of FIG. 2a, (a)-(e) of FIG. 2a and (o)-(r) of FIG. 2c Citations).

First, as shown in Figs. 1 and 2A (a), an n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P clad layer is formed on an n-type GaAs substrate 102 (450 μm in thickness) by MOCVD. 103 (thickness 2㎛), Ga _0.5 In _0.5 P active layer 104 (thickness 5㎚), p-type _{(Al 0 .7 Ga 0 .3)} 0.5 In 0 .5 P first cladding layer 105 ( 0.2㎛ thickness), p-type Ga _{0 .5 0 .5} In p etching stop layer 106 (thickness 10㎚), p-type _{(Al 0 .7 Ga 0 .3)} 0.5 In 0 .5 p second cladding layer (108) (thickness 1.2 mu m), a p-type Ga _0.5 In _0.5 P intermediate layer 109 (thickness 50 nm) and a p-type GaAs contact layer 110 (thickness 0.2 mu m) were sequentially formed. Next, on the p-type GaAs contact layer 110, an SiO ₂ film 113 (thickness 0.6 mu m) was formed by atmospheric pressure CVD.

On the other hand, the n-type GaAs substrate 102 used is an inclined substrate having an off angle in which the substrate orientation is inclined by 10 ° in the (100) plane.

Next, as shown in Fig. 2A (b), a SiO ₂ stripe 114 (width 2 mu m) was formed by a photolithography technique and a dry etching technique.

Next, as shown in (c) of FIG. 2A, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 and the p-type Ga _0.5 In are formed using the SiO ₂ stripe 114 as a mask. _{The 0.5} P intermediate layer 109 and the p-type GaAs contact layer 110 were dry etched to a position of 300 nm above the p-type Ga _0.5 In _0.5 P etch stop layer 106. Here, dry etching was stopped by time control.

As a dry etching, the ICP method was used. In addition, a mixed gas of SiCl ₄ and Ar was used as the etching gas. As dry etching conditions, the SiCl ₄ content in the mixed gas was about 11% by volume, the pressure in the chamber was about 0.6 Pa, the bias power of the lower electrode was 120W, and the ICP power was 200W.

Next, as shown in Fig. 2A (d), a 300 nm thick SiO ₂ film 115 is grown by plasma CVD on the entire surface (including the ridge side) of the intermediate obtained in Fig. 2A (c). I was.

Next, as shown in (e) of FIG. 2A, the SiO ₂ film 115 in regions other than the ridge side surface was removed by dry etching to form a SiO ₂ sidewall protective layer 116.

Here, dry etching was performed using the RIE method. Using the mixed gas of CF ₄ , CHF ₃ and O ₂ as the etching gas, the volume content of CF ₄ and CHF _{3 in} the mixed gas was 5% and 40%, and the pressure was 50 Pa, respectively, as dry etching conditions.

Next, the substrate was subjected to surface treatment using a fluoric acid chemical solution for the purpose of removing residues of the SiO ₂ film 115 in regions other than the ridge sidewalls.

Next, when the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 reaches the p-type Ga _0.5 In _0.5 P etching stop layer 106 using a mixed chemical solution of tartaric acid and hydrochloric acid. Etched to Here, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is resistant to the hydrochloric acid-based chemical liquid, the etching in the direction perpendicular to the substrate surface is stopped by the exposure of this layer. By visual observation of the interference fringe in the etching region, the etching stop in the direction perpendicular to the substrate surface was confirmed.

Since the SiO ₂ sidewall protective layer 116 is highly resistant to hydrochloric acid-based chemicals, the region where this layer is formed on the ridge sidewall surface is not etched, and side etching occurs on the ridge top portion (first ridge sidewall surface 118). Did not do it.

On the other hand, as shown in Fig. 2c of (o), do not have the side wall Si0 ₂ protective layer 116 is formed on the ridge side wall region was conducted is etched isotropically. On the other hand, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is formed, the etching in the direction perpendicular to the substrate surface does not proceed any further when the surface appears, but this is not performed in the above-described etching region. After visual confirmation of the interference fringe, it is continued as it is after that, and a substantially linear inclined surface (second ridge sidewall surface 119) is formed at the ridge edge, so that p-type (Al _0.7 Ga _0.3 ) _0.5 In _{In the case where the 0.5} P second cladding layer was used as the material for etching, wet etching was continued at the same time because it was etched at 200 nm in the direction perpendicular to the substrate surface (additional etching). Even if the further etching was continued in this manner, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 was formed, the etching did not proceed in the direction perpendicular to the substrate surface, but the inclined surface of the ridge edge (second ridge sidewall surface). (119) could form an almost straight inclined surface in the cross section perpendicular to the stripe direction of the ridge.

Next, as shown in Fig. 2C, only the SiOs sidewall protective layer 116 was removed by time control using a fluoric acid chemical.

Next, as shown in Fig. 2C (q), the n-type Al _0.5 In _0.5 P current block layer 107 is optionally formed by using the SiO ₂ stripe 114 as a mask by MOCVD. ) Grown. On the other hand, n-type Al _{0 .5 0 .5} In order to remove the damaged layer of the ridge side wall prior to growing the P current blocking layer 107, was subjected to surface treatment with sulfuric acid and the chemical solution (97% sulfuric acid). At this time, the ridge sidewall was etched by about 25 nm on one side. Subsequently, the n-type GaAs cap layer 111 (thickness 0.17 µm) was selectively grown using the SiO ₂ stripe 114 as a mask by the MOCVD method.

Next, as shown in Fig. 2C (r), after removing the SiO ₂ stripe 114 using a fluoric acid chemical, the p-side electrode 112 made of Ti / Pt / Au by vapor deposition (thickness 50 / An n-side electrode 101 (thickness 100/50/400 nm) made of 100/50 nm) and AuGe / Ni / Au was formed to complete a ridge stripe type semiconductor laser wafer.

The obtained ridge stripe had high verticality and symmetry, and the angle formed between the ridge side surface (first ridge sidewall surface 118) near the top of the ridge and the n-type GaAs substrate 102 surface was 86 °. On the other hand, the angle formed between the ridge side surface (the second ridge sidewall surface 119) near the bottom of the ridge and the surface of the n-type GaAs substrate 102 is an n-type GaAs substrate 102 having an off angle of about 10 °. As it used, it became 40 degrees, 62 degrees respectively in both ridges.

Further, an overhang in the sunshade where the p-type Ga _0.5 In _0.5 P intermediate layer 109 and the p-type GaAs contact layer 110 protruded was not formed on the ridge formed in this embodiment. Therefore, no cavity was generated during the growth of the n-type Al _0.5 In _0.5 P current block layer 107.

The obtained ridge stripe semiconductor laser wafer was excellent in the perpendicularity to the substrate surface of the ridge side surface and the symmetry of the ridge cross-sectional shape. In addition, since the kink level reached the maximum value 300 mW measurable with the measuring device used, it was confirmed that the kink level exceeded 300 mW at 25 ° C, and stably formed a ridge stripe semiconductor laser exhibiting excellent performance. Could.

On the other hand, a case where a SiN dielectric film was used instead of n-type Al _0.5 In _0.5 P as the current block layer 107 was also performed. In this case, growth of the n-type GaAs cap layer 111 is unnecessary, and other conditions are performed in the same manner, and thus, a ridge stripe type having the same performance as the case where n-type Al _0.5 In _0.5 P is used as the current block layer 107. The semiconductor laser can be formed stably.

In this embodiment, the boundary between the ridge side formed by dry etching and the ridge side formed by wet etching is a refractive portion at one ridge side, and the first ridge side wall surface and the second ridge side wall surface are angled. Formed and continued. Further, on the other ridge side surface, a stepped step portion that is a third surface is formed between the first ridge sidewall surface and the second ridge sidewall surface, and the dimension (g-g ') of the stepped step 117 is O. It became .07 micrometers. This aspect is the case where a semiconductor substrate having an inclined off angle as described in (l) of FIG. 2B is used, and the amount of side etching among the side etchings generated on both sides of the ridges in the wet etching process. In the case where the side etching amount of this larger side (the 2nd ridge sidewall surface of the left side of a figure in FIG.2 (o), (p) is the same as the thickness of a side wall protective layer, the side side etching amount is smaller (FIG. It is because in 2c (o) and (p), the side etching amount of the 2nd ridge side wall surface of the right side of the figure corresponded to the case where it is smaller than the thickness of a side wall protective layer.

Example 2

Subsequently, (a) to (b) of FIG. 2A used in the second embodiment, (t-1) to (t-2) and (t-7) to (t-10) of FIG. 2E of the subsequent steps. With reference to the following, the present invention will be described in more detail with reference to Examples in order to make the understanding of the present invention easier, but the present invention is not limited to the following Examples, but can be applied to any ridge stripe type semiconductor laser device. Do.

First, as shown in FIG. 2A (a), the n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P clad layer 103 is formed on the n-type GaAs substrate 102 (450 μm in thickness) by MOCVD. (2 μm thick), Ga _0.5 In _0.5 P active layer 104 (5 nm thick), p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P first clad layer 105 (0.2 μm thick), p-type Ga _0.5 In _0.5 P etching stop layer 106 (10 nm thick), p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 (thickness 1.2 μm), p-type Ga _0.5 In _0.5 P intermediate layer 109 (Thickness 50 nm) and the p-type GaAs contact layer 110 (thickness 0.2 micrometer) were formed one by one. Next, an SiO ₂ film 113 (thickness: 0.6 mu m) was formed on the p-type GaAs contact layer 110 by the atmospheric pressure CVD method.

On the other hand, the n-type GaAs substrate 102 used is an inclined substrate having an off angle in which the substrate orientation is inclined by 10 ° in the (100) plane.

Next, as shown in Fig. 2A (b), a SiO ₂ stripe 114 (width 2 mu m) was formed by a photolithography technique and a dry etching technique.

Next, as shown in (t-1) of FIG. 2E, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 and the p-type Ga are formed using the SiO ₂ stripe 114 as a mask. _{The 0.5} In _0.5 P intermediate layer 109 and the p-type GaAs contact layer 110 were dry etched to a position of 200 nm above the p-type Ga _0.5 In _0.5 P etch stop layer 106. Here, dry etching was stopped by time control.

As a dry etching, the ICP method was used. In addition, a mixed gas of SiCl ₄ and Ar was used as the etching gas. As dry etching conditions, the SiCl ₄ content in the mixed gas was about 8% by volume, the pressure in the chamber was about 0.4 Pa, the bias power of the lower electrode was 100W, and the ICP power was 250W. As a result, as shown in FIG. 2G, a dry etching sidewall side surface 123 serving as a third inclined intermediate surface was formed between the first dry etching sidewall surface 121 and the dry etching bottom surface 122. . Compared with the conditions of Example 1, the dry etching conditions lower the etching gas concentration, lower the lower electrode power, and lower the pressure in the chamber.

At the corner of the ridge bottom formed by etching, the flow of gas is worse than that of other parts, and the supply of etching gas is not sufficient compared with other parts, so the amount of dry etching is reduced at the corners, as shown by 123 in FIG. A third intermediate inclined surface is likely to occur. Under the dry etching conditions, a curved third intermediate inclined surface may be formed as shown at 124 of FIG. 2H. In this embodiment, the etching gas concentration is lowered to easily generate such a state. In addition, in this embodiment, by lowering the bias power of the lower electrode, the potential for pushing ions contributing to the etching into the substrate direction is reduced. Thereby, the lack of etching in a corner part is encouraged and it is thought that the 3rd inclined intermediate side wall surface like 123 of FIG. 2G arises. On the other hand, since the linearity of the ions contributing to the dry etching is lowered, the pressure is reduced to compensate for this.

Next, as shown in FIG. 2E (t-2), an SiO ₂ film having a thickness of 300 nm is formed on the entire surface (including the ridge side surface) of the intermediate obtained in FIG. 2E (t-1) by plasma CVD. 128).

Next, as shown in (t-7) of FIG. 2E, the SiO ₂ film 128 in regions other than the ridge side surface was removed by dry etching to form a SiO ₂ sidewall protective layer 130.

Here, dry etching was performed using the RIE method. By using a mixed gas of CF ₄ , CHF ₃ and O ₂ as the etching gas, as dry etching conditions, the volume content of CF ₄ and CHF _{3 in} the mixed gas was 5% and 40%, and the pressure was 50 Pa, respectively.

Next, the substrate was subjected to surface treatment using a fluoric acid chemical to remove the residues of the SiO ₂ film 128 in regions other than the ridge sidewalls.

Next, when the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 reaches the p-type Ga _0.5 In _0.5 P etching stop layer 106 using a mixed chemical solution of tartaric acid and hydrochloric acid. Etched to Here, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is resistant to the hydrochloric acid-based chemical liquid, the etching in the vertical direction with respect to the substrate surface is stopped by the exposure of this layer. By visual observation of the interference fringe in the etching region, the etching stop in the direction perpendicular to the substrate surface was confirmed.

Since the SiO ₂ sidewall protection layer 130 is highly resistant to hydrochloric acid-based chemicals, the region where the layer is formed on the ridge sidewall surface is not etched, and side etching occurs on the ridge top portion (first ridge sidewall surface 121). Did not do it.

On the other hand, as shown in Fig. 2e of the (t-7), that does not have the SiO ₂ side wall protection layer 130 is formed on the ridge side wall region was conducted is etched isotropically. On the other hand, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is formed, the etching in the direction perpendicular to the substrate surface does not proceed any further when the surface appears, but this is not the interference in the above-described etching region. After visual confirmation of the pattern, and after that, it is continued as it is, and a substantially linear inclined surface (second ridge sidewall surface 135) is formed at the ridge edge, so that p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 In the case where the P second cladding layer is used as the material for etching, wet etching is performed at the same time because it is etched 100 nm in the direction perpendicular to the substrate surface (additional etching). Even if the further etching was continued in this manner, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 was formed, the etching did not proceed in the direction perpendicular to the substrate surface, but the inclined surface of the ridge edge (second ridge sidewall surface). (135) was able to form a substantially straight inclined surface in the cross section perpendicular to the ridge stripe direction.

Next, as shown in (t-8) of FIG. 2E, only the SiO ₂ sidewall protective layer 130 was removed by time control using a fluoric acid chemical. At this time, the boundary between the first ridge side wall surface 121 and the second ridge side wall surface 135 becomes a refractive portion in one ridge side surface, and the first ridge side wall surface and the second ridge side wall surface are angled to directly Subsequently formed. Further, on the other ridge side surface, a third inclined intermediate surface 142 that extends obliquely downward in a straight line is formed between the first ridge side wall surface and the second ridge side wall surface, and the width p- p ') was 0.06 micrometer.

Next, as shown in (t-9) of FIG. 2E, the n-type Al _0.5 In _0.5 P current block layer 138 is optionally formed by using the SiO ₂ stripe 114 as a mask by MOCVD. 0.3 μm). On the other hand, the surface treatment was performed with sulfuric acid chemical solution (97% sulfuric acid) in order to remove the damage layer of the ridge sidewall before growing the Al _0.5 In _0.5 P current block layer 138. At this time, the ridge sidewall was etched by about 25 nm on one side. Subsequently, the n-type GaAs cap layer 139 (thickness 0.17 µm) was selectively grown using the SiO ₂ stripe 114 as a mask by the MOCVD method.

Next, as shown in (t-10) of FIG. 2E, after removing the SiO ₂ stripe 114 using a fluoric acid chemical, the p-side electrode 140 made of Ti / Pt / Au by a vapor deposition method (thickness). An n-side electrode 141 (thickness 100/50/400 nm) made of 50/100/50 nm) and AuGe / Ni / Au was formed to complete a ridge stripe type semiconductor laser wafer.

The obtained ridge stripe had high perpendicularity and symmetry, and the angle formed between the ridge side surface (first ridge sidewall surface 121) and the n-type GaAs substrate 102 surface near the upper edge of the ridge was 90 degrees. On the other hand, the angle formed between the ridge side surface (second ridge sidewall surface 135) and the surface of the n-type GaAs substrate 102 near the bottom of the ridge is about n-type GaAs substrate 102 having an off angle of about 10 °. As it is used, it is different from both sides of a ridge, and is 40 degrees (the 2nd ridge side wall surface of the left side of a figure in (t-8) of FIG. 2E), 62 degrees (FIG. (T-8) of FIG. 2E) 2nd ridge side wall surface) of the right side of the.

The obtained ridge stripe semiconductor laser wafer was excellent in the perpendicularity to the substrate surface of the ridge side surface and the symmetry of the ridge cross-sectional shape. In addition, since the kink level reached the maximum value 300 mW measurable with the measuring device used, it was confirmed that the kink level exceeded 300 mW at 25 ° C, and it was possible to stably form a ridge stripe type semiconductor laser exhibiting excellent performance. there was.

On the other hand, the SiN dielectric film was used instead of the n-type Al _0.5 In _0.5 P as the current block layer 138. In this case, the growth of the n-type GaAs cap layer 139 is unnecessary, and other conditions are performed in the same manner, and thus, a ridge stripe type having the same performance as the case where n-type Al _0.5 In _0.5 P is used as the current block layer 138. The semiconductor laser can be formed stably.

In the present embodiment, the boundary between the ridge side formed by dry etching and the ridge side formed by wet etching (see FIG. 2E (t-8)) is a refractive portion in one ridge side, and the first ridge The side wall surface and the second ridge side wall surface were formed at an angle and directly connected to each other. On the other ridge side, a third inclined intermediate surface 142 is formed between the first ridge sidewall surface and the second ridge sidewall surface, and the angle of the inclined intermediate surface 142 is 42 °. The dimension (p-p ') became 0.06 micrometer, and the ridge with small influence of the refractive index change by having an inclined intermediate surface could be formed. This aspect is the case where a semiconductor substrate having an inclined off angle as described in (l) of FIG. 2B is used, and the amount of side etching among the side etchings generated on both sides of the ridges in the wet etching process. In this larger side ((t-7) and (t-8) in FIG. 2E), the amount of side etching of the side etching amount of the second ridge sidewall surface on the left side of the drawing is the same as the thickness of the sidewall protective layer, In this smaller side ((t-7), (t-8) in Fig. 2E), the side etching amount of the second ridge sidewall surface on the right side of the drawing is smaller than the thickness of the sidewall protective layer, This is because the sidewall surface dimensions after the third dry etching in the parallel direction corresponded to ≧ (sidewall protective layer thickness) − (side etching amount).

Example 3

Subsequently, (u) to (u-1) to (u-2) and (u-6) of FIG. 2F used in the second embodiment of the processes subsequent to (a) to (b) of FIG. 2A used in the first embodiment. In order to further understand the present invention with reference to)-(u-9), the present invention will be described in more detail with reference to Examples, but the present invention is not limited to the following Examples, and all ridge stripes are provided. Applicable in the type semiconductor laser device.

First, as shown in FIG. 2A (a), the n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P clad layer 103 is formed on the n-type GaAs substrate 102 (450 μm in thickness) by MOCVD. (2 μm thick), Ga _0.5 In _0.5 P active layer 104 (5 nm thick), p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P first clad layer 105 (0.2 μm thick), p-type Ga _0.5 In _0.5 P etching stop layer 106 (thickness 10 nm), p type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 (thickness 1.2 μm), p type Ga _0.5 In _0.5 P intermediate layer 109 ) (Thickness 50 nm) and the p-type GaAs contact layer 110 (thickness 0.2 µm) were formed in this order. Next, an SiO ₂ film 113 (thickness: 0.6 mu m) was formed on the p-type GaAs contact layer 110 by the atmospheric pressure CVD method.

On the other hand, the n-type GaAs substrate 102 used is an inclined substrate having an off angle in which the substrate orientation is inclined by 10 ° in the (100) plane.

Next, as shown in Fig. 2A (b), a SiO ₂ stripe 114 (width 2 mu m) was formed by a photolithography technique and a dry etching technique.

Next, as shown in (u-1) of FIG. 2F, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 and the p-type Ga are formed using the SiO ₂ stripe 114 as a mask. _{The 0.5} In _0.5 P intermediate layer 109, and the p-type GaAs contact layer 110 were dry etched to a position of 200 nm above the p-type Ga _0.5 In _0.5 P etch stop layer 106. Here, dry etching was stopped by time control.

As a dry etching, the ICP method was used. In addition, a mixed gas of SiCl ₄ and Ar was used as the etching gas. As dry etching conditions, the SiCl ₄ content in the mixed gas was about 6% by volume, the pressure in the chamber was about 0.25 Pa, the lower electrode temperature was about 150 ° C, the bias power of the lower electrode was 120W, and the ICP power was 250W. As a result, as shown in FIG. 2H, between the first ridge sidewall surface 121 and the bottom surface 122 after dry etching, the third curved drywall sidewall surface 124 protruding in the ridge inward direction is formed. ) Was formed.

Next, as shown in Fig. 2F (u-2), an SiO ₂ film having a thickness of 300 nm is formed on the entire surface (including the ridge side surface) of the intermediate obtained in Fig. 2F (u-1) by plasma CVD. (129) was grown.

Next, as shown in (u-6) of FIG. 2F, the SiO ₂ film 129 in the regions other than the ridge side surface was removed by dry etching, and the SiO ₂ sidewall protective layer 131 was formed.

Here, dry etching was performed using the RIE method. In addition, using a mixed gas of CF ₄ , CHF ₃ and O ₂ as the etching gas, the volume content of CF ₄ and CHF _{3 in} the mixed gas was 5% and 40%, the pressure was 50 Pa, respectively, and the stage temperature was the dry etching condition. It was 15 degreeC.

Next, the substrate was subjected to surface treatment using a fluoric acid chemical to remove residues of the SiO ₂ film 129 in regions other than the ridge sidewalls.

Next, as shown in (u-7) of FIG. 2F, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second clad layer 108 is p-type Ga using a mixed chemical solution of tartaric acid, hydrochloric acid and water. Etching was performed until the _0.5 In _0.5 P etch stop layer 106 was reached. Here, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is resistant to the hydrochloric acid-based chemical liquid, the etching in the direction perpendicular to the substrate surface is stopped by the exposure of this layer. By visual observation of the interference fringe in the etching region, the etching stop in the direction perpendicular to the substrate surface was confirmed. The volume content of tartaric acid and hydrochloric acid in the chemical solution was 40% and 30%, respectively.

Since the SiO ₂ sidewall protective layer 131 is highly resistant to hydrochloric acid-based chemicals, the region where the layer is formed on the ridge sidewall surface is not etched, and side etching occurs on the ridge top portion (first ridge sidewall surface 121). Did not do it.

On the other hand, etching was performed isotropically in the region where the SiO ₂ sidewall protective layer 131 was not formed on the ridge sidewall surface. On the other hand, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is formed, the etching in the direction perpendicular to the substrate surface does not proceed any further when the surface appears, but this is not the interference in the above-described etching region. After visual confirmation of the pattern, and after that, it is continued as it is, and a substantially linear inclined surface (second ridge sidewall surface 135) is formed at the ridge edge, so that p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 In the case where the P second clad layer was used as the material to be etched, wet etching was continued at the same time because it was etched 100 nm in the direction perpendicular to the substrate surface (additional etching) (see FIG. 2J). Even if further etching was continued in this manner, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 was formed, the etching did not proceed in the direction perpendicular to the substrate surface, but the inclined surface of the ridge edge portion (second ridge side). In the cross section perpendicular | vertical to the stripe direction of the ridge, the wall surface 135 became a straight line for the most part of the 2nd ridge side wall surface 135, and could form the substantially inclined surface. In addition, the boundary between the first ridge side wall surface 121 and the second ridge side wall surface 135 becomes a refractive portion in one ridge side surface, and the first ridge side wall surface and the second ridge side wall surface are angled to directly Subsequently formed. Further, on the other ridge side surface, a curved third inclined intermediate surface 143 was formed between the first ridge side wall surface and the second ridge side wall surface.

Next, as shown in (u-7) of FIG. 2F, only the SiO ₂ sidewall protective layer 131 was removed by time control using a fluoric acid chemical.

Next, as shown in Fig. 2F, (u-8), an n-type Al _0.5 In _0.5 P current block layer 138 is optionally formed by using the SiO ₂ stripe 114 as a mask by MOCVD. Μm). In addition, the surface treatment was performed with sulfuric acid chemical solution (97% sulfuric acid) in order to remove the damage layer of the ridge sidewall before growing the n-type Al _0.5 In _0.5 P current block layer 138. At this time, the ridge sidewall was etched by about 25 nm on one side. Subsequently, the n-type GaAs cap layer 139 (thickness 0.17 µm) was selectively grown using the SiO ₂ stripe 114 as a mask by the MOCVD method.

Next, as shown in Fig. 2F (u-9), after removing the SiO ₂ stripe 114 using a fluoric acid chemical, the p-side electrode 140 (thickness) made of Ti / Pt / Au by evaporation method (thickness). An n-side electrode 141 (thickness 100/50/400 nm) made of 50/100/50 nm) and AuGe / Ni / Au was formed to complete a ridge stripe type semiconductor laser wafer.

The obtained ridge stripe had high perpendicularity and symmetry, and the angle formed between the ridge side surface (first ridge sidewall surface 121) close to the ridge top and the surface of the n-type GaAs substrate 102 became 87 °. On the other hand, the angle formed between the ridge side surface (second ridge sidewall surface 135) near the bottom of the ridge and the surface of the n-type GaAs substrate 102 uses an n-type GaAs substrate 102 having an off angle of about 10 °. Since the ridges are different on both sides of the ridge, respectively, 40 ° (the second ridge sidewall surface on the left side of the figure in (u-6) and (u-7) of FIG. 2F) and 62 ° (u- of FIG. 2F). 6) and (u-7), it became the 2nd ridge side wall surface of the right side of a figure.

The obtained ridge stripe semiconductor laser wafer was excellent in the perpendicularity to the substrate surface of the ridge side surface and the symmetry of the ridge cross-sectional shape. In addition, since the kink level reached the maximum value 300 mW measurable with the measuring device used, it was confirmed that the kink level exceeded 300 mW at 25 ° C, and it was possible to stably form a ridge stripe type semiconductor laser exhibiting excellent performance. there was.

On the other hand, the SiN dielectric film was used instead of the n-type Al _0.5 In _0.5 P as the current block layer 138. In this case, the growth of the n-type GaAs cap layer 139 is unnecessary, and other conditions are performed in the same manner, and thus, a ridge stripe type having the same performance as the case where n-type Al _0.5 In _0.5 P is used as the current block layer 138. The semiconductor laser could be formed stably.

In addition, in the third embodiment, the boundary between the ridge side formed by dry etching and the ridge side formed by wet etching is a refractive portion at one ridge side, and the first ridge side wall surface and the second ridge side wall surface are An angle was formed and formed in direct succession. Further, on the other ridge side surface, a third inclined intermediate surface is formed between the first ridge side wall surface and the second ridge side wall surface, and the angle of the inclined intermediate surface 143 is 45 °, and the ridge edge portion In this case, a ridge with a small change in refractive index could be formed. On the other hand, in the third embodiment, the inclined intermediate surface 143 is curved, and the angle of the inclined intermediate surface 143 is here the inclined middle at the connection point between the second ridge sidewall surface 135 and the inclined intermediate surface 143. It is an angle between the tangent of the surface 143 and the surface of the semiconductor substrate. This aspect is the case where a semiconductor substrate having an inclined off angle as described in (l) of FIG. 2B is used, and the amount of side etching among the side etchings generated on both sides of the ridges in the wet etching process. In the case where the side etching amount of this larger side ((u-6) and (u-7) of FIG. 2F is the same as the thickness of the sidewall protective layer, In the case where the side etching amount of the smaller side (the second ridge sidewall surface on the right side of the figure in (u-6) and (u-7) of FIG. 2F is smaller than the thickness of the sidewall protective layer, (parallel with the substrate surface) This is because the size of the sidewall surface after the second dry etching in the direction) ≥ (sidewall protective layer thickness)-(side etching amount).

Example 4

Subsequently, refer to (a) to (e) of FIG. 2A used in the first embodiment, and (w-1) to (w-6) and (x) of FIG. 2K used in the third embodiment of the process subsequent thereto. In order to further understand the present invention, the present invention will be described in more detail with reference to Examples. However, the present invention is not limited only to the following Examples and can be applied to all ridge stripe type semiconductor laser devices.

First, as shown in Fig. 2A (a), the n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P clad layer 103 is formed on the n-type GaAs substrate 102 (450 μm in thickness) by MOCVD. (2 μm thick), Ga _0.5 In _0.5 P active layer 104 (5 nm thick), p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P first clad layer 105 (0.2 μm thick), p-type Ga _0.5 In _0.5 P etching stop layer 106 (thickness 10 nm), p type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 (thickness 1.2 μm), p type Ga _0.5 In _0.5 P intermediate layer 109 ) (Thickness 50 nm) and the p-type GaAs contact layer 110 (thickness 0.2 µm) were formed in this order. Next, an SiO ₂ film 113 (thickness 0.6 mu m) was formed on the p-type GaAs contact layer 110 by the atmospheric pressure CVD method.

On the other hand, the n-type GaAs substrate 102 used is an inclined substrate having an off angle in which the substrate direction is inclined by 10 ° in the (100) plane.

Next, as shown in Fig. 2A (b), a SiO ₂ stripe 114 (width 2 m) was formed by photolithography and dry etching.

Next, as shown in (c) of FIG. 2A, the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 108 and the p-type Ga _0.5 In are formed using the SiO ₂ stripe 114 as a mask. _{The 0.5} P intermediate layer 109 and the p-type GaAs contact layer 110 were dry etched to a position of 300 nm above the p-type Ga _0.5 In _0.5 P etch stop layer 106. Here, dry etching was stopped by time control.

As a dry etching, the ICP method was used. In addition, a mixed gas of SiCl ₄ and Ar was used as the etching gas. As dry etching conditions, the SiCl ₄ content in the mixed gas was about 11% by volume, the pressure in the chamber was about 0.7 Pa, the lower electrode temperature was about 190 ° C, the bias power of the lower electrode was 120W, and the ICP power was 200W.

Next, as shown in Fig. 2A (d), an SiO ₂ film 115 having a thickness of 300 nm is formed on the entire surface (including the ridge side surface) of the intermediate obtained in Fig. 2A (c) by plasma CVD. Grown.

Next, as shown in Fig. 2A (e), the SiO ₂ film 115 in regions other than the ridge side surface is removed by dry etching, and the SiO ₂ sidewall protective layers 116α and 116β (Fig. 2K (w-)). 1)).

Here, dry etching was performed using the RIE method. In addition, as dry etching conditions using a mixed gas of CF ₄ , CHF ₃ and O ₂ as the etching gas, the volume content of CF ₄ and CHF _{3 in} the mixed gas was 5% and 40%, the pressure was 50 Pa, respectively, and the stage temperature was It was 15 degreeC.

Next, fluorine-based, using a chemical liquid, is subjected to surface treatment of the substrate for the purpose of removing regions of the SiO ₂ film 115 residues other than the side wall ridges. At this time, the SiO ₂ sidewall protective layers 116α and 116β were also etched in the fluoric acid chemical, and the thicknesses of the SiO ₂ sidewall protective layers 116α and 116β were 0.12 μm.

Next, as shown in FIG. 2K (w-1), a resist pattern 145 was formed by photolithography.

Next diagram form an SiO ₂ side wall protection layer (116γ), the 0.07㎛ thickness, by etching the fluorine SiO ₂ using a chemical solution-based sidewall protection layer (116β) as shown in (w-2) of 2k After that, the resist pattern 145 was removed.

Next, as shown in (w-3) of FIG. 2K, p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second clad layer 108 is p-type Ga using a mixed chemical solution of tartaric acid, hydrochloric acid and water. Etching was performed until a _0.5 In _0.5 P etch stop layer 106 was reached. Here, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is resistant to the hydrochloric acid-based chemical liquid, the etching in the direction perpendicular to the substrate surface is stopped by the exposure of this layer. By visual observation of the interference fringe in the etching region, the etching stop in the direction perpendicular to the substrate surface was confirmed. The volume content of tartaric acid and hydrochloric acid in the chemical solution was 40% and 30%, respectively.

Since the SiO ₂ sidewall protective layers 116α and γ are highly resistant to hydrochloric acid-based chemicals, the regions where these layers are formed on the ridge sidewall surfaces are not etched, but are side etched on the ridge top portion (first ridge sidewall surface 146). Did not occur.

On the other hand, in the region where the SiO ₂ sidewall protective layers 116α and 116γ are not formed on the ridge sidewall surface, etching proceeds isotropically. Further, since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is formed, the etching in the direction perpendicular to the substrate surface does not proceed any further when the surface appears, but this is not caused by the interference pattern in the above-described etching region. After visual confirmation, the film was continued again afterwards to form a substantially straight inclined surface (second ridge sidewall surface 147) at the ridge edge, so that the p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P In the case where the second cladding layer was used as the material for etching, wet etching was continued at the same time because it was etched at 200 nm in the direction perpendicular to the substrate surface (additional etching). Since the p-type Ga _0.5 In _0.5 P etching stop layer 106 is formed even after further etching in this manner, the etching is not performed in the direction perpendicular to the substrate surface, but the inclined surface of the ridge edge portion (the second ridge sidewall surface ( 147)), in the cross section perpendicular to the stripe direction of the ridge, most of the upper side of the second ridge sidewall surface 147 became a straight line, and an almost straight inclined surface could be formed.

Next, as shown in FIG. 2K (w-4), only the SiO ₂ sidewall protective layers 116α and 116γ were removed by time control using a fluoric acid chemical.

Next, as shown in Fig. 2K (w-5), the n-type Al _0.5 In _0.5 P current block layer 148 is selectively formed using the SiO ₂ stripe 114 as a mask by MOCVD. Μm). In addition, in order to remove the damage layer of the ridge sidewall before growing the n-type Al _0.5 In _0.5 P current block layer 148, surface treatment was performed with sulfuric acid chemical liquid. At this time, the ridge sidewall was etched by about 25 nm on one side. Subsequently, the n-type GaAs cap layer 149 (thickness 0.1 mu m) was selectively grown using the SiO ₂ stripe 114 as a mask by MOCVD.

Next, as shown in (w-6) of FIG. 2K, after removing the SiO ₂ stripe 114 using a fluoric acid chemical, the p-side electrode 150 made of Ti / Pt / Au by the vapor deposition method (thickness). An n-side electrode 151 (thickness 100/50/400 nm) made of 50/100/50 nm) and AuGe / Ni / Au was formed to complete a ridge stripe type semiconductor laser wafer.

The obtained ridge stripe had high verticality and symmetry, and the angle formed between the ridge side surface (first ridge sidewall surface 146) close to the ridge upper end and the surface of the n-type GaAs substrate 102 was 90 °. On the other hand, the angle formed between the ridge side surface (second ridge sidewall surface 147) near the bottom of the ridge and the surface of the n-type GaAs substrate 102 uses the n-type GaAs substrate 102 having an off angle of 10 °. As it was, it became 40 degrees, 62 degrees respectively in both ridges.

In addition, an overhang in the sunshade where the p-type Ga _0.5 In _0.5 P intermediate layer 109 and the p-type GaAs contact layer 110 protruded was not formed on the ridge formed in this embodiment. Therefore, no cavity was generated during the growth of the n-type Al _0.5 In _0.5 P current block layer 148.

The obtained ridge stripe semiconductor laser wafer was excellent in the perpendicularity to the substrate surface of the ridge side surface and the symmetry of the ridge cross-sectional shape. In addition, since the kink level reached the maximum value 300 mW measurable with the measuring device used, it was confirmed that the kink level exceeded 300 mW at 25 ° C, and it was possible to stably form a ridge stripe type semiconductor laser exhibiting excellent performance. there was.

On the other hand, the SiN dielectric film was used instead of the n-type Al _0.5 In _0.5 P as the current block layer 148. In this case, the growth of the n-type GaAs cap layer 149 is unnecessary, and other conditions are performed in the same manner, and thus, a ridge stripe type having the same performance as the case where n-type Al _0.5 In _0.5 P is used as the current block layer 148. The semiconductor laser can be formed stably.

In addition, in the fourth embodiment, the thicknesses of the sidewall protective layers 116α and 116γ are adjusted so that (side wall protective layer thickness) = (side etching amount) on both sides of the ridge. Therefore, the boundary between the ridge side formed by the dry etching and the ridge side formed by the wet etching is a refractive portion in the ridge side, and the first ridge side wall surface and the second ridge side wall surface are formed in direct angle at an angle. This is because, as described above, when the semiconductor substrate having the inclined off angle is used, the side etching amounts correspond to the thicknesses of the sidewall protective layers on both sides of the ridge in the wet etching process. .

As described above, according to the present invention, it is possible to improve device characteristics such as uniform horizontal radiation angle of laser light, improvement of differential quantum efficiency, and improvement of kink level in a ridge stripe type semiconductor laser device. In addition, ridge stripe can be formed uniformly in the wafer plane and between the wafers, and the yield can be improved. Therefore, it can use efficiently for a ridge stripe type semiconductor laser device. These semiconductor laser devices can be applied to an optical disk or the like which can be rewritten.

Claims (17)

On the compound semiconductor substrate, a cladding layer of a first conductivity type, an active layer, a first cladding layer of a second conductivity type, an etch stop layer, a second cladding layer of a second conductivity type formed on a stripe ridge, 12. A semiconductor laser device having a current block layer formed on at least part of said ridge, said cross-sectional shape perpendicular to the stripe direction of said ridge, wherein each side of each side of said ridge is perpendicular to a surface of said semiconductor substrate and said ridge A first surface extending downward from an upper end and a second surface formed of a straight edge portion inclined surface inclined downwardly obliquely toward the ridge outside at the ridge edge portion, the first surface and the second surface (a) is directly connected, (b) the first surface and the second surface are connected via a third intermediate surface; The third intermediate surface, (b1) a stepped step surface parallel to the surface of the semiconductor substrate, protruding outside the ridge, having a linear shape having a length in a direction parallel to the surface of the semiconductor substrate when viewed from the cross section, or or, (b2) connected through a straight or curved inclined intermediate surface protruding outwardly from the ridge obliquely downward, A ridge stripe type semiconductor laser device in which the (111) plane of the semiconductor constituting the second clad layer is exposed on the second plane. The ridge stripe type semiconductor laser device according to claim 1, wherein the (111) surface is exposed to at least 50% or more of the second surfaces. The ridge stripe type semiconductor laser device according to claim 1, wherein an angle formed between the first surface and the surface of the semiconductor substrate in a cross-sectional shape perpendicular to the stripe direction of the ridge is 85 ° or more and 95 ° or less. The ridge stripe type semiconductor laser device according to claim 1, wherein a length of a linear stepped step surface parallel to the semiconductor substrate surface of the third intermediate surface is equal to or less than a layer thickness of the current block layer on the ridge side surface. The ridge stripe type semiconductor laser device according to claim 1, wherein the surface orientation of the surface of the semiconductor substrate is a surface orientation inclined with respect to the (100) plane. The ridge stripe type semiconductor laser device according to claim 5, wherein the inclination direction of the (100) plane is a direction. Forming a cladding layer of a first conductivity type, an active layer, a first cladding layer of a second conductivity type, an etching stop layer, and a second cladding layer of a second conductivity type on the compound semiconductor substrate; Etching the second cladding layer of the second conductivity type to the middle using a dry etching technique except for a portion forming a stripe ridge, and one layer on the side of the ridge formed by the dry etching. Forming a sidewall protective layer as described above, and further etching the second cladding layer of the second conductivity type until the etching stop layer is reached by using a wet etching technique, and the ridge side formed by the dry etching and the Forming a stripe ridge having a ridge side formed by wet etching; removing the sidewall protection layer; and forming a current block layer except at least a portion of the ridge. The method for producing a ridge, the ridge stripe type semiconductor laser device to etch at least a portion of the side surface of the semiconductor (111) constituting the second clad layer so as to expose in a step, and in the wet etching process. The method of manufacturing a ridge stripe type semiconductor laser device according to claim 7, wherein the wet etching step exposes the (111) plane to an area of at least 50% or more of the ridge side surfaces formed by the wet etching. The cross section perpendicular to the stripe direction of the ridge, wherein the thickness of the sidewall protective layer is ≥ (side etching amount of the second clad layer of the second conductivity type in the wet etching step). , Manufacturing method of ridge stripe type semiconductor laser device. The method of manufacturing a ridge stripe type semiconductor laser device according to claim 7, wherein the surface orientation of the surface of the semiconductor substrate is the surface orientation inclined with respect to the (100) plane. The method of manufacturing a ridge stripe type semiconductor laser device according to claim 10, wherein the inclination direction of the (100) plane is a direction. On a compound semiconductor substrate having a surface orientation inclined with respect to the (100) plane, a cladding layer of a first conductivity type, an active layer, a first cladding layer of a second conductivity type, an etching stop layer, and a second A step of sequentially forming the second cladding layer of the conductive type and a step of etching the second cladding layer of the second conductive type to the middle using a dry etching technique except for a portion of the stripe ridge. And a step of forming at least one sidewall protective layer having different film thicknesses on both sides of the ridge on the ridge side of the ridge portion formed by the dry etching, and the second conductive type second using a wet etching technique. Further etching the clad layer until reaching the etch stop layer, forming a stripe ridge having a ridge side formed by the dry etching and a ridge side formed by the wet etching; At least a method for producing a, the ridge stripe type semiconductor laser device including a step of excluding a portion, and forming a current blocking layer on the step and the ridge to remove the group protecting the side wall layer. The cross-section perpendicular to the stripe direction of the ridge, wherein the sidewall protective layer formed on both sides of the ridge when the ridge is viewed from the ridge in a downward direction, The thickness of the sidewall protective layer formed on the right side of the ridge is smaller than the thickness of the sidewall protective layer formed on the left side of the ridge. The manufacturing method of the ridge stripe type semiconductor laser device according to claim 12, wherein in the wet etching step, etching is performed so that the (111) plane of the semiconductor constituting the second clad layer is exposed on at least a portion of the ridge side surface. The manufacturing method of the ridge stripe type semiconductor laser device according to claim 14, wherein in the wet etching step, the (111) surface is exposed to an area of at least 50% or more of the ridge side surfaces formed by the wet etching. The cross-section perpendicular to the stripe direction of the ridge, wherein the thickness of the two sidewall protective layers is thinner than the thickness of the two sidewall protective layers, ≥ the second clad of the second conductivity type in the wet etching process. The side etching amount of a layer) is a manufacturing method of a ridge stripe type semiconductor laser device. The manufacturing method of the ridge stripe type semiconductor laser device according to claim 12, wherein the inclination direction of the (100) plane is a direction.

Images