KR100853798B1 - Method of forming a metal line in semiconductor device - Google Patents

Method of forming a metal line in semiconductor device Download PDF

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KR100853798B1
KR100853798B1 KR1020070073394A KR20070073394A KR100853798B1 KR 100853798 B1 KR100853798 B1 KR 100853798B1 KR 1020070073394 A KR1020070073394 A KR 1020070073394A KR 20070073394 A KR20070073394 A KR 20070073394A KR 100853798 B1 KR100853798 B1 KR 100853798B1
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forming
film
semiconductor device
metal wiring
layer
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KR1020070073394A
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Korean (ko)
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백인철
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Abstract

A method for forming a metal line of a semiconductor device is provided to increase a metal line region and to reduce a line resistance of the metal line by using an Ru layer as a diffusion barrier. A first interlayer dielectric(12) is formed on a semiconductor substrate. A metal line(14) is formed on the first interlayer dielectric. A Ru layer(16) is formed on the metal line. A second interlayer dielectric is formed on the semiconductor substrate including the Ru layer. In the process for forming the Ru layer, the Ru layer is formed by using a Ru(EtCp)2 precursor. In the process for forming the Ru layer, the Ru layer is formed by using an ALD(Atomic Layer Deposition) method at the temperature of 100-300 °C.

Description

반도체 소자의 금속배선 형성방법{Method of forming a metal line in semiconductor device}Method of forming a metal line in semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체소자의 금속배선 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.

최근 들어, 반도체 장치의 크기가 점차 감소되면서 RC 딜레이를 감소시키기 위해 층간절연막으로 주로 저유전막을 사용한다. In recent years, as the size of a semiconductor device is gradually reduced, a low dielectric film is mainly used as an interlayer insulating film to reduce the RC delay.

이 저유전막이 반도체 장치 내에 형성되는 금속 배선과 인터그레이션(intergration)되는 경우가 발생하는 데, 이때, 저유전막으로 금속물질이 확산되어 금속배선간의 브릿지(bridge)를 야기하게 되고, 이는 소자의 정상적인 동작을 방해하게 된다. 따라서, 금속배선과 저유전막간의 확산을 방지하기 위해 확산방지막을 형성한다. When the low dielectric film is integrated with the metal wiring formed in the semiconductor device, a metal material is diffused into the low dielectric film, which causes a bridge between the metal wirings. It will interfere with normal operation. Therefore, a diffusion barrier film is formed to prevent diffusion between the metal wiring and the low dielectric film.

이때, 확산 방지막으로 SiN막을 사용할 경우, 절연물질인 SiN막의 두께만큼 금속배선이 형성될 영역이 감소하게 되고, 이로 인해 금속배선의 라인저항이 증가하게 됨으로써, 소자의 동작특성을 저하시키는 문제점이 있다. In this case, when the SiN film is used as the diffusion barrier, the area in which the metal wiring is to be formed is reduced by the thickness of the SiN film, which is an insulating material, and thus the line resistance of the metal wiring is increased, thereby degrading the operation characteristics of the device. .

상술한 문제점을 해결하기 위한 본 발명의 목적은 금속배선의 라인저항이 감소시켜 소자의 동작특성을 향상시킬 수 있도록 하는 반도체 소자의 금속배선 형성방법을 제공함에 있다. An object of the present invention for solving the above problems is to provide a method for forming a metal wiring of a semiconductor device to reduce the line resistance of the metal wiring to improve the operating characteristics of the device.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 형성방법은 반도체 기판 상에 제1 층간절연막을 형성하는 단계와, 상기 제1 층간 절연막 상에 금속배선을 형성하는 단계와, 상기 금속배선 상에 Ru막을 형성하는 단계와, 상기 Ru막이 형성된 기판 상에 제2 층간절연막을 형성하는 단계를 포함한다. According to an aspect of the present invention, there is provided a method of forming a metal interconnection of a semiconductor device, the method comprising: forming a first interlayer dielectric layer on a semiconductor substrate; forming a metal interconnection on the first interlayer dielectric layer; Forming a Ru film on the wiring; and forming a second interlayer insulating film on the substrate on which the Ru film is formed.

상기 Ru막을 형성하는 단계는 Ru(EtCp)2의 전구체를 이용하고, 100~ 300℃의 온도에서 ALD방법을 통해 형성한다. Forming the Ru film using a precursor of Ru (EtCp) 2 , it is formed by the ALD method at a temperature of 100 ~ 300 ℃.

상기 제1 층간 절연막은 산화막이고, 상기 제2 층간절연막은 저유전막이다. The first interlayer insulating film is an oxide film, and the second interlayer insulating film is a low dielectric film.

이상에서와 같이, 본 발명에 따른 반도체소자의 금속배선 형성방법에 있어서, 금속배선 상에만 형성되는 Ru막을 확산방지막으로 사용함으로써, 기존의 부도체인 SiN막을 확산방지막으로 사용할 때보다 금속배선이 형성될 영역이 증가하게 되어, 금속배선의 라인저항이 감소하게 되는 효과가 있다. As described above, in the method for forming the metal wiring of the semiconductor device according to the present invention, by using the Ru film formed only on the metal wiring as the diffusion barrier, metal wiring can be formed than when using the conventional non-conductor SiN film as the diffusion barrier. The area is increased, so that the line resistance of the metal wiring is reduced.

또한, 본 발명에 따른 반도체소자의 금속배선 형성방법에 있어서, 금속배선 상에만 형성되는 Ru막을 확산방지막으로 사용함으로써, 기존의 SiN막을 확산방지막으로 사용할 경우 수반되는 산화막 상에 형성된 확산방지막의 제거공정을 수행하지 않아도 되므로 공정단순화를 가져오는 효과가 있다. In addition, in the method for forming a metal wiring of a semiconductor device according to the present invention, by using a Ru film formed only on the metal wiring as a diffusion barrier, the step of removing the diffusion barrier formed on the oxide film accompanying the existing SiN film as a diffusion barrier Since it does not have to be carried out has the effect of bringing the process simplification.

이하, 첨부된 도면 및 실시 예를 통해 본 발명의 실시 예를 구체적으로 살펴보면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

상기와 같은 특징을 갖는 본 발명에 따른 반도체소자의 금속배선 형성방법에 대한 실시예를 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다. An embodiment of the method for forming metal wirings of a semiconductor device according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

도 1 내지 도 3은 본 발명에 따른 반도체 소자의 금속배선 형성방법을 순차적으로 도시한 공정 단면도들이다. 1 to 3 are cross-sectional views sequentially illustrating a method of forming metal wirings of a semiconductor device according to the present invention.

먼저, 도 1에 도시된 바와 같이, 게이트(미도시), 캐패시터(미도시) 및 금속 배선(미도시)과 같은 소정의 하부 구조가 형성된 기판(미도시) 전면에 제1 층간절연막인 산화막(12)을 형성한다. First, as shown in FIG. 1, an oxide film, which is a first interlayer insulating film, is formed on an entire surface of a substrate (not shown) on which a predetermined substructure such as a gate (not shown), a capacitor (not shown), and a metal wiring (not shown) are formed. 12) form.

이어, 제1 층간 절연막(12)이 형성된 기판 전면에 금속물질을 증착한 후, 상기 금속물질 상에 금속배선 형성용 포토레지스트 패턴을 형성한다. 그리고, 이를 마스크로 이용한 식각공정을 수행하여, 금속배선(14)을 형성한다. Subsequently, a metal material is deposited on the entire surface of the substrate on which the first interlayer insulating layer 12 is formed, and then a photoresist pattern for forming metal wirings is formed on the metal material. Then, an etching process using the same as a mask is performed to form the metal wiring 14.

다음, 도 2에 도시된 바와 같이, 상기 금속배선(14) 상에 확산방지막인 Ru막(16)을 형성한다. Next, as shown in FIG. 2, a Ru film 16 as a diffusion barrier film is formed on the metal wire 14.

상기 Ru막(16)은 Ru(EtCp)2의 전구체를 이용한 ALD(Atomic layer deposition)방법으로 형성한다. 이때, ALD방법은 300℃ 이하의 온도 즉, 100~ 300℃의 온도에서 수행되는 데, 이 온도에서 ALD방법이 수행되면, Ru(EtCp)2의 전구체가 산화막인 하부 층간절연막에는 증착되지 않고, 금속배선(14) 상에만 형성된다. The Ru film 16 is formed by an atomic layer deposition (ALD) method using a precursor of Ru (EtCp) 2 . At this time, the ALD method is performed at a temperature of 300 ° C. or lower, that is, 100 to 300 ° C. When the ALD method is performed at this temperature, the precursor of Ru (EtCp) 2 is not deposited on the lower interlayer insulating film, which is an oxide film. It is formed only on the metal wiring 14.

따라서, 금속배선 상에만 형성되는 Ru막을 확산방지막으로 사용함으로써, 기존의 절연물질인 SiN막을 확산방지막으로 사용할 때보다 금속배선이 형성될 영역이 증가하게 되어, 금속배선의 라인저항이 감소하게 된다. Therefore, by using the Ru film formed only on the metal wiring as the diffusion barrier, the area where the metal wiring is to be formed is increased, compared to when using the SiN film, which is a conventional insulating material, as the diffusion barrier, thereby reducing the line resistance of the metal wiring.

또한, 금속배선 상에만 형성되는 Ru막을 확산방지막으로 사용함으로써, 기존의 SiN막을 확산방지막으로 사용할 경우 수반되는 산화막 상에 형성된 확산방지막의 제거공정을 수행하지 않아도 되므로 공정단순화를 가져온다. In addition, since the Ru film formed only on the metal wiring is used as the diffusion barrier, it is not necessary to perform the step of removing the diffusion barrier formed on the oxide film when the existing SiN film is used as the diffusion barrier, thereby simplifying the process.

다음, 도 3에 도시된 바와 같이, 상기 확산방지막인 Ru막(16)이 형성된 결과물 상에 제2 층간절연막인 저유전막(18)을 형성함으로써, 본 공정을 완료한다. Next, as shown in FIG. 3, the low dielectric film 18, which is the second interlayer insulating film, is formed on the resultant product on which the Ru film 16, which is the diffusion barrier film, is formed, thereby completing this process.

이상에서 설명한 본 발명은 상술한 실시 예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 종래의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

도 1 내지 도 3은 본 발명에 따른 반도체 소자의 금속배선 형성방법을 순차적으로 도시한 공정 단면도1 to 3 are cross-sectional views sequentially illustrating a method of forming metal wirings of a semiconductor device according to the present invention.

＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

12, 18: 층간절연막 14: 금속배선12, 18: interlayer insulating film 14: metal wiring

16: 확산방지막16: diffusion barrier

Claims (4)

반도체 기판 상에 제1 층간절연막을 형성하는 단계와,Forming a first interlayer insulating film on the semiconductor substrate; 상기 제1 층간 절연막 상에 금속배선을 형성하는 단계와,Forming a metal wiring on the first interlayer insulating film; 상기 금속배선 상에 Ru막을 형성하는 단계와,Forming a Ru film on the metal wiring; 상기 Ru막이 형성된 기판 상에 제2 층간절연막을 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성방법. And forming a second interlayer insulating film on the substrate on which the Ru film is formed. 제1 항에 있어서, 상기 Ru막을 형성하는 단계는The method of claim 1, wherein the forming of the Ru film Ru(EtCp)2의 전구체를 이용하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법. A method for forming metal wiring in a semiconductor device, comprising using a precursor of Ru (EtCp) 2 . 제1 항에 있어서, 상기 Ru막을 형성하는 단계는The method of claim 1, wherein the forming of the Ru film 100~ 300℃의 온도에서 ALD방법을 통해 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법. Metal wiring forming method of a semiconductor device, characterized in that formed through the ALD method at a temperature of 100 ~ 300 ℃. 제1 항에 있어서, 상기 제1 층간 절연막은 산화막이고, 상기 제2 층간절연막은 저유전막인 것을 특징으로 하는 반도체소자의 금속배선 형성방법. The method of claim 1, wherein the first interlayer insulating film is an oxide film, and the second interlayer insulating film is a low dielectric film.
KR1020070073394A 2007-07-23 2007-07-23 Method of forming a metal line in semiconductor device KR100853798B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040096322A (en) * 2003-05-09 2004-11-16 매그나칩 반도체 유한회사 Method of forming metal line of semiconductor devices
KR100761467B1 (en) 2006-06-28 2007-09-27 삼성전자주식회사 Metal interconnection and method for forming the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040096322A (en) * 2003-05-09 2004-11-16 매그나칩 반도체 유한회사 Method of forming metal line of semiconductor devices
KR100761467B1 (en) 2006-06-28 2007-09-27 삼성전자주식회사 Metal interconnection and method for forming the same

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