KR100853467B1 - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to supply termination resistance stably by controlling target range due to level difference of two reference voltages. A reference voltage generation unit(100) generates a first and a second reference voltage. A switching unit(400) controls level difference between the first reference voltage and the second reference voltage in response to a plurality of switching control signals. A termination resistance control unit(200) supplies a plurality of code signals, when a feedback signal adjusted by the plurality of code signals is located between the first reference voltage and the second reference voltage in correspondence to an external resistance. A termination unit(300) supplies termination resistance corresponding to the plurality of code signals.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device including an on die termination circuit.

In general, various semiconductor devices implemented as integrated circuit chips such as CPUs, memories, and gate arrays are incorporated into various electrical products, such as personal computers, servers, or workstations. In most cases, the semiconductor device has a receiving circuit for receiving various signals transmitted from the outside world through an input pad and an output circuit for providing an internal signal to the outside through an output pad.

On the other hand, as the speed of operation of electrical products is increased, the swing width of signals interfaced between the semiconductor devices is gradually decreasing. The reason is to minimize the delay time for signal transmission. However, as the swing width of the signal decreases, the influence on external noise increases, and the reflection of the signal due to impedance mismatching (hereinafter referred to as mismatching) at the interface stage becomes more serious. The impedance mismatch occurs due to external noise, fluctuations in power supply voltage, change in operating temperature, change in manufacturing process, or the like. When impedance mismatching occurs, high-speed data transfer is difficult and output data output from the data output terminal of the semiconductor device may be distorted. Therefore, when the semiconductor device on the receiving side receives the distorted output signal to the input terminal, problems such as setup / hold fail or misjudgement of the input level may frequently occur.

Accordingly, the semiconductor device on the receiving side, which requires a high speed of operation, employs an impedance matching circuit called on-chip termination or on-die termination near a pad in the integrated circuit chip. Typically, in an on-die termination scheme, source termination is performed by an output circuit on the transmission side, and parallel termination is performed by a termination circuit connected in parallel to a receiver circuit connected to the input pad on the receiver side.

On the other hand, the concept of ZQ calibration is introduced from DDR3 SDRAM. When ZQC command is applied, the termination circuit has 240Ω resistance value connected to external pin. That is, a plurality of codes for controlling on / off switching of the termination circuit are calculated in response to the ZQC command to reflect the influence of the PVT fluctuation.

Such a semiconductor memory device will be described in detail with reference to the following drawings.

1 is a block diagram of a semiconductor memory device according to the prior art.

Referring to FIG. 1, a semiconductor memory device according to the related art includes a reference voltage generator 10 for generating first and second reference voltages VREF_A and VREF_B, and first and second code signals PCODE <0. : N>, the first and the second when the feedback signal adjusted by NCODE <0: N> is within the range of the first and second reference voltages VREF_A and VREF_B corresponding to the external resistance value ZQ. Termination resistance adjustment unit 20 for supplying two code signals PCODE <0: N> and NCODE <0: N>, and first and second code signals PCODE <0: N> and NCODE <0: And a termination part 30 for supplying a termination resistor corresponding to N>).

FIG. 2 is an internal circuit diagram of the reference voltage generator 10 shown in FIG. 1.

Referring to FIG. 2, the reference voltage generator 10 includes a plurality of resistors R1, R2, R3, R4, R5, R6, and R7 connected in series and each of the first and second voltages applied to both ends of the resistor R4. And output as second reference voltages VREF_A and VREF_B.

3 is a diagram illustrating a level change of a feedback signal according to the driving of the semiconductor memory device illustrated in FIGS. 1 and 2. This will be described in detail with reference to the driving.

As shown in FIG. 3, the reference voltage generator 10 outputs the first and second reference voltages VREF_A and VREF_B. At this time, the level difference between the first and second reference voltages VREF_A and VREF_B becomes a target range.

Subsequently, the termination resistance adjustment unit 20 adjusts the first code signal PCODE <0: N> so that the first feedback signal FD_ZQ corresponds to the external resistance value ZQ. 2 Set it within the target range of the reference voltages VREF_A and VREF_B.

In other words, while the first feedback signal FD_ZQ has a higher level than the first and second reference voltages VREF_A and VREF_B, the termination resistance value adjusting unit 20 performs the first code signal PCODE <0: N>. ) Is counted down so that the level of the first feedback signal FD_ZQ decreases. Subsequently, when the first feedback signal FD_ZQ is within the target range, the first code signal PCODE <0: N> is supplied to the termination unit 30.

In addition, although not shown in the drawing, when the first code signal PCODE <0: N> is set, the termination resistance adjusting unit 20 is driven as described above, and the second code signal NCODE <0: N>). That is, the second feedback signal NCAL_DQ adjusted by the second code signal NCODE <0: N> corresponds to the resistance value of the first code signal PCODE <0: N>. The second code signal NCODE <0: N> at a point in time within the range of the reference voltages VREF_A and VREF_B is supplied.

Finally, the termination unit 30 supplies resistors corresponding to the first and second code signals PCODE <0: N> and NCODE <0: N> to the corresponding pads.

However, when the target range is greater than or less than the change width of the level of the first feedback signal FD_ZQ due to one bit adjustment of the first code signal PCODE <0: N>, the first code signal PCODE <0 There is a problem that: N>) is not set. This occurs even when the second code signal NCODE <0: N> is generated. As such, when the first and second code signals PCODE <0: N> and NCODE <0: N> are not set, the termination unit 30 may not supply a resistor.

On the other hand, it looks at the following drawings with respect to the above problem.

4A is a diagram illustrating a waveform diagram of the prior art in the case where a change in level of a feedback signal is larger than a target range.

As shown in FIG. 4A, when the level change width of the first feedback signal FD_ZQ is larger than the target range, the first feedback signal FD_ZQ may be oscillated and may not be stabilized to a constant level.

Specifically, when the first feedback signal FD_ZQ is greater than the first and second reference voltages VREF_A and VREF_B, the first code signal PCODE <0: N> is down counted to form the first feedback signal. Let the voltage level of (FD_ZQ) fall. In addition, when the first feedback signal FD_ZQ is smaller than the first and second reference voltages VREF_A and VREF_B, the first code signal PCODE <0: N> may be down counted to form the first feedback signal FD_ZQ. Allow the voltage level of to rise.

Therefore, when the first code signal PCODE <0: N> is counted down one bit, the voltage level of the first feedback signal FD_ZQ is smaller than the first and second reference voltages VREF_A and VREF_B, and the first code When the signal PCODE <0: N> is counted up one bit, the voltage level of the first feedback signal FD_ZQ is greater than the first and second reference voltages VREF_A and VREF_B. Since the first feedback signal FD_ZQ does not have a stable level, the first code signal PCODE <0: N> repeatedly performs up counting and down counting, and thus does not have a stable value.

FIG. 4B is a diagram illustrating a waveform diagram of the related art in a case where a change width of a level of a feedback signal is relatively smaller than that of FIG. 3.

As shown in FIG. 4B, the first and second feedback signals FD_ZQ and NCAL_DQ are stably located within the target range, but the accuracy is low.

As such, in order to eliminate the problem that the target range is relatively too large or too small, the prior art includes a metal option or the like. However, in order to adjust the spacing of the target range by the metal option, etc., the re-modification process of changing the metal layer is required, so that the manufacturing process takes a long time.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of stably supplying a termination resistance by adjusting a target range due to a level difference between two reference voltages. .

According to an aspect of the present invention, there is provided a semiconductor memory device comprising: reference voltage generating means for generating first and second reference voltages; Switching means for adjusting a level difference between the first reference voltage and the second reference voltage in response to a plurality of switching control signals; Termination resistance value adjusting means for supplying said plurality of code signals at a point in time at which a feedback signal adjusted by a plurality of code signals is located between said first and second reference voltages corresponding to an external resistance value; And termination means for supplying termination resistors corresponding to the plurality of code signals.

According to another aspect of the present invention, a semiconductor memory device may include: reference voltage generating means for generating first and second reference voltages; First switching means for adjusting a level difference between the first reference voltage and the second reference voltage in response to a plurality of range control signals; Second switching means for adjusting voltage levels of the first and second reference voltages in response to a plurality of level control signals; Termination resistance value adjusting means for supplying the plurality of code signals at a point in time at which the feedback signal adjusted by the plurality of code signals is located between the first and second reference voltages corresponding to an external resistance value; And termination means for supplying termination resistors corresponding to the plurality of code signals.

The present invention described above can adjust the target range, which is the level difference between the two reference voltages, and can stably supply the termination resistor. Therefore, the reliability of the semiconductor memory device including the same is improved.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

5 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

Referring to FIG. 5, a semiconductor memory device according to the present invention may include a control signal generator 500 for outputting a plurality of switching control signals TM_REF1, TM_REF2, TM_REF3, and TM_REF4 in response to test signals TM1 and TM2. The reference voltage generator 100 for generating the first and second reference voltages VREF_A and VREF_B, and the level difference between the first reference voltage and the second reference voltages VREF_A and VREF_B may be used to generate a plurality of switching control signals ( The switching unit 400 for adjusting in response to the TM_REF1, TM_REF2, TM_REF3, TM_REF4, and the feedback signal adjusted by the first and second code signals PCODE <0: N> and NCODE <0: N> The first and second code signals PCODE <0: N> and NCODE <0: N> at a point in time within the range of the first and second reference voltages VREF_A and VREF_B corresponding to the external resistance value ZQ. Termination resistance adjusting unit 200 for supplying the power supply, and termination unit 300 for supplying the termination resistance corresponding to the first and second code signals (PCODE <0: N>, NCODE <0: N>) ).

Here, the connection relationship between the reference voltage generator 100 and the switching unit 400 will be described.

The reference voltage generator 100 includes a plurality of resistors connected in series and outputs voltages across the four resistors as the first and second reference voltages VREF_A and VREF_B. That is, the reference voltage generator 100 includes a first resistor string including a plurality of resistors R1, R2, and R3 disposed in series between the supply terminal of the external voltage and the node A, and disposed in series between the node A and the node B. A second resistor string including a plurality of resistors R4_1, R4_2, R4_3, and R4_4, and a third resistor string including a plurality of resistors R5, R6, and R7 disposed in series between the node B and the supply terminal of the ground voltage. And a voltage applied to the node A as the first reference voltage VREF_A, and a voltage applied to the node B as the second reference voltage VREF_B. Here, the second resistor string disposed between the node A and the node B includes the first resistor R4_1 connected between the node A and the node N1, the second resistor R4_2 connected between the nodes N1 and N2, and the node. The third resistor R4_3 connected between N2 and node N3 and the fourth resistor R4_4 connected between node N3 and node B are disposed.

In addition, the switching unit 400 is connected to the nodes A, N1, N2, N3, and B of the four resistors positioned in the second resistor string in which the first and second reference voltages VREF_A and VREF_B are output. Four switches SW1, SW2, SW3, and SW4 switched by the first to fourth switching control signals TM_REF1, TM_REF2, TM_REF3, and TM_REF4 are included. In other words, the switching unit 400 may switch the node A and the node N1 in response to the first switching control signal TM_REF1 and the node N1 in response to the second switching control signal TM_REF2. And the second switch SW2 for switching the node N2, the third switch SW3 for switching the node N2 and the node N3 in response to the third switching control signal TM_REF3, and the fourth switching control signal TM_REF4. In response, a fourth switch SW4 for switching between node N3 and node B is included.

Meanwhile, the process of adjusting the level difference between the first and second reference voltages VREF_A and VREF_B of the reference voltage generator 100 according to the driving of the switching unit 400 will be described.

First, when all of the first to fourth switching control signals TM_REF1, TM_REF2, TM_REF3, and TM_REF4 are deactivated to the logic level 'L', the first to fourth switches SW1, SW2, SW3, and SW4 are turned off. Therefore, the first and second reference voltages VREF_A and VREF_B supplied by the reference voltage generator 100 have a level difference as much as resistance drops caused by the resistors R4_1, R4_2, R4_3, and R4_4.

In addition, when only the first switching control signal TM_REF1 is activated at the logic level 'H', the first switch SW1 is turned on, so that the resistors R4_2, R4_3, and R4_4 are connected between the node A and the node B. Therefore, the first and second reference voltages VREF_A and VREF_B supplied by the reference voltage generator 100 have a level difference as much as resistance drops caused by the resistors R4_2, R4_3, and R4_4. That is, it can be seen that the voltage loss caused by the resistor R4_1 is reduced, so that the target range is reduced.

In addition, when the first and second switching control signals TM_REF1 and TM_REF2 are activated to the logic level 'H', the first and second switches SW1 and SW2 are turned on, so that the resistors R4_3, R4_4 is the same as connected. Therefore, the first and second reference voltages VREF_A and VREF_B supplied by the reference voltage generator 100 have a level difference as much as the resistance drops caused by the resistors R4_3 and R4_4. That is, it can be seen that the voltage loss caused by the resistors R4_1 and R4_2 is reduced, so that the target range is reduced.

The change in the target range according to the activation of the first to fourth switching control signals TM_REF1, TM_REF2, TM_REF3 and TM_REF4 is as described above.

Therefore, the present invention includes a plurality of resistor strings R4_1, R4_2, R4_3, and R4_4 between nodes to which the first and second reference voltages VREF_A and VREF_B are supplied in the reference voltage generator 100, and the switching unit Select through 400. Accordingly, the level difference between the first and second reference voltages VREF_A and VREF_B may be adjusted by applying the first to fourth switching control signals TM_REF1, TM_REF2, TM_REF3, and TM_REF4. That is, the target range can be adjusted as needed. In addition, through the fuse option, the first to fourth switching control signals TM_REF1, TM_REF2, TM_REF3, and TM_REF4 may be kept constant. Therefore, the target range can be adjusted by the level difference between the two reference voltages, thereby eliminating the problem of the oscillation of the first and second code signals PCODE <0: N> and NCODE <0: N>.

For reference, the switching unit 400 of the present invention may further include a plurality of switches in the connection node of the plurality of resistors in the first resistor string or the third resistor string. As described above, when the switching unit is further provided outside the second resistor string, the voltage level of each of the first and second reference voltages can be adjusted. For example, if a switch is further included across each of the resistors R1, R2, and R3 in the first row of resistors, the resistor is turned off by the turned-on switch. When the resistor R1 is excluded, the total resistance value of the first resistor string is reduced, so that the levels of the first reference voltage and the second reference voltage are increased. Therefore, when the first or third resistor string, that is, the switching unit is further included outside the nodes A and B where the reference voltages VREF_A and VREF_B are output, the voltages of the first and second reference voltages VREF_A and VREF_B are included. You can adjust the level.

FIG. 6 is an internal circuit diagram of the termination resistance adjusting unit 200 shown in FIG. 5.

Referring to FIG. 6, in the termination resistance adjusting unit 200, the first feedback signal FD_ZQ adjusted by the first code signal PCODE <0: N> corresponds to the first and second resistance values ZQ. The first code signal generator 210 for supplying the first code signal PCODE <0: N> at a point in time within the range of the second reference voltages VREF_A and VREF_B, and the second code signal NCODE < Range of the first and second reference voltages VREF_A and VREF_B in response to the second feedback signal NCAL_DQ adjusted by 0: N> corresponding to the resistance value of the first code signal PCODE <0: N>. And a second code signal generator 250 for supplying a second code signal NCODE <0: N> at a point in time.

The first code signal generator 210 divides an external voltage into a resistance value and an external resistance value ZQ by the first code signal PCODE <0: N> and outputs the external voltage as the first feedback signal FD_ZQ. And a first level detector 232 for detecting a level difference between the first reference voltage VREF_A and the first feedback signal FD_ZQ, and a second reference voltage VREF_B. The first code signal PCODE <0: in response to the output of the second level detector 234 and the first and second level detectors 232 and 234 for detecting the level difference of the feedback signal FD_ZQ. N>) and a first code generation unit 240 for generating.

The second code signal generator 250 divides the external voltage into a resistance value of the first code signal PCODE <0: N> and a resistance value of the second code signal NCODE <0: N>. A second feedback unit 260 for outputting the second feedback signal NCAL_DQ, a third level detector 272 for detecting a level difference between the first reference voltage VREF_A and the second feedback signal NCAL_DQ; And responding to outputs of the fourth level detector 274 and the third and fourth level detectors 272 and 274 for detecting a level difference between the second reference voltage VREF_B and the second feedback signal NCAL_DQ. And a second code generator 280 for generating a second code signal NCODE <0: N>.

Next, the driving of the termination resistance adjustment unit 200 will be described briefly.

First, the first feedback unit 220 divides an external voltage into a resistance value of the first code signal PCODE <0: N> and an external resistance value ZQ, and outputs the external voltage as the first feedback signal FD_ZQ.

Subsequently, the first and second level detectors 232 and 234 respectively determine whether the first feedback signal FD_ZQ has a lower level than the first reference voltage VREF_A or the second reference voltage VREF_B or a higher level. Sense if you have

Subsequently, in response to the results of the first and second level detectors 232 and 234, the first code generator 240 may have the first feedback signal FD_ZQ greater than the first and second reference voltages VREF_A and VREF_B. If high, the first code signal PCODE <0: N> is down counted.

Subsequently, an external voltage is divided into a resistance value and an external resistance value ZQ according to the newly set first code signal PCODE <0: N> and output as a first feedback signal FD_ZQ. The sensing units 232 and 234 are driven. In addition, the first code generator 240 down or up counts the first code signal PCODE <0: N> in response to the first and second level detectors 232 and 234.

The above-described process is repeatedly performed until the first feedback signal FD_ZQ is located between the voltage levels of the first and second reference voltages VREF_A and VREF_B.

Meanwhile, the second code signal generator 250 has the same driving as the first code signal generator 210 as described above. However, instead of the external resistance value ZQ, the external voltage is divided by the resistance value of the first code signal PCODE <0: N> and the resistance value of the second code signal NCODE <0: N>. The only difference is that the feedback signal NCAL_DQ is generated. Therefore, detailed description thereof will be omitted.

Next, the driving of the semiconductor memory device shown in FIGS. 5 and 6 will be described.

First, the reference voltage generator 100 generates the first and second reference voltages VREF_A and VREF_B. In this case, the switching unit 400 may turn on or turn off the first to fourth switches SW1, SW2, SW3, and SW4 according to the logic levels of the first to fourth switching control signals TM_REF1, TM_REF2, TM_REF3, and TM_REF4. do. Therefore, the level difference between the first and second reference voltages VREF_A and VREF_B supplied by the reference voltage generator 100 is the same as the voltage drop caused by the resistance of the switches not disposed on both resistors.

Subsequently, the first code signal generator 210 may control the first and second feedback signals FD_ZQ adjusted by the first code signal PCODE <0: N> to correspond to the external resistance value ZQ. The first code signal PCODE <0: N> at a point in time within the range of the reference voltages VREF_A and VREF_B is supplied. In addition, the second code signal generator 250 has a resistance of the second feedback signal NCAL_DQ adjusted by the second code signal NCODE <0: N> due to the first code signal PCODE <0: N>. The second code signal NCODE <0: N> is supplied at a point in time within the range of the first and second reference voltages VREF_A and VREF_B corresponding to the value.

Subsequently, the termination unit 300 provides termination resistors corresponding to the first and second code signals PCODE <0: N> and NCODE <0: N> to the corresponding pads.

Therefore, the above-described present invention can adjust the level difference between the first and second reference voltages VREF_A and VREF_B through the test signal. Therefore, the level difference between the first and second reference voltages VREF_A and VREF_B is not appropriate, so that the first and second code signals PCODE <0: N> and NCODE <0: N> are stably generated. This solves the problem of not being able to supply the termination resistor. In addition, after the test, the fuse option can be cut to continuously set the desired level difference.

The apparatus may further include a switching unit to adjust the voltage level of each reference voltage as well as the level difference between the first and second reference voltages VREF_A and VREF_B.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1 is a block diagram of a semiconductor memory device according to the prior art.

FIG. 2 is an internal circuit diagram of the reference voltage generator shown in FIG. 1. FIG.

3 is a diagram illustrating a level change of a feedback signal according to the driving of the semiconductor memory device shown in FIGS. 1 and 2.

4A is a diagram showing a waveform diagram of the prior art in the case where a change in level of a feedback signal is larger than a target range.

4B is a diagram illustrating a waveform diagram of the related art in the case where a change in level of a feedback signal is relatively smaller than that of FIG. 3.

5 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

FIG. 6 is an internal circuit diagram of the termination resistance adjustment unit shown in FIG. 5. FIG.

* Explanation of symbols for the main parts of the drawings

100: reference voltage generator

200: termination resistance adjustment unit

300 termination

400: switching unit

500: control signal generator

Claims (21)

Reference voltage generating means for generating first and second reference voltages; Switching means for adjusting a level difference between the first reference voltage and the second reference voltage in response to a plurality of switching control signals; Termination resistance value adjusting means for supplying said plurality of code signals at a point in time at which a feedback signal adjusted by a plurality of code signals is located between said first and second reference voltages corresponding to an external resistance value; And Termination means for supplying termination resistors corresponding to the plurality of code signals A semiconductor memory device having a. The method of claim 1, The reference voltage generating means, A first resistor string in which a plurality of resistors are disposed in series between the supply terminal of the power supply voltage and the first node; A second resistor string in which a plurality of resistors are disposed in series between the first node and the second node; A third resistor string including a plurality of resistors disposed in series between the second node and a supply terminal of a ground voltage; Outputting a voltage across the first node as the first reference voltage and a voltage across the second node as a second reference voltage A semiconductor memory device characterized in that. The method of claim 2, The switching means, A plurality of switches connected between the connection nodes of the plurality of resistors in the second row of resistors and for switching each node in response to the switching control signal; A semiconductor memory device characterized in that. The method of claim 3, The second row of resistance, A first resistor connected between the first node and a third node, A second resistor connected between the third node and a fourth node; A third resistor connected between the fourth node and the fifth node, A fourth resistor connected between the fifth node and the second node is disposed A semiconductor memory device characterized in that. The method of claim 4, wherein The switching means, A first switch for switching between the first node and the third node in response to a first switching control signal; A second switch for switching between the third node and the fourth node in response to a second switching control signal; A third switch for switching between the fourth node and the fifth node in response to a third switching control signal; And a fourth switch for switching the fifth node and the second node in response to a fourth switching control signal. A semiconductor memory device characterized in that. The method of claim 5, Control signal generating means for generating the plurality of switching control signals in response to a plurality of test signals or fuse options Containing more  A semiconductor memory device characterized in that. The method of claim 6, The termination resistance value adjusting means, A first feedback signal for supplying the plurality of first code signals when the first feedback signal adjusted by the plurality of first code signals is within a range of the first and second reference voltages corresponding to the external resistance value; 1 code signal generator, The second plurality of second feedback signals adjusted by a plurality of second code signals are located within a range of the first and second reference voltages corresponding to resistance values of the plurality of first code signals; Comprising a second code signal generator for supplying a code signal A semiconductor memory device characterized in that. The method of claim 7, wherein The first code signal generator, A first feedback unit for dividing an external voltage into a resistance value of the plurality of first code signals and the external resistance value and outputting the external voltage as the first feedback signal; A first level detector for detecting a level difference between the first reference voltage and the first feedback signal; A second level detector for detecting a level difference between the second reference voltage and the first feedback signal; And a first code generator configured to generate the plurality of first code signals in response to outputs of the first and second level detectors. A semiconductor memory device characterized in that. The method of claim 8, The second code signal generator, A second feedback unit for dividing an external voltage into resistance values by the plurality of first code signals and resistance values by the plurality of second code signals and outputting the external voltage as the second feedback signal; A third level detector configured to detect a level difference between the first reference voltage and the second feedback signal; A fourth level detector for detecting a level difference between the second reference voltage and the second feedback signal; And a second code generator for generating the plurality of second code signals in response to the outputs of the third and fourth level detectors. A semiconductor memory device characterized in that. Reference voltage generating means for generating first and second reference voltages; First switching means for adjusting a level difference between the first reference voltage and the second reference voltage in response to a plurality of range control signals; Second switching means for adjusting voltage levels of the first and second reference voltages in response to a plurality of level control signals; Termination resistance value adjusting means for supplying said plurality of code signals at a point in time at which a feedback signal adjusted by a plurality of code signals is located between said first and second reference voltages corresponding to an external resistance value; And Termination means for supplying termination resistors corresponding to the plurality of code signals A semiconductor memory device having a. The method of claim 10, The reference voltage generating means, A first resistor string in which a plurality of resistors are disposed in series between the supply terminal of the power supply voltage and the first node; A second resistor string in which a plurality of resistors are disposed in series between the first node and the second node; A third resistor string including a plurality of resistors disposed in series between the second node and a supply terminal of a ground voltage; Outputting a voltage across the first node as the first reference voltage and a voltage across the second node as a second reference voltage A semiconductor memory device characterized in that. The method of claim 11, The first switching means, A plurality of switches connected between the connection nodes of the plurality of resistors in the second resistor row and for switching each node in response to the plurality of range control signals; A semiconductor memory device characterized in that. The method of claim 12, The second switching means, A plurality of switches connected between connection nodes of a plurality of resistors in the first resistor string or the third resistor string, and for switching each node in response to the plurality of level control signals; A semiconductor memory device characterized in that. The method of claim 13, The first resistor string includes first to third resistors disposed in series between the supply terminal of the power supply voltage and the first node. The second row of resistors includes fourth to sixth resistors disposed in series between the first node and the second node. The third resistor string includes seventh to ninth resistors disposed in series between the second node and a supply terminal of a ground voltage; A semiconductor memory device characterized in that. The method of claim 14, The first switching means, A first switch for switching both nodes of the fourth resistor in response to a first range control signal; A second switch for switching both nodes of the fifth resistor in response to a second range control signal; And a third switch for switching both nodes of the sixth resistor in response to a third range control signal. A semiconductor memory device characterized in that. The method of claim 15, The second switching means, A fourth switch for switching both nodes of the first resistor in response to a first level control signal; A fifth switch for switching both nodes of the second resistor in response to a second level control signal; And a sixth switch for switching both nodes of the third resistor in response to a third level control signal. A semiconductor memory device characterized in that. The method of claim 16, The second switching means, A seventh switch for switching both nodes of the seventh resistor in response to a fourth level control signal; An eighth switch for switching both nodes of the eighth resistor in response to a fifth level control signal; And a ninth switch for switching both nodes of the ninth resistor in response to a sixth level control signal. A semiconductor memory device characterized in that. The method of claim 17, Control signal generation means for generating the plurality of range control signals and the plurality of level control signals in response to a plurality of test signals or fuse options Containing more  A semiconductor memory device characterized in that. The method of claim 18, The termination resistance value adjusting means, A first feedback signal for supplying the plurality of first code signals when the first feedback signal adjusted by the plurality of first code signals is within a range of the first and second reference voltages corresponding to the external resistance value; 1 code signal generator, The second plurality of second feedback signals adjusted by a plurality of second code signals are located within a range of the first and second reference voltages corresponding to resistance values of the plurality of first code signals; Comprising a second code signal generator for supplying a code signal A semiconductor memory device characterized in that. The method of claim 19, The first code signal generator, A first feedback unit for dividing an external voltage into a resistance value of the plurality of first code signals and the external resistance value and outputting the external voltage as the first feedback signal; A first level detector for detecting a level difference between the first reference voltage and the first feedback signal; A second level detector for detecting a level difference between the second reference voltage and the first feedback signal; And a first code generator configured to generate the plurality of first code signals in response to outputs of the first and second level detectors. A semiconductor memory device characterized in that. The method of claim 20, The second code signal generator, A second feedback unit for dividing an external voltage into resistance values by the plurality of first code signals and resistance values by the plurality of second code signals and outputting the external voltage as the second feedback signal; A third level detector configured to detect a level difference between the first reference voltage and the second feedback signal; A fourth level detector for detecting a level difference between the second reference voltage and the second feedback signal; And a second code generator for generating the plurality of second code signals in response to the outputs of the third and fourth level detectors. A semiconductor memory device characterized in that.

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