KR100849508B1

KR100849508B1 - Dual port memory having bypass structure

Info

Publication number: KR100849508B1
Application number: KR1020070019752A
Authority: KR
Inventors: 임영훈; 하지태
Original assignee: 엠텍비젼 주식회사
Priority date: 2007-02-27
Filing date: 2007-02-27
Publication date: 2008-07-31

Abstract

A dual port memory having a bypass structure is provided to control an internal bus of other processors without any external bus line by using the bypass structure and reduce a system mounting area by removing the external bus line. A memory cell array(236-240) includes a shared memory area(238). A first memory interface(232) performs a data read or write operation in the shared memory area based on an address and a command received from a first processor(200) through a first port(222). A second memory interface(234) performs the data read or write operation in the shared memory area based on the address and the command received from a second processor(210) through a second port(224). A first bypass unit(250) bypasses an internal bus control signal received from the first processor. A second bypass unit(252) bypasses the internal bus control signal received from the second processor. The internal bus control signal includes at least one of the internal bus control command, the address, and the data read or written by the internal bus control command of the second processor. The internal bus control command includes at least one of a chip select signal, a write enable signal, and a read enable signal.

Description

Dual port memory having bypass structure

1 is a diagram illustrating a configuration of a dual port memory system according to the prior art.

2 is a diagram showing the configuration of a dual port memory system according to a first preferred embodiment of the present invention.

3 is a diagram showing a detailed bypass configuration according to the first embodiment of the present invention;

4 is a diagram showing the detailed configuration of the bypass unit according to the first embodiment of the present invention.

5 is a diagram showing the configuration of a dual port memory system according to a second embodiment of the present invention;

6 is a diagram showing a detailed bypass configuration according to a second embodiment of the present invention;

7 is a diagram showing the detailed configuration of the bypass unit according to the second embodiment of the present invention.

8 is a diagram showing the configuration of a dual port memory system according to a third embodiment of the present invention;

The present invention relates to a dual port memory having a bypass structure and a system including the same. More specifically, a dual port capable of transmitting and receiving signals for controlling an internal bus between processors connected to dual port memory without a separate external line. It's about memory.

Recently, portable terminals such as mobile phones and PDAs (Personal Digital Assistants) include various additional functions such as digital cameras, video phones, and multimedia data playback in addition to mobile communication functions such as voice calls.

The portable terminal is provided with a modem processor for processing the original functions of the mobile communication and an application processor for processing various applications.

In addition, in general, a portable terminal having two processors performs data transmission and reception between the two processors at a high speed, thereby improving the processing performance of the system and reducing the memory footprint of the dual port memory (particularly dual port SDRAM). ) Is used.

In other words, when two processors use dual port memory, each processor can use its port to access the shared memory area to read and write data, resulting in faster data transfer and processing speeds, resulting in overall system Performance is improved.

1 is a diagram illustrating a configuration of a dual port memory system according to the related art.

Referring to FIG. 1, each processor 100, 104 is connected to a dual port Synchronous Dynamic Random Access Memory 108 via a respective external bus interface 102, 106.

Dual-port SDRAM 108 is a shared memory area in which two processors each independently write or read, and a share in which two processors jointly access to write or read. It includes a memory area.

Each processor 100, 104 accesses the shared memory area after obtaining rights from the dual port SDRAM 108 if it wishes to access the shared memory area.

The dual port SDRAM 108 utilizes a semaphore 110 to ensure mutual exclusive access of each processor to the shared memory area and to ensure synchronized work between each processor.

The semaphore processing unit 110 determines whether or not access to the predetermined shared memory area (permission or not) is performed based on the current state of the predetermined shared memory area (eg, '0' or '1'). By providing each processor 100, 104 mutually exclusively so that each processor has mutually exclusive access to a given shared memory area.

After the authorization is obtained, each of the processors 100 and 104 transmits an SDRAM command and an address to the dual port SDRAM 108, outputs data to the dual port SDRAM 108 in the write mode, and reads from the dual port SDRAM 108 in the read mode. Received data.

Each processor (100,104) connected to the dual-port SDRAM 108 according to the prior art allows a counterpart processor to execute a predetermined operation by writing or reading data to a shared memory area, which is a process for each processor (100,104) to acquire and release rights. Because of the need to repeat the inefficient problem.

Meanwhile, according to the related art, when the first processor 100 transmits / receives a signal for controlling the internal bus to the second processor 104, as shown in FIG. 1, a host interface (HPI) 112 is shown. And a separate signal line 114 for transmitting and receiving commands, addresses and data.

For example, when the first processor 100 is a main processor (eg, a modem processor) and the second processor 104 is an application processor for processing various applications, the main processor 100 is an application processor. Command and address signals are sent to the host interface 112 via a command line and an address line included in separate signal lines 114 to boot 104 and allow the application processor 104 to perform certain operations. It transmits and inputs and outputs data through the data line included in the signal line 114.

However, when the separate signal line 114 is provided as described above, since each processor connected to the dual port SDRAM 108 transmits and receives a predetermined signal using an external line, system performance is degraded and the number of hardware wires is increased externally. There was a problem that the system mounting area is large.

In the present invention, to solve the problems of the prior art as described above, it is proposed a dual port memory having a bypass structure that can control the internal bus of the counterpart processor without a separate external signal line.

It is another object of the present invention to provide a dual port memory having a bypass structure that can reduce the system mounting area by eliminating external signal lines.

In order to achieve the above object, according to a preferred embodiment of the present invention, a memory cell array having a shared memory region; A first memory interface configured to perform a write or read operation of data to the shared memory area based on an address and a command provided through a first port from a first processor; A second memory interface configured to write or read data to the shared memory area based on an address and a command provided from a second processor through a second port; A first bypass unit bypassing an internal bus control signal received from the first processor; And a second bypass unit configured to transfer the bypassed internal bus control signal to the second processor.

According to another aspect of the invention, a memory cell array having a shared memory region; A first memory interface configured to perform a write or read operation of data to the shared memory area based on an address and a command provided through a first port from a first processor; A second memory interface configured to write or read data to the shared memory area based on an address and a command provided from a second processor through a second port; A first bypass unit bypassing a first internal bus control signal received from the first processor and transferring a second internal bus control signal received from the second processor to the first processor; And a second bypass unit configured to bypass the second internal bus control signal received from the second processor to the first bypass unit and to transfer the first internal bus control signal to the second processor. Dual port memory is provided.

According to another aspect of the invention, a memory cell array having a shared memory region; A first memory interface configured to perform a write or read operation of data to the shared memory area based on an address and a command provided through a first port from a first processor; A second memory interface configured to write or read data to the shared memory area based on an address and a command provided from a second processor through a second port; A first bypass unit bypassing an internal bus control signal received from a third processor corresponding to the host; And a second bypass unit configured to transfer the bypassed internal bus control signal to a fourth processor side corresponding to a slave.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, the same reference numerals will be used for the same means regardless of the reference numerals in order to facilitate the overall understanding.

2 is a diagram illustrating a configuration of a dual port memory system according to a first embodiment of the present invention.

As shown in FIG. 2, the dual port memory system according to the present invention may include a first processor 200, a second processor 210, and a dual port memory 220.

The first and second processors 200 and 210 are units for decoding and executing instructions, and the first processor 200 may be a modem processor used in a portable terminal such as a mobile phone, and the second processor 210 may be a portable terminal. It may be an application processor for performing an application such as a video processor, a multimedia processor used in the.

Hereinafter, a description will be made based on the connection of two processors to a dual port memory according to the present invention, but the present invention is not limited thereto.

The first processor 200 is connected to the dual port memory 220 through a first external bus interface (EBI) 202.

The dual port memory 220 may be a dual port SDRAM having a DRAM cell structure. Hereinafter, the dual port memory 220 is described as a dual port SDRAM, but is not necessarily limited thereto.

The first EBI 202 serves as a memory controller. When the first EBI 202 is connected to the dual port memory 220 configured as the SDRAM as in the present invention, the first EBI 202 may share the functions of the SRAM as well as the SDRAM.

In this case, the first EBI 202 informs the application of the chip select signal (Chip Select, / CS), the low strobe signal (Row ADDRress Strobe, / RAS), and the column address to activate the DRAM operation corresponding to the SDRAM command. Column strobe signal (Column ADDRress Strobe (/ CAS)), write enable signal (Write Enable, / WE) to determine data write or read, output enable signal (Ouput Enable, / OE) to determine data input and output, and clock An enable signal CKE may be output, but a chip select signal (Chip Select, / CS), a write enable signal (Write Enable, / WE), and a read enable signal (Read Enable,) corresponding to an SRAM command may be output. / RE) (the lead enable signal may correspond to the above output enable signal).

Therefore, the first EBI 202 according to the first embodiment of the present invention uses the same interface as the SRAM external interface, but the unit memory cell structure has the unit memory cell structure of DRAM, and includes a refresh circuit (PSRAM) having a refresh circuit. It may be an external interface.

In the following description, the first EBI 202 is a PSRAM external interface capable of outputting both an SDRAM command and an SRAM command, but is not necessarily limited thereto.

Meanwhile, a second external bus interface EBI 212 may be provided on the second processor 210 to output a command, an address, and input / output data to the dual port memory 220.

According to the first preferred embodiment of the present invention, an internal bus control signal transmitted from a counterpart processor while sharing only the dual port memory 220 without using a separate signal line on the second processor 210 side (for internal bus control). Internal Bus Interface (IBI) 214 is provided that can receive commands, addresses, and the like.

As described above, the first EBI 202 connected to the first processor 200 may output not only an SDRAM command but also an SRAM command. According to a preferred embodiment of the present invention, / CS, / WE and / RE An SRAM command including a may be used as a signal for controlling an internal bus of the second processor 210.

In this case, the IBI 214 connected to the second processor 210 receives a command, an address, etc. for controlling an internal bus transmitted from the first processor 200 and transmits the received command to the second processor 210. Here, the internal bus interface 214 may have the same configuration as a conventional host interface.

Such an internal bus interface separate from the second EBI 212 is provided because a general external bus interface has only a command and an address output function, and cannot receive a command received from a counterpart processor for internal bus control.

For example, when the first processor 200 is a main processor (baseband chip processor) used in a mobile communication terminal and the second processor 210 is an application processor, the second processor 210 may provide an internal bus control signal. In this case, the first processor 200 may boot the second processor 210 or the second processor 210 may execute another operation.

The IBI 214 may be configured as a single chip with the second processor 210 and the second EBI 212. The IBI 214 may be configured as a separate chip capable of receiving SRAM commands, addresses, etc. without being limited thereto. It may be.

As described above, the dual port memory 220 according to the present invention is provided with a bypass structure in order to transmit signals for controlling the internal bus without passing through a separate external line.

As shown in FIG. 2, the dual port memory 220 according to the present invention is connected to the first processor 200 having the first EBI 202 through the first port 222, and the second port 224. Is connected to the second processor 210 having the second EBI 212.

As illustrated in FIG. 2, the dual port memory 220 according to the present invention may include a dual port SDRAM logic 230, a first bypass unit 250, and a second bypass unit 252.

The dual port SDRAM logic 230 allows the first and second processors 200 and 210 to share and use the dual port memory 220. The first and second memory interfaces 232, the second memory interface 234, and the first and second processors 200 and 210 share the dual port memory 220. The first processor 200 may include a first dedicated memory area 236, a shared memory area 238, a second dedicated memory area 240, and a semaphore processor 242.

The first memory interface 232 may be configured as an SDRAM memory interface. The first memory interface 232 receives the SDRAM command SDRAM CMD1 and the address ADDR1 from the first processor 200 through the first port 222, decodes the address into a row address and a column address, and then decodes the first memory interface 232. The data DATA1 is read from or written to the memory cell array 210 according to a predetermined operation timing based on the address.

The writing and reading may be performed in synchronization with a clock signal provided by the first processor 200.

To this end, the first memory interface 232 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), and an input / output buffer (not shown) used in a general SDRAM interface. ) May be included.

The second memory interface 234 may be configured as an SDRAM memory interface. After receiving the SDRAM command SDRAM CMD2 and the address ADDR2 from the second processor 210 through the second port 224, decoding the address ADDR2 into a row address and a column address, and then performing data ( DATA2) is read from or written to the memory cell array.

The second memory interface 234 may include a control signal decoder (not shown), a row decoder (not shown), a column decoder (not shown), and an input / output buffer (not shown) corresponding to the received address and control signal. have.

The first dedicated memory area 236, the shared memory area 238, and the second dedicated memory area 240 corresponding to the memory cell array are formed in bank units having a unit memory cell structure of DRAM and having a predetermined size. Can be. In addition, each shared memory area may be configured in units of blocks having a predetermined size in one bank.

Although the dual port memory system is illustrated as including one shared memory area 238 in FIG. 2, it is not limited thereto, and it will be apparent to those skilled in the art that a larger number of shared memory areas may be provided.

The semaphore processor 242 controls mutually exclusive access to the shared memory area 238.

The first and second bypass units 250 and 252 are connected to the first port 222 and the second port 224, respectively, and selectively output commands, addresses, and data input and output from each processor.

The first bypass unit 250 is connected to the first processor 200 through the first EBI 202 to perform a bypass function of a signal input from the first processor 200.

As described above, the first EBI 202 may output not only an SDRAM command but also an SRAM command for controlling an internal bus of the second processor 210. The address ADDR1 and the data DATA1 input from the first processor 200 are transferred to the dual port SDRAM logic 220 or bypassed to the second bypass unit 252 according to the selection signal of.

The selection signal may be an SDRAM command or SRAM command signal output from the first EBI 202.

3 illustrates the bypass structure of FIG. 2 in detail, and FIG. 3 illustrates a process of bypassing the SRAM command as a selection signal.

As illustrated in FIG. 3, the first bypass unit 250 according to the present invention may determine whether the first EBI (eg, / CS included in the SRAM command) of the first EBI (the first EBI) of the first processor 200 is input. The address ADDR1 and the data DATA1 input from the 202 may be bypassed to the second bypass unit 252.

However, the present invention is not limited thereto, and the first bypass unit 250 may use a combination of / CS, / WE, and / RE included in the SRAM command as the selection signal.

4 is a diagram showing the detailed configuration of the first and second bypass unit according to the present invention.

As shown in FIG. 4, the first bypass unit 250 according to the first embodiment of the present invention may include a plurality of demuxes 400 and 402.

The first demux 400 bypasses the address ADDR1 input from the first processor 200 to the dual port SDRAM logic 230 or the second bypass unit 252 using the SRAM command signal as the selection signal. Perform the function.

The second demux 402 also performs a demuxing function of the data DATA1 input from the first processor 200 or output to the first processor 200 using the SRAM command as a selection signal.

For example, when the second demux 402 receives data to be written to the dual port SDRAM logic 230 or the second processor 210 from the first processor 200, the second demux 402 may input a selection signal corresponding to the SRAM command. Accordingly, the input data is transferred to the dual port SDRAM logic 230 or bypassed to the second bypass unit 252.

In FIG. 4, a plurality of demuxes are illustrated. However, in addition to the demux, another circuit for receiving a single input signal in response to a selection signal and selectively outputting one of two output signals may be implemented. Of course it is possible.

Meanwhile, the second bypass unit 252 according to the present invention may include a plurality of switching units 404 and 406.

The first switching unit 404 according to the present invention uses the SRAM command output from the first processor 200 as a selection signal to convert the address ADDR2 received from the second processor 210 to the dual port SDRAM logic 230. The address ADDR1, which is transmitted or bypassed from the first bypass unit 250, is transmitted to the second processor 210.

The second switching unit 406 transfers the address DATA2 received from the second processor 210 to the dual port SDRAM logic 230 using the SRAM command output from the first processor 200 as a selection signal, or A function of outputting the address DATA1 bypassed from the first bypass unit 250 to the second processor 210 side. In this case, the second switching unit 406 may transfer the data DATA1 output from the second processor 210 to the first bypass unit 250 according to the SRAM command of the first processor 200.

The switching units 404 and 406 may be configured as a plurality of three-phase buffers that are opened or closed according to a predetermined selection signal, but are not necessarily limited thereto.

According to the first preferred embodiment of the present invention, the address line 254 of the second processor 210 extends from the first switching section 404 to the second EBI 212 and at the predetermined branch point 258 the IBI ( Branched to 214 and extended.

The address output from the second processor 210 is transmitted to the first switching unit 404 through the address line 254, and the address output from the first processor 200 and bypassed is the branched address line 254. The first switching unit 404 is transmitted to the IBI 214 through.

In addition, the data line 256 corresponding to the second processor 210 extends from the second switching unit 406 to the second EBI 212 and branches to the IBI 214 at the predetermined branch point 260.

Data input and output from the second processor 210 is transferred to the second switching unit 404 through the data line 256, and output from the first processor 200 and bypassed (or the first processor 200). Data to be transmitted to the IBI 214 at the second switching unit 406 or to the second switching unit 406 at the IBI 214 through the branched data line 256.

When the SBI command is received from the dual port memory 220 at the IBI 214, the second processor 210 performs a process of controlling an internal bus according to the command, address, and data received at the IBI 214.

According to the present invention, the address line 254 and the data line 256 where the first processor 200 branches the internal bus control signal of the second processor 210 to the internal bus interface via the dual port memory 220. Because it can pass through branches of, it can improve memory performance.

In the above description, the internal bus interface is provided only on the second processor side, but according to the second embodiment of the present invention, all of the plurality of processors connected to the dual port memory 220 may transmit and receive signals for internal bus control. have.

5 is a diagram illustrating a configuration of a dual port memory system according to a second exemplary embodiment of the present invention.

As shown in FIG. 5, a dual port memory system according to the present invention includes a first processor 200 having a first EBI 202 and a first IBI 204, a dual port memory 220, and a second EBI ( 212 and a second processor 210 having a second IBI 214.

The first IBI 204 receives a signal for controlling an internal bus transmitted from the second processor 210, for example, an SRAM command and an address ADDR2, and performs input / output of data according to the SRAM command. .

In FIG. 2, the first EBI 202 outputs both the SDRAM command and the SRAM command. However, in FIG. 5, the first EBI 204 may output the SRAM command for controlling the internal bus. 202 can only perform SDRAM command output.

As such, when the first processor 200 includes the first IBI 204, the address line 500 corresponding to the first processor 200 is connected to the first EBI 202 by the first bypass unit 510. ) And also branches to a first IBI 204 at a predetermined branch point 501.

Here, when the first EBI 202 outputs the address ADDR1 corresponding to the memory cell of the dual port SDRAM logic 230, the corresponding address is transmitted to the first bypass unit 510 through the address line 500. The address ADDR2 output by the second processor 210 to control the internal bus is transferred from the first bypass unit 510 to the first IBI 204 through the branched address line 500. .

The data line 502 extends from the first bypass unit 510 to the first EBI 202 and branches to the first IBI 204 at the predetermined branch point 503.

Here, when data is written to a memory cell of the dual port SDRAM logic 230, the data is transferred from the first EBI 202 to the first bypass unit 510 through the data line 502, and read. The data is transferred from the first bypass unit 510 to the first EBI 202 through the data line 502.

Meanwhile, data DATA2 for controlling the internal bus of the first processor 200 by the second processor 210 may be divided into the first bypass unit 510 and the first IBI 204 through the branched data line 502. Input and output between).

According to a second embodiment of the present invention, the second EBI 212 and the second IBI 214 in the second processor 210, the second EBI 212, the second IBI 214, and the dual port memory 220. Since the address line 254 and the data line 256 branched to each other are the same as those described with reference to FIGS. 2 to 4, detailed description thereof will be omitted.

The first bypass unit 510 transfers the address and data output from the first processor 200 to control the internal bus of the second processor 210 to the dual port SDRAM logic 230 according to a predetermined selection signal. Or bypasses to the second bypass unit 512.

In addition, the first bypass unit 510 may also perform a function of outputting an address and data transmitted from the second processor 210 to the first IBI 204 of the second processor 210 according to a predetermined selection signal. Can be.

FIG. 6 illustrates a case in which an SRAM command output from each of the processors 200 and 210 is used as a selection signal. The SRAM command SRAM CMD1 is used to control an internal bus of the second processor 210 in the first processor 200. ), The first bypass unit 510 outputs the input address ADDR1 and data DATA1 to the second bypass unit 512. In addition, the first bypass unit 510 receives the address and data bypassed from the second bypass unit 512 according to the SRAM command SRAM CMD2 output from the second processor 210. Perform the function to output to.

When the second processor 210 outputs the SRAM command SRAM CMD2 to control the internal bus of the first processor 200, the second bypass unit 512 may input the address ADDR2 and the data ( DATA2) is output to the first bypass unit 510. In addition, the second bypass unit 512 receives the address and data transferred from the first bypass unit 510 according to the SRAM command SRAM CMD1 output from the first IBI 204 of the first processor 200. A function of outputting to the second IBI 214 is performed.

When both the first and second processors 200 and 210 have internal bus interfaces 204 and 214, the configuration of the first and second bypass units 510 and 512 may be different from that of FIG. 4, and FIG. 7 is the bypass of FIG. 5. It is a figure which shows a detailed part structure.

As illustrated in FIG. 7, the first bypass unit 510 according to the present invention may include a plurality of demuxes 700 and 702 and a plurality of switching units 704 and 706.

The first demux 700 receives an address ADDR1 input from the first processor 200 using the SRAM command (for example, SRAM CMD1 of FIG. 6) as a selection signal, or the dual port SDRAM logic 230 or the second. Bypass the bypass unit 512 side.

The first switching unit 704 receives the address bypassed by the second bypass unit 512 in accordance with a predetermined selection signal and outputs the address to the first IBI 204. The selection signal of the first switching unit 704 may be an SRAM command SRAM CMD2 of the second processor 210.

The second demux 702 performs a demux function of data input from the first processor 200 or output to the first processor 200 according to the selection signal.

Meanwhile, the second switching unit 706 performs a data switching function for controlling the internal bus according to the selection signal. For example, when the SRAM command (SRAM CMD2) is received, the second switching unit 706 outputs the data transmitted by the second processor 210 to the first IBI 204 or the first for controlling the internal bus. The data transmitted by the processor 200 bypasses the second bypass unit 512.

Meanwhile, the second bypass unit 512 may also include a plurality of demuxes 710 and 712 and a plurality of switching units 714 and 716.

The third demux 710 receives the address ADDR2 input from the second processor 210 using the SRAM command signal (for example, SRAM CMD2 of FIG. 6) as a selection signal, and uses the dual port SDRAM logic 230 or the second signal. 1 bypasses the bypass unit 510.

The third switching unit 714 receives the address bypassed by the first demux 700 on the first bypass unit 510 side and outputs the address to the second IBI 214 according to a predetermined selection signal. The selection signal of the third switching unit 714 may be an SRAM command SRAM CMD1 of the first processor 200.

The third demux 712 performs a demuxing function of data input from the second processor 210 or output to the second processor 210 according to the selection signal.

Meanwhile, the fourth switching unit 716 performs a data switching function for controlling the internal bus according to the selection signal. For example, when the SRAM command SRAM CMD1 is received, the fourth switching unit 716 outputs data transmitted by the first processor 200 to the second IBI 214 or internal bus for internal bus control. As a result of the control, the data transmitted by the second processor 210 is output to the second demux 702 of the first bypass unit 510.

8 is a diagram illustrating a dual port memory system according to a third exemplary embodiment of the present invention.

FIG. 8 illustrates a case in which the third processor 800 transmits a signal for controlling the internal bus of the fourth processor 810 through the dual port memory 220 separately from the first and second processors 200 and 210. One drawing.

8, the first processor 200 and the third processor 800 adjacent to each other may share and use an address line and a data line, and the second processor 210 and the third processor 800 may be used. The address line data line can be shared.

The address line 820 corresponding to the first and third processors extends from the first bypass portion 806 to the first EBI 202 and also at the predetermined branch point 821 the first host parallel of the third processor. Interface 802 may be branched to.

In addition, the data lines 822 corresponding to the first and third processors extend from the first bypass portion 806 to the first EBI 202 and at the predetermined branch point 823, the first HPI ( Branch to Host Parallel Interface, 802.

On the other hand, the address line 824 corresponding to the second and fourth processors extends from the second bypass unit 808 to the second EBI 212 and at the predetermined branch point 825 the second HPI ( May be branched to a Host Parallel Interface (812).

In addition, the data lines 826 corresponding to the second and fourth processors extend from the second bypass portion 808 to the second EBI 212 and at the predetermined branch point 827 the second HPI ( May be branched to a Host Parallel Interface (812).

In the host-slave structure, when the third processor 800 corresponding to the host wants to transmit a signal for controlling the internal bus of the fourth processor 810, the third processor 800 and the first processor as described above. Since the processor 200 shares an address and a data line, the first bypass unit 806 may use an internal bus control signal (eg, SRAM CMD) output by the first HPI 802 of the third processor 800. The address and data input as a selection signal are transferred to the dual port SDRAM logic 230 or the second bypass unit 808 is bypassed.

The first bypass unit 808 may include a demux for demuxing and outputting an address output from the first processor 200 and an address output from the third processor 800, and the first processor 200. And a switching unit for transferring data input / output to the fourth processor to the first HPI 802 according to the internal bus control.

Meanwhile, the second bypass unit 808 includes a switching unit and transfers the SDRAM command input from the second EBI 212 to the dual port SDRAM logic 230 or the first bypass unit 806. The SRAM command of the three processors is output to the second HPI 812.

In addition, a separate switching unit may enable input / output of data between the second processor 210 and the dual port SDRAM logic 230 and between the third processor 800 and the fourth processor 810.

Although the first and second processors are illustrated as interfacing SDRAMs, the present invention is not limited thereto, and the first and second processors may transmit and receive signals for controlling internal buses of the counterpart processor as shown in FIGS. 2 to 7. Those skilled in the art will appreciate that they may be included in the category.

According to the third embodiment of the present invention, the third processor and the fourth processor can transmit and receive signals for controlling an internal bus through a dual port memory, and do not have to provide a separate signal line to the outside, Signal transmission can be efficiently handled.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, according to the present invention, there is an advantage in that a signal for controlling an internal bus can be transferred between a plurality of processors through a dual port memory having a bypass structure without a separate external signal line.

In addition, according to the present invention, since there is no separate external signal line, the system chip mounting area can be reduced.

Claims

A memory cell array having a shared memory area;

A first memory interface configured to perform a write or read operation of data to the shared memory area based on an address and a command provided through a first port from a first processor;

A second memory interface configured to write or read data to the shared memory area based on an address and a command provided from a second processor through a second port;

A first bypass unit bypassing an internal bus control signal received from the first processor; And

And a second bypass unit configured to transfer the bypassed internal bus control signal to the second processor.

The method of claim 1,

And the internal bus control signal includes at least one of an internal bus control command of the second processor, an address, and data written or read according to the internal bus control.

The method of claim 2,

The internal bus control command includes at least one of a chip select signal, a write enable signal, and a read enable signal,

The first bypass unit bypasses the input address and data to the second bypass unit using a signal according to at least one of the chip select signal, the write enable signal, and the read enable signal, or a combination thereof. Dual port memory.

The method of claim 3,

And the internal bus control command is an SRAM command.

The method of claim 4, wherein

The external bus interface of the first processor selectively outputs the SDRAM command and the SRAM command for writing or reading data to the shared memory area under the control of the first processor.

The method of claim 2,

The first bypass unit,

A first demux for demuxing an address received from the first processor using the internal bus control command as a selection signal; And

And a second demux for demuxing data received from the first processor using the internal bus control command as a selection signal.

The method of claim 2,

The second bypass unit,

A first switching unit configured to transfer the bypassed address to the second processor or to output an address input from the second processor to the second memory interface using the internal bus control command as a selection signal; And

And a second switching unit configured to transfer the bypassed data to the second processor or to output data input from the second processor to the second memory interface using the internal bus control command as a selection signal. Dual port memory.

Claim 8 was abandoned when the registration fee was paid.

The method of claim 7, wherein

And the first switching unit extends to an external bus interface of the second processor and is connected to an address line branched to an internal bus interface receiving the internal bus control command at a predetermined branch point.

Claim 9 was abandoned upon payment of a set-up fee.

The method of claim 7, wherein

A memory cell array having a shared memory area;

A first bypass unit bypassing a first internal bus control signal received from the first processor and transferring a second internal bus control signal received from the second processor to the first processor; And

And a second bypass unit configured to bypass the second internal bus control signal received from the second processor to the first bypass unit, and to transfer the first internal bus control signal to the second processor. Dual port memory.

The method of claim 10,

The first internal bus control signal includes at least one of a first command for controlling an internal bus of the second processor, an address, and data written or read according to the internal bus control, and the second internal bus control signal And at least one of a second command for controlling an internal bus of the first processor, an address, and data written or read according to the internal bus control.

The method of claim 11,

The address is bypassed from the second bypass unit using a signal according to at least one or a combination of a chip select signal, a write enable signal, and a read enable signal included in the second command. And delivering data to the first processor.

The method of claim 11,

The first bypass unit,

One or more demuxes that demux the address and data received from the first processor using the first command as a selection signal; And

And at least one switching unit configured to transfer the address and data bypassed from the second bypass unit to the first processor using the second command as a selection signal.

Claim 14 was abandoned when the registration fee was paid.

The one or more switching unit,

A first switching unit extending to a first external bus interface of the first processor and connected to an address line branched to a first internal bus interface receiving the second command at a predetermined branch point; And

And a second switching unit extending to a first external bus interface of the first processor and connected to a data line branched to a first internal bus interface receiving the second command at a predetermined branch point.

The method of claim 11,

The second bypass unit bypasses the first bypass unit by using a signal according to at least one or a combination of a chip select signal, a write enable signal, and a read enable signal included in the first internal bus control command. And passing the address and data to be passed to the first processor.

The method of claim 11,

The second bypass unit,

At least one demux for demuxing the address and data received from the second processor using the second command as a selection signal; And

And at least one switching unit configured to transfer the address and data bypassed from the first bypass to the second processor using the first command as a selection signal.

Claim 17 was abandoned upon payment of a registration fee.

The method of claim 16,

The one or more switching unit,

A first switching unit extending to an external bus interface of the second processor and connected to an address line branched to a second internal bus interface receiving the first command at a predetermined branch point; And

And a second switching unit extending to an external bus interface of the second processor and connected to a data line branched to a second internal bus interface receiving the first command at a predetermined branch point.

A memory cell array having a shared memory area;

A first bypass unit bypassing an internal bus control signal received from a third processor corresponding to the host; And

And a second bypass unit configured to transfer the bypassed internal bus control signal to a fourth processor corresponding to a slave.

The method of claim 18,

And the first and third processors share an address line and a data line.

The method of claim 18,

And the second and fourth processors share an address line and a data line.