KR100847921B1 - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and particularly effective for the wiring forming technology of a semiconductor integrated circuit device. In the case of using the plating method, the embedding ability is high, but the crystal grains formed by this method are small and sufficient. In order to solve the problem that electrical characteristics are not obtained, a connection hole is formed in the insulating film on the upper layer of the semiconductor substrate, a connection conductor film is formed so as to fill the connection hole on the insulating film, and the connection conductor film is formed after the forming step of the connection conductor film. The planarization treatment was performed to remove the connection conductor film other than the connection hole, thereby forming the connection conductor portion in the connection hole, and forming the wiring groove in the wiring formation region of the insulating film after the connection conductor portion was formed. A wiring conductor film is formed to fill the wiring groove on the film, and the wiring conductor film is formed. After the process carried out by the leveling process to the wiring conductive film by removing the wiring conductive film other than the wiring homnae were configured to form a buried wiring in the wiring trench.

By doing so, the effect that the conductor film can be satisfactorily embedded in both the wiring groove and the finer connection hole than that is obtained.

Description

Semiconductor integrated circuit device and its manufacturing method {@@@@}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly, to a technology effective by applying to a wiring forming technology of a semiconductor integrated circuit device.

As a wiring forming method of a semiconductor integrated circuit device, there is a process called, for example, the damascene method. In this method, a wiring forming groove is formed in the insulating film, and then a wiring forming conductor film is deposited on the front surface of the semiconductor substrate, and the conductive film in a region other than the groove is removed by chemical mechanical polishing (CMP). This is a method of forming a buried wiring in a wiring forming groove. This method is considered as a method of forming a buried wiring made of a copper (copper or copper alloy) conductor material, which is particularly difficult to finely etch.

In addition, there is a dual-Damascene method as an application of the large machine method. In this method, a wiring forming groove and a connection hole for connecting the lower layer wiring are formed in the insulating film, and then the wiring forming conductor film is deposited on the entire surface of the semiconductor substrate, and the conductor film in the region other than the groove is removed by CMP. By forming a buried wiring in the wiring forming groove, a plug is formed in the connection hole. In the case of this method, particularly in a semiconductor integrated circuit device having a multilayer wiring structure, the number of steps can be reduced and the wiring cost can be reduced.

Such a wire forming technique is disclosed in, for example, Japanese Patent Publication No. 8-78410, 1996 Symp, VLSI Tech, Digest pp. 48-49, Electronic Materials March, pp. 22-27, 1996, Japanese Patent Publication Publication Flat 8-148560 or IBM. J. RES. DEVELOP. VOL. 39 No. 4 pp. 419-435, July 1995.

By the way, the present inventors have found that the above-described problem is encountered in the technology of forming the buried wiring.

In other words, the overall structure and manufacturing conditions in the case where the buried wiring technology is applied to the semiconductor integrated circuit device are not completely established. In particular, in the above-described double machine method, the wiring forming groove and the connection hole are simultaneously filled with the same conductor film, but the connection hole finer than the wiring forming groove is simultaneously filled with the wiring forming groove with sufficient and good electrical characteristics. This is difficult due to the miniaturization of wiring and connection holes. For example, when copper is used as the wiring material, it is difficult to embed copper into the connection hole by the sputtering method. On the other hand, when the plating method is used, although the embedding ability is high, the crystal grains formed immediately after the film formation of copper formed by this method may be small and sufficient electrical characteristics may not be obtained. In addition, even though the embedding capability of the plating method is high, there is a limit and it is difficult to bury the high aspect ratio fine connection holes. This problem occurs even when there are wiring grooves having different aspect ratios in the same buried wiring layer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique in which a semiconductor film for embedding wiring can be satisfactorily embedded in a semiconductor integrated circuit device having a buried wiring structure without using a high technology.

It is also an object of the present invention to provide a technique capable of promoting the miniaturization of a wiring groove, a connection hole, or both in a semiconductor integrated circuit device having a buried wiring structure.

In addition, another object of the present invention is to provide a technique capable of improving the reliability of the buried wiring.

Another object of the present invention is to provide a technique for assembling a buried wiring using a copper conductor material into the entire structure of a semiconductor integrated circuit device without causing irrationality.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

An outline of typical ones of the inventions disclosed in the present application will be briefly described as follows.

The method for manufacturing a semiconductor integrated circuit device of the present invention is a method for manufacturing a semiconductor integrated circuit device having a buried wiring in a wiring layer on an upper layer of a semiconductor substrate, the method comprising: [a] drilling a connection hole in an insulating film on an upper layer of the semiconductor substrate; b) forming a connecting conductor film so as to fill the connection hole on the insulating film; and [c] forming a connection conductor film, and then performing a flattening treatment on the connecting conductor film to form a connection conductor other than the inside of the connection hole. Forming a connecting conductor portion in the connection hole by removing the conductor film; [d] forming a wiring groove in the wiring forming region of the insulating film after forming the connecting conductor portion; Forming a wiring conductor film so as to fill the wiring groove; and [f] flattening the wiring conductor film after forming the wiring conductor film. The process includes forming a buried wiring in the wiring groove by removing the wiring conductor film other than the inside of the wiring groove.

In the method for manufacturing a semiconductor integrated circuit device of the present invention, the wiring conductor film is made of copper or copper alloy. When the conductor film is formed by the sputtering method, it has a step of performing heat treatment after the planarization treatment step of the wiring conductor film.

The method for manufacturing a semiconductor integrated circuit device of the present invention is a method for manufacturing a semiconductor integrated circuit device having a buried wiring in a wiring layer on an upper layer of a semiconductor substrate, and in the case of embedding a conductor film in wiring grooves having different dimensions formed in the same buried wiring layer. The conductor films are separately embedded in the wiring grooves having different dimensions.

In addition, the method for manufacturing a semiconductor integrated circuit device of the present invention is a method for manufacturing a semiconductor integrated circuit device having a buried wiring in a wiring layer on an upper layer of a semiconductor substrate, wherein [a] a wiring groove and a connection hole are formed in an insulating film on the upper layer of the semiconductor substrate. A step of punching, [b] a step of forming a conductor film made of copper or copper alloy by sputtering so that the wiring groove and the connection hole are embedded in the insulating film; and [c] the planarization treatment of the conductor film made of copper or copper alloy. And embedding the conductor film in the wiring groove and the connection hole by removing the conductor film made of copper or copper alloy other than the wiring groove and the connection hole, and [d] the planarization treatment process of the conductor film made of the copper or copper alloy. It has a process of performing heat processing afterwards.

In addition, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a buried wiring in a wiring layer on an upper layer of a semiconductor substrate, wherein the wiring material of the portion where the buried wiring and the semiconductor substrate are in contact with each other is tungsten, tungsten alloy, titanium, titanium nitride. At least 1 type of a ride, aluminum, or aluminum alloy is used, and the buried wiring in the upper wiring layer is comprised with copper or copper alloy.

The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having buried wiring in at least one or more of the wiring layers of the upper layer of the semiconductor substrate, wherein the wiring material of the best wiring layer in the wiring layer is made of aluminum or aluminum alloy. The buried wiring in the lower wiring layer is made of copper or copper alloy.

In addition, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a buried wiring in a wiring layer on an upper layer of a semiconductor substrate, and when connecting wiring made of aluminum or aluminum alloy and wiring made of copper or copper alloy, barriers are connected to those connection portions. The conductor film is interposed.

The semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a buried wiring in a wiring layer on an upper layer of a semiconductor substrate, wherein the wiring above the wiring layer of the predetermined buried wiring in the wiring layer is lower than the wiring layer of the predetermined buried wiring. In the case where the wiring is electrically connected, the connection conductor portion provided in the connection hole extending from the wiring in the upper layer to the wiring layer of the predetermined buried wiring and the connection hole provided in the connection hole extending from the wiring in the lower layer to the wiring layer of the predetermined buried wiring. The body portion is electrically connected via a relay connection conductor portion provided in a connection groove of the wiring layer of the predetermined buried wiring, and the relay connection conductor portion has at least a length in a wiring extension direction of the predetermined buried wiring. It is formed to be longer than the length of the wiring extension direction of the connection hole. That will.

Embodiment of the Invention

Best Mode for Carrying Out the Invention Embodiments of the present invention will be described in detail below with reference to the drawings. (In addition, in the entire drawings for explaining the embodiments, those having the same functions are denoted by the same reference numerals, and repetitive description thereof is omitted).

Example 1

1 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a main part of a first layer wiring of the semiconductor integrated circuit device of FIG. 1, and FIGS. 6 is a cross-sectional view of an essential part showing a second layer wiring of the semiconductor integrated circuit device of FIG. 1, and FIG. 7 is a semiconductor integrated view showing a modified example of interconnection between wiring layers of the semiconductor integrated circuit device of FIG. 8 to 12 are main part cross sectional views in the manufacturing process of the semiconductor integrated circuit device of FIG. 1, and FIGS. 13 to 18 are part of main parts in the manufacturing process of the semiconductor integrated circuit device of FIG. Cutting perspective view.

First, the structure of the semiconductor integrated circuit device of the first embodiment will be described with reference to FIGS. The semiconductor substrate 1 is made of, for example, a p-type silicon (Si) single crystal, and p well PW and n well NW are formed thereon. The p well PW contains, for example, boron (B) of p-type impurity, and the n well NW contains, for example, phosphorus (P) or arsenic (As) of n-type impurity.

In addition, an element isolator 2 is formed on the semiconductor substrate 1. The element isolator 2 is formed by embedding a separation insulating film 2b made of, for example, silicon oxide or the like in a separation groove 2a formed in the upper portion of the semiconductor substrate 1. The upper surface of the device isolation section 2 is planarized to substantially coincide with the main surface of the semiconductor substrate 1.

In the region of the p-well PW and n-well NW surrounded by the element isolator 2, for example, an n-channel MOSFET (hereinafter referred to as a metal-oxide-semiconductor field effect transistor, hereinafter referred to as nMOS) (3n) and a p-channel MOSFET ( Hereinafter, only pMOS) 3p is formed. A CMOS (Complimentary MOS) is formed by the nMOS 3n and the pMOS 3p. However, the integrated circuit elements formed on the semiconductor substrate 1 are not limited to HOSFETs or MISFETs (Metal-Insulator-Semiconductors), and may be variously changed. The bipolar transistors, diodes or resistors, or these integrated circuit devices may be the same The structure formed on a phase may be sufficient.

The nMOS 3n has a pair of semiconductor regions 3nd formed on top of the p well PW, a gate insulating film 3ni formed on the semiconductor substrate 1, and a gate electrode 3ng formed thereon. In addition, the channel region of the nMOS 3n is formed between the pair of semiconductor regions 3nd in the p well PW.

This semiconductor region 3nd is a region for forming a source / drain region of the nMOS 3n, and contains, for example, phosphorus or As of an n-type impurity. Further, the semiconductor region 3nd may have a structure having a relatively low concentration semiconductor region disposed on the channel region side and a relatively high concentration semiconductor region disposed outside thereof.

The gate insulating film 3ni is made of silicon oxide, for example. The gate curvature 3ng formed thereon is made of, for example, a monolithic film of low resistance polysilicon. However, the gate electrode 3ng is not limited to a monolayer of low-resistance polysilicon, but may be a so-called polyside structure formed by forming a silicide film such as tungsten silicide on a monolayer of low-resistance polysilicon, for example. For example, a so-called polymetal structure may be formed by forming a metal film such as tungsten through a barrier metal film such as titanium nitride on a single film of low resistance polysilicon.

On the other hand, the pMOS 3p has a pair of semiconductor regions 3pd formed on top of the n well NW, a gate insulating film 3pi formed on the semiconductor substrate 1, and a gate electrode 3pg formed thereon. have. The channel region of the pMOS 3p is formed between the pair of semiconductor regions 3pd in the n well NW.

This semiconductor region 3pd is a region for forming a source / drain region of the pMOS 3p, and contains, for example, boron of p-type impurity. Further, the semiconductor region 3pd may have a structure having a relatively low concentration semiconductor region disposed on the channel region side and a relatively high concentration semiconductor region disposed outside thereof.

The gate insulating film 3pi is made of silicon oxide, for example. The gate electrode 3pg formed thereon is made of, for example, a monolayer of low resistance polysilicon. However, the gate electrode 3pg is not limited to a monolithic film of low-resistance polysilicon, but may be a so-called polyside structure formed by forming a silicide film such as tungsten silicide on a monolithic film of low-resistance polysilicon. For example, a so-called polymetal structure may be formed by forming a metal film such as tungsten through a barrier metal film such as titanium nitride or the like on a monolayer film of low resistance polysilicon.

On such a semiconductor substrate 1, an interlayer insulating film 4a made of, for example, silicon oxide whose surface is planarized by, for example, the CMP method, is formed, whereby nMOS 3n and pMOS 3P are formed. It is covered. Wiring grooves 5a and 5b having different widths or lengths are formed on the interlayer insulating film 4a. The depths of the wiring grooves 5a and 5b are the same, for example, about 0.3 to 1.0 m, preferably about 0.5 m. The aspect ratio of the wiring groove 5a is, for example, about 0.1 to 1.0, preferably smaller than 0.7 in consideration of satisfactory filling of the wiring conductor film. The aspect ratio of the wiring groove 5b is, for example, about 0.5 to 2.5, and is preferably smaller than 1.5 in consideration of embedding the wiring conductor film.

1 and 2, the first layer wiring 6L is embedded in the wiring grooves 5a and 5b. This first layer wiring 6L is composed of a relatively thin conductor film 6L ₁ at the lower and side portions and a relatively thick conductor film 6L ₂ surrounded by the thin conductor film 6L ₁ .

The thin conductor film 6L ₁ is made of a material having a function of improving the adhesion between the first layer wiring 6L and the interlayer insulating film 4a or a barrier function of suppressing diffusion of members of the thick conductor film 6L ₂ . For example, tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tungsten nitride (WN), tungsten nitride silicide (WSiN), titanium silicide nitride (TiSiN), tantalum nitride (TaN) Or tantalum nitride (TaSiN) or the like.

In the case where the thin conductor film 6L ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case of being made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. Although not particularly limited, in the first embodiment, the thin conductor film 6L ₁ is made of TiN, for example.

The thick conductor film 6L ₂ is a member constituting the main body of the first layer wiring 6L. For example, the thick conductor film 6L ₂ is made of aluminum (Al), Al alloy, tungsten, tungsten alloy, copper (Cu) or Cu alloy. Made of low resistance material. One example of an A1 alloy is one in which a selected one or more elements selected from elements such as Si, Cu, Ge, and the like are added to a conductor film made of A1. As an example of Cu alloy, what added one or more selected from the elements, such as magnesium (Mg), Si, Ti, etc., was added to the conductor film which consists of Cu. One example of the tungsten alloy is one in which a selected one or more elements selected from elements such as Si and N are added to a conductor film made of tungsten. In addition, in the following description, about A1 alloy, tungsten alloy, and Cu alloy, it is basically the same as that mentioned above. When the thick conductor film 6L ₂ is made of Cu or Cu alloy, the wiring resistance can be considerably lowered compared to the case of AL or tungsten, and the thick conductor film 6L ₂ is made of AL or AL alloy. Compared with the case, the electron transfer (EM) resistance of the first layer wiring 6L can be improved. Although not particularly limited, in the first embodiment, the thick conductor film 6L ₂ is made of, for example, Cu.

However, the structure of the first layer wiring 6L is not limited to the structure shown in FIGS. 1 and 2, and can be variously changed. For example, the structure shown in FIGS. 3 to 5 may be used. Figure 3 is a thin conductive film (6L ₁₎ and is provided with a thick conductive film (6L ₂₎ the cap conductive film ((6L ₃₎ so as to cover the structure. Cap conductive film (6L _3), for example, tungsten, TiN, Ti , Ta, WN, WSiN, TiSiN, TaN, TaSiN, etc. This structure can further suppress the diffusion of Cu atoms by applying especially when the thick conductor film 6L ₂ is composed of Cu or Cu alloy. Therefore, the reliability of the semiconductor integrated circuit device can be further improved, and although not particularly limited, the direct contact between the wiring material and the thick conductor film 6L ₂ in relation to the upper wiring material has a high specific resistance. It is also suitable for the case where an alloy is formed, etc. The cap conductor film may be provided only on the upper surface of the thick conductor film 6L ₂ so that the upper surface thereof substantially coincides with the upper surface of the interlayer insulating film 4a.

4 is a structure in which the first layer wiring 6L is composed of only the thick conductor film 6L ₂ . That is, it is a structure without a thin conductor film. 5 is a structure in which the cap conductor film 6L ₃ is provided on the upper surface of the thick conductor film 6L ₂ in the structure of FIG. This structure is not particularly limited, if in direct contact to the wiring material and thick film conductor (6L ₂₎ in relation to the upper layer of the wiring material is suitable for this, such as high specific resistance alloy ll is formed.

The first layer wiring 6L in the wiring groove 5a is electrically connected to the semiconductor region 3nd of the nMOS 3n or the semiconductor region 3pd of the pMOS 3p through the connection conductor portion 7C. Although the connecting conductor portion 7C is most embedded in the connecting hole 8a bored in the interlayer insulating film 4a from the bottom surface of the wiring groove 5a toward the upper surface of the semiconductor substrate 1, the connecting conductor portion ( The upper portion of 7C) protrudes into the first layer wiring 6L so as to penetrate the upper and lower surfaces of the first layer wiring 6L. The diameter of the connection hole 8a is about 0.2-1.0 micrometer, for example, Preferably it is about 0.4 micrometer. In addition, the aspect ratio of the connection hole 8a is preferably about 2 to 6 and smaller than about 4 in consideration of satisfactory embedding of the connection conductor portion. The height of the upper surface of the connection conductor portion 7C substantially coincides with the height of the upper surface of the first layer wiring 6L.

The connection conductor portion 7C is composed of a relatively thin conductor film 7C ₁ at the lower and side portions thereof and a relatively thick conductor film 7C ₂ surrounded by the thin conductor film 7C ₁ . The thin conductor film 7C ₁ is made of a material having a function of improving the adhesion between the connection conductor portion 7C and the interlayer insulating film 4a and a barrier function of suppressing diffusion of members of the thick conductor film 7C ₂ , For example, it consists of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN.

In the case where the thin conductor film 7C ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case of being made of TiN, Tl, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the first embodiment, the thin conductor film 7C ₁ is made of, for example, tungsten.

The thick conductor film 7C ₂ is a member constituting the main body of the connection conductor portion 7C, and is made of a low resistance material such as, for example, A1, Al alloy, tungsten or tungsten alloy. Cu or Cu alloy is not used for the constituent material of the thick conductor film 7C ₂ . That is, in the first embodiment, the connection conductor portion 7C which is in direct contact with the semiconductor substrate 1 even if Cu or Cu alloy is used as the constituent material of the buried conductor film 6L ₂ of the first layer wiring 6L. Cu or Cu alloy is not used for the constituent material of. As a result, it is possible to reduce the wiring resistance of the first layer wiring 6L and to suppress the connection failure caused by the diffusion of Cu atoms toward the semiconductor substrate 1 side.

In the case where the thick conductor film 7C ₂ is made of Al or Al alloy, the resistance of the connection conductor portion 7C can be lowered compared with the case of tungsten or tungsten alloy. In addition, when the buried conductor film 7C ₂ is made of tungsten or tungsten alloy, the EM resistance and SM resistance of the connection conductor part 7C can be improved as compared with the case where the buried conductor film 7C ₂ is made of Al or Al alloy. It becomes possible. Although not particularly limited, in the first embodiment, the thick conductor film 7C ₂ is made of, for example, tungsten. Therefore, in the first embodiment, different types of conductor films (such as Cu for forming the first layer wiring 6L and tungsten for the connecting conductor portion 7C) are formed in the plane of the height position of the first layer wiring 6L. It is a structure that exists. In addition, the connecting conductor portion also constitutes a part of the wiring.

In addition, although the above description demonstrated the case where the 1st layer wiring 6L in the wiring groove 5a, 5b is comprised from the same material, it is not limited to this. For example, a film thick conductor is embedded in the wiring grooves (5b) (6L ₂₎ and the thick conductor embedding the material of the thin conductor film (6L ₁₎ a wiring trench (5a) layer (6L ₂₎ and a thin conductor film It may be a different type of conductive material as the constituent material of ₍₁ 6L). This is because, for example, when attempting to embed Cu or the like in the wide wiring groove 5a and the narrow wiring groove 5b at the same time, the narrow wiring groove 5b may not be sufficiently buried. The wide wiring groove 5a is embedded in Cu, and the narrow wiring groove 5b is a structural example in which tungsten or the like is embedded by CVD or the like. In addition, the formation method in this case is mentioned later.

On the interlayer insulating film 4a, for example, an interlayer insulating film 4b is formed on the silicon nitride film 4b ₁ on which silicon oxide 4b ₂ having a thicker film thickness than the silicon nitride film is formed. The silicon nitride film 4b ₁ functions as a barrier film for preventing diffusion of Cu when the thick conductor film 6L ₂ or the buried conductor film 7C ₂ is made of a Cu-based conductive material. Further, in forming the connection hole (8a), which will be described later by using the silicon nitride layer (4b ₁₎ as an etching stopper layer, and etching the silicon oxide layer (4b _2), and then it is removed by etching the silicon nitride layer (4b _2). In addition, when the thick conductor film 6L ₂ or the buried conductive film 7C ₂ is made of a conductive material other than Cu, the silicon nitride film 4b ₁ may not be provided. Wiring grooves 5c and 5d having different widths are formed on the interlayer insulating film 4b. The depths of the wiring grooves 5c and 5d are the same, for example, about 0.3 to 1.0 mu m, preferably about 0.6 mu m. In addition, the aspect ratio of the wiring groove 5c is, for example, about 0.1 to 1.0, preferably smaller than 0.7 in consideration of satisfactory filling of the wiring conductor film. In addition, the aspect ratio of the wiring groove 5d is preferably about 0.5 to 2.5, and smaller than 1.5 in consideration of satisfactory filling of the wiring conductor film. The silicon oxide film 4b ₂ is composed of, for example, a TEOS film or an SOG film formed by a CVD method. By using a low dielectric constant SOG (Spin On Glass) film, the capacitance between wirings can be reduced and the operation speed of the circuit can be improved.

In the wiring grooves 5c and 5d, as shown in Figs. 1 and 6, the second layer wiring 9L is formed in the embedded state. This second layer wiring 9L is composed of a relatively thin conductor film 9L ₁ at the lower and side portions and a relatively thick conductor film 9L ₂ surrounded by the thin conductor film 9L ₁ .

The thin conductor film 9L ₁ is made of a material having a function of improving the adhesion between the second layer wiring 9L and the interlayer insulating film 4b or a barrier capable of suppressing diffusion of members of the thick conductor film 9L ₂ . For example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN and the like.

In the case where the thin-walled conductor film 9L ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. Although not particularly limited, in the first embodiment, the thin conductor film 9L ₁ is made of TiN, for example.

Further, the thick conductor film 9L ₂ is a member constituting the main body of the second layer wiring 9L, and is made of a low resistance material such as, for example, A 1, A 1 alloy, tungsten, tungsten alloy, Cu, or Cu alloy. . When the thick conductor film 9L ₂ is made of Cu or Cu alloy, the wiring resistance can be significantly reduced as compared with the case of Al or tungsten. Further, the EM resistance of the second layer wiring 9L can be improved as compared with the case where the thick conductor film 9L ₂ is made of Al or Al alloy. Although not particularly limited, in the first embodiment, the thick conductor film 9L ₂ is made of, for example, Cu.

However, the structure of the second layer wiring 9L is not limited to the structure shown in FIGS. 1 and 6, but can be variously changed. For example, in FIGS. 3 to 5 described as the first layer wiring 6L. It is good also as a structure shown in figure. That is, any structure may be provided with a cap conductive film on the upper surface of the thick conductor film (9L ₂₎ and a thin conductor film (9L _1). The cap conductor film is made of a low resistance material such as tungsten or the like or a material having a barrier function such as TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. In particular, this structure can further suppress the diffusion of Cu atoms by applying the thick conductor film 9L _{2 made} of Cu or Cu alloy, thereby further improving the reliability of the semiconductor integrated circuit device. . Further, it not particularly limited, if in direct contact to the wiring material and thick film conductor (9L ₂₎ in relation to the upper layer of the wiring material is suitable for this, such as high specific resistance alloy ll is formed. The cap conductor film may be provided only on the upper surface of the thick conductor film 6L ₂ so that the upper surface thereof substantially coincides with the upper surface of the interlayer insulating film 4a.

As another structure, the structure in which the second layer wiring 9L is composed of only the thick conductor film 9L ₂ may be used. That is, it is a structure without a thin conductor film. As another structure, in a structure without the thin conductor film, a structure in which a cap conductor film is provided on the upper surface of the thick conductor film 9L ₂ may be used. This structure is not particularly limited, if in direct contact to the wiring material and thick film conductor (9L ₂₎ in relation to the upper layer of the wiring material is suitable for if they are formed is such as alloys with high resistivity.

The second layer wiring 9L formed in the wiring groove 5c is electrically connected to the first layer wiring 6L through the connection conductor portion 10C. Although most of the connection conductor portion 10C is embedded in the connection hole 8b bored in the interlayer insulating film 4b toward the upper surface of the first layer wiring 6L from the bottom surface of the wiring groove 5c, the connection purpose is used. The upper portion of the body portion 10C protrudes into the second layer wiring 9L so as to penetrate the upper and lower surfaces of the second layer wiring 9L. The diameter of the connection hole 8b is, for example, about 0.2 to 1.2 mu m, preferably about 0.4, for example. In addition, the aspect ratio of the connection hole 8b is preferably about 2 to 6 and smaller than about 4 in consideration of satisfactory embedding of the connection conductor portion. The height of the upper surface of the connection conductor portion 10C substantially coincides with the height of the upper surface of the second layer wiring 9L, that is, the height of the upper surface of the interlayer insulating film 4b.

Connection purposes body (10C) is composed of a lower portion and a relatively thin conductive film (10C ₁₎ with a thin conductive film (10C ₁₎ relatively thick conductive film (10C ₂₎ surrounded by the side. The thin conductor film 10C ₁ is made of a material having a function of improving the adhesion between the connecting conductor portion 10C and the interlayer insulating film 4b or a barrier function of suppressing diffusion of members of the thick conductor film 10C ₂ , For example, it consists of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN.

In the case where the thin conductor film 10C ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. Although not particularly limited, in the first embodiment, the thin conductor film 10C ₁ is made of, for example, tungsten.

The thick conductor film 10C ₂ is a member constituting the main body of the connection conductor portion 7C. The thick conductor film 10C ₂ is made of a low-resistance material such as, for example, A 1, A 1 alloy, tungsten, tungsten alloy, Cu, or Cu alloy. By constructing the thick conductor film 10C _{2 with} , for example, Cu or Cu alloy, the resistance of the conductor portion 10C for the connection hole can be lowered as compared with the case where the thick conductor film 10C ₂ is composed of Al, Al alloy, tungsten or tungsten alloy, In addition, the EM resistance of the connecting conductor portion 10C can be improved. In the case where the thick conductor film 10C ₂ is made of Al or Al alloy, the resistance of the connecting conductor portion 10C can be lowered as compared with the case of tungsten or tungsten alloy. In addition, when the buried conductor film 10C ₂ is made of tungsten or tungsten alloy, the EM resistance and SM resistance of the connection conductor part 10C can be improved compared to the case where the buried conductor film 10C ₂ is made of Al or AL alloy. It becomes possible. Although not particularly limited, in the first embodiment, the thick conductor film 10C ₂ is made of, for example, tungsten.

Further, in the interlayer insulating film 4b, a connection hole 8c which is punched from the upper surface toward the upper surface of the first layer wiring 6L and exposed by a part of the first layer wiring 6L is drilled. 8c) is formed with the connection conductor portion 10C embedded. The diameter of this connection hole 8c is about 0.2-1.2 micrometer, for example, Preferably it is about 0.4 micrometer. The aspect ratio of the connection hole 8c is preferably about 2 to 6 and smaller than about 4 in consideration of satisfactory embedding of the connection conductor portion. The connecting conductor portion 10C has the same structure as described above, but is not directly connected to the second layer wiring 9L in FIG. However, the constituent materials of the thick conductor film 10C2 of the connection conductor portion 10C embedded in the connection hole 8c and the thin conductor film 10C ₁ are embedded in the connection conductor portion 10C embedded in the connection hole 8b. thick conductor film (10C ₂₎ and the constituent material of the thin conductor film (10C ₁₎ and may be composed of other kinds of conductive material.

In the above description, the case where the second layer wiring 9L in the wiring grooves 5c and 5d is made of the same material has been described, but the present invention is not limited thereto. For thicker conductor film example embedded in the wiring grooves (5d) (9L ₂₎ and the thick conductor embedding the material of the thin conductor film (9L ₁₎ on the wiring groove (5c) the film (9L ₂₎ and the thin conductor films ( and the material of the 9L ₁₎ may be composed of other kinds of conductive material. This is because, for example, when attempting to embed Cu or the like in the wide wiring groove 5c and the narrow wiring groove 5d at the same time, the narrow wiring groove 5d may not be sufficiently buried. The wide wiring groove 5c is embedded in Cu, and the narrow wiring groove 5d is a structure example in which tungsten or the like is embedded by CVD or the like. In addition, the formation method in this case is mentioned later.

On the interlayer insulating film 4b, like the interlayer insulating film 4b, for example, an interlayer insulating film 4c composed of a silicon nitride film 4c ₁ and a silicon oxide film 4c ₂ is formed. Wiring grooves 5e and 5f having different widths are formed on the interlayer insulating film 4c. The depths of the wiring grooves 5e and 5f are the same, and are, for example, about 0.3 to 1.04 µm, preferably about 0.6 µm. The aspect ratio of the wiring groove 5e is, for example, about 0.1 to 1.0, preferably smaller than 0.7 in consideration of satisfactory filling of the wiring conductor film. The aspect ratio of the wiring groove 5f is, for example, about 0.5 to 2.5, and preferably smaller than 1.5 in consideration of satisfactory filling of the wiring conductor film.

In the wiring grooves 5e and 5f, as shown in Fig. 1, the third layer wiring 11L is formed in a buried state. This third layer wiring 11L is composed of a relatively thin conductor film 11L ₁ at the lower and side portions and a relatively thick conductor film 11L ₂ surrounded by the thin conductor film 11L ₁ .

The thin conductor film 11L ₁ is made of a material having a function of improving the adhesion between the third layer wiring 11L and the interlayer insulating film 4c or a barrier function of suppressing diffusion of members of the thick conductor film 11L ₂ . For example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN.

When the thin conductor film 11L ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case of the thin conductor film 11L ₁ made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. In addition, when the thin conductor film 11L ₁ is made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, TaSiN, or the like, adhesion with the interlayer insulating film 4c can be particularly improved. Although not particularly limited, in the first embodiment, the thin conductor film 11L ₁ is made of TiN, for example.

The thick conductor film 11L ₂ is a member constituting the main body of the third layer wiring 11L. For example, it consists of low-resistance materials, such as A1, A1 alloy, tungsten, tungsten alloy, Cu or Cu alloy. When the thick plating film 11L ₂ is made of Cu or Cu alloy, the wiring resistance can be significantly reduced as compared with the case of Al or tungsten. Further, the EM resistance of the third layer wiring 11L can be improved as compared with the case where the thick conductor film 11L ₂ is made of Al or Al alloy. Although not particularly limited, in the first embodiment, the thick conductor film 11L ₂ is made of, for example, Cu.

However, the structure of the third layer wiring 11L is not limited to the structure shown in FIG. 1 but can be variously changed. For example, the structure shown in FIGS. 3 to 5 described as the first layer wiring 6L. You may also That is, any structure may be provided with a cap conductive film on the upper surface of the thick conductor film (11L ₂₎ and a thin conductor film (11L _1). The cap conductor film is made of a low resistance material such as tungsten or the like or a material having a barrier function such as TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. This structure can further suppress the diffusion of Cu atoms by applying the thick conductor film 11L _{2 made} of Cu or Cu alloy to further improve the reliability of the semiconductor integrated circuit device. Further, although not particularly limited, it is suitable for the case when directly contact the wiring material and thick film conductor (11L ₂₎ in relation to the material of the upper layer wiring discard the like high resistivity alloy formed. The cap conductor film may be provided only on the upper surface of the thick conductor film 11L ₂ so that the upper surface thereof substantially coincides with the upper surface of the interlayer insulating film 4a.

It may be a structure configured by the third wiring layer (11L) of only the thick film conductor (11L ₂₎ As another structure. That is, it is a structure without a thin conductor film. As another structure, in the structure without the thin conductor film, the structure in which the cap conductor film is provided in the upper surface of the wiring groove 5a may be sufficient. This structure is not particularly limited, but is suitable for direct contact when the wiring material and thick film conductor (11L ₂₎ in relation to the material of the upper layer wiring discard the like high resistivity alloy formed.

The third layer wiring 11L formed in the wiring grooves 5e and 5f is electrically connected to the second layer wiring 9L through the connecting conductor portion 12C. Most of the connection conductor portion 12C is embedded in the connection hole 8d which is punched in the interlayer insulating film 4c toward the upper surface of the second layer wiring 9L from the bottom surfaces of the wiring grooves 5e and 5f. However, the upper portion of the connection conductor portion 12C protrudes into the third layer wiring 11L so as to pass through the upper and lower surfaces of the third layer wiring 11L. The diameter of the connection hole 8d is, for example, about 0.5 to 1.2 m, preferably about 0.4 m, for example. In addition, the aspect ratio of the connection hole 8d is preferably less than about 4 in consideration of satisfactorily embedding the connection conductor portion about 2 to 8 degrees. The height of the upper surface of the connecting conductor portion 12C substantially coincides with the height of the upper surface of the third layer wiring 11L, that is, the height of the upper surface of the interlayer insulating film 4c.

The connecting conductor portion 12C is composed of a relatively thin conductor film 12C ₁ and a relatively thick conductor film 12C ₂ surrounded by a thin conductor film 12C ₁ , for example. The thin conductor film 12C ₁ is made of a material having a function of improving the adhesion between the connecting conductor portion 12C and the interlayer insulating film 4c and a barrier function of suppressing diffusion of members of the thick conductor film 12C ₂ , For example, it consists of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN.

In the case where the thin conductor film 12C ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case of being made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the first embodiment, the thin conductor film 12C ₁ is made of, for example, tungsten.

The thick conductor film 12C ₂ is a member constituting the main body of the connecting conductor portion 12C, and is made of a low resistance material such as, for example, A1, A1 alloy, tungsten, tungsten alloy, Cu or Cu alloy. By forming the thick conductor film 12C _{2 with} , for example, Cu or a Cu alloy, the resistance of the connection hole conductor portion 12C can be lowered as compared with the case where the thick conductor film 12C ₂ is made of Al, Al alloy, tungsten or tungsten alloy. EM resistance of the connection conductor part 12C can be improved. In the case where the thick conductor film 12C ₂ is made of Al or Al alloy, the resistance of the connecting conductor portion 12C can be lowered as compared with the case of tungsten or tungsten alloy. In addition, when the thick conductor film 12C ₂ is made of tungsten or tungsten alloy, the EM resistance and SM resistance of the connecting conductor portion 12C can be improved as compared with the case where the thick conductor film 12C ₂ is made of Al or Al alloy. It becomes possible. Although not particularly limited, in the first embodiment, the thick conductor film 12C ₂ is made of, for example, tungsten.

Further, in the interlayer insulating film 4c, a connection hole 8e is drilled from the upper surface toward the upper surface of the second layer wiring 9L, and a part of the second layer wiring 9L is exposed. 8e) is formed with the connection conductor portion 12C embedded. The diameter of this connection hole 8e is, for example, about 0.2 to 1.2 mu m, preferably about 0.5 mu m, for example. The aspect ratio of the connection hole 8e is preferably about 2 to 6 and smaller than about 4 in consideration of satisfactory embedding of the connection conductor portion. The connecting conductor portion 12C has the same structure as described above, but is not directly connected to the third wiring layer 11L in FIG. Moreover, this connection conductor part 12C is in contact with and electrically connected to 10 C of connection conductor parts formed in the connection hole 8c of the lower layer. That is, in the first embodiment, in the wiring layer having the buried wiring structure, the connecting conductor portions 10C and 12C are electrically connected to each other in a state where they pass through the predetermined wiring layer. By forming the connection conductor portion 12C from the same constituent material as the connection conductor portion 10C, the connection resistance can be reduced. In other words, the contact resistance and the like can be lowered as compared with the case where the connection conductor portions 10C and 12C are connected via the second layer wiring 9L made of different conductor material, so that the connection resistance can be reduced.

However, the connection conductor portion 12C in which the constituent materials of the thick conductor film 12C ₂ and the thin conductor film 12C ₁ of the connection conductor portion 12C embedded in the connection hole 8e are embedded in the connection hole 8e. The thick conductor film 12C ₂ and the thin conductor film 12C ₁ may be made of a different kind of conductor material.

In addition, as shown in FIG. 7, the connection structure between the connecting conductor portions 10C and 12C on the right side of FIG. 1 is connected to the interlayer insulating film 4c by the third layer wiring 11L and the first layer wiring 6L. ), And may be electrically connected directly via one connection conductor 12C in the connection hole 8e ₁ penetrating through (4b). Thereby, connection resistance can be reduced.

On the interlayer insulating film 4c, like the interlayer insulating film 4b, for example, an interlayer insulating film 4d composed of a silicon nitride film 4d ₁ and a silicon oxide film 4d ₂ is formed. A fourth layer wiring 13L is formed on the upper surface of this interlayer insulating film 4d. The fourth layer wirings 13L and 13L are made of, for example, Al or Al alloy, and the lower third layer wirings (8f, 8f), which are drilled in the interlayer insulating film 4d, respectively, 11L) and the connecting conductor portion 12C.

As the constituent material of the uppermost fourth layer wiring 13L, for example, A1 or A1 alloy can be used, whereby conventional bonding wire connection technology and bump electrode formation technology can be followed. In other words, although the bonding wire and the bump electrode are connected to the best wiring layer, the conventional wiring phase and the bonding electrode of the bump electrode can be used as it is by making the best wiring material A1 or A1 alloy conventionally used. For this reason, a semiconductor integrated circuit device having a buried wiring structure made of Cu-based material can be introduced into the assembly line without involving technical changes in the assembly process (wire bonding process or bump electrode forming process). Therefore, the cost reduction of the semiconductor integrated circuit device having the buried wiring made of Cu-based material can be promoted, and the production and development time can be shortened.

The diameter of the connection hole 8f is, for example, about 0.2 to 1.2 mu m, preferably about 0.5 mu m, for example. The aspect ratio of the connection hole 8f is preferably about 2 to 6 and smaller than 4 information in consideration of good embedding of the connection conductor portion. A connection conductor portion 14C is embedded in the connection hole 8f. The connecting conductor portion 14C is composed of a relatively thin conductor film 14C ₁ at the lower and side portions thereof and a relatively thick conductor film 14C ₂ surrounded by the thin conductor film 14C ₁ . The connecting conductor 14C does not penetrate the fourth layer wiring 13L.

The thin conductor film 14C ₁ is made of a material having a function of improving adhesion between the connecting conductor portion 14C and the interlayer insulating film 4d and a barrier function of suppressing diffusion of members of the thick conductor film 14C ₂ , For example, it consists of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. In the case where the thin conductor film 14C ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case of being made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the first embodiment, the thin conductor film 14C ₁ is made of, for example, tungsten.

The thick conductor film 14C ₂ is a member constituting the main body of the connecting conductor portion 14C, and is made of a low resistance material such as an Al or Al alloy, tungsten or tungsten alloy. In the case where the thick conductor film 14C ₂ is made of Al or Al alloy, the resistance of the connecting conductor portion 14C can be lowered compared with the case of tungsten or tungsten alloy. In addition, when the thick conductor film 14C ₂ is made of tungsten or tungsten alloy, the EM resistance and SM resistance of the connecting conductor portion 14C can be improved as compared with the case where the thick conductor film 14C ₂ is made of Al or Al alloy. It becomes possible. In the case where the thick conductor film 14C _{2 is} formed of tungsten or tungsten alloy, the Cu constituting the third layer wiring 11L and the A ℓ or Aℓ alloy constituting the fourth layer wiring 13L are made of a thick barrier metal. Since it can isolate | separate, resistance rise can be prevented easily by reaction of both. That is, by embedding a material having a barrier function in the connection hole 8, the third layer wiring made of Cu-based material and the fourth layer wiring 13L made of Se-based material can isolate the distance. It can reduce by reaction of both. Although not particularly limited, in the first embodiment, the thick conductor film 14C ₂ is made of, for example, tungsten.

A surface protective film 15 is formed on the interlayer insulating film 4d, whereby the surface of the fourth layer wiring 13L is covered. The surface protective film 15 is, for example, a protective film 15b on the protective film 15a. ) Is laminated, for example, the protective film 15a is made of SiO ₂ , and the upper protective film 15b is made of, for example, silicon nitride. A portion of the surface protective film 15 is formed with an opening 16 through which a portion of the fourth layer wiring 13L is exposed. In the 4th layer wiring 13L, the part exposed by this opening part 16 forms the bonding pad part BP. In other words, the bonding wires are directly connected to the bonding pads BP, and the leads of the packages constituting the semiconductor integrated circuit device are electrically connected thereto. Further, a bump electrode made of lead-tin alloy, gold, or the like may be provided on the bonding pad portion BP via a base metal layer. The above-described interlayer insulating films 4a to 4d are, for example, coating films formed by SOG (Spin On Glass), organic films, CVD films containing fluorine, silicon nitride films or laminated films formed by laminating them. It may be a back.

Next, the manufacturing method of the semiconductor integrated circuit device of the first embodiment will be described with reference to FIGS.

First, a method of forming a buried wiring made of the same material will be described with reference to FIGS. In addition, since the structures of the first layer wiring 6L, the second layer wiring 9L, and the third layer wiring 11L are the same here, the first layer wiring 6L is embedded as a representative example for the sake of simplicity. The formation method of wiring is demonstrated.

8 is a sectional view of an essential part of a semiconductor integrated circuit device in a manufacturing process; In the interlayer insulating film 4a formed on the semiconductor substrate 1, connection holes 8a exposed by the main surface (semiconductor region 3nd) of the semiconductor substrate 1 are already drilled by photolithography and dry etching techniques. have. The interlayer insulating film 4a may be, for example, a silicon oxide film, a silicon oxide film formed by a SOG (Spin On Glass) method, an organic film, a CVD-added CVD film, a silicon nitride film, or a laminated film formed by laminating them. Is done. The surface of the interlayer insulating film 4a is flattened by, for example, polishing a silicon oxide film deposited by CVD (Chemical Vapor Deposition) method by CMP method or the like.

Subsequently, as shown in Fig. 9, for example, tungsten (W) sputtering a thin conductive film (7C ₁₎ made of, such as on the top surface, side surfaces and bottom surface of the connection hole (8a) of the interlayer insulating film (4a) It deposits by etc. A thin conductive film (7C ₁₎ is a diffusion or thick conductive film (7C _2), such as material gas in the form of a function or thick conductive film (7C ₂₎ to improve the adhesion of the connecting purpose body and the interlayer insulating film (4a) It is made of a material having a barrier function for suppressing diffusion of members, and is not limited to tungsten, but can be variously changed. For example, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN may be used.

Thereafter, a thick conductor film 7C ₂ made of, for example, tungsten or the like is deposited on the thin conductor film 7C ₁ by the CVD method or the like. Thereby, the conductor film can be satisfactorily filled in the fine connection hole 8a. The thick conductor film 7C ₂ is not limited to tungsten or the like and can be variously changed. For example, a low-resistance material such as Al or Al alloy may be used. In addition, the method of forming the thick film conductor (7C ₂₎ is not limited to the CVD method, for example, it may be such that a combination of a plating method or a sputtering method, CVD method, plating method.

In the second layer wiring and the third layer wiring, however, Cu or Cu alloy may be used as the material for forming the thick conductor film of the connecting conductor portions 10C and 12C (see Fig. 1). In this case, for example, a CVD method or a plating method may be used as the Cu film formation method.

Next, the semiconductor substrate 1 is subjected to, for example, a CMP (Chemical Mechanical Polishing) process, so that the thick conductor film 7C ₂ on the interlayer insulating film 4a in the region other than the connection hole 8a. By removing the thin conductor film 7C ₁ , the connection conductor portion 7C is formed in the connection hole 8a as shown in FIG. 10.

Subsequently, as shown in FIG. 11, after forming the wiring groove forming photoresist pattern 17a on the interlayer insulating film 4a, using this as an etching mask, the interlayer insulating film exposed by the photoresist pattern 17a. By removing the portion (4a), the wiring groove 5a and the wiring groove 5b (see Fig. 1) are formed on the interlayer insulating film 4a. At this time, the upper part of the connection conductor part 7C previously formed in the wiring groove 5a protrudes.

Then, after removing the photoresist pattern 17a, as shown in FIG. 12, the surface of the interlayer insulating film 4a including the wiring groove 5a and the exposed surface of the connection conductor portion 7C, for example, TiN. A thin conductor film 6L ₁ made of or the like is deposited by the sputtering method or the like. The thin conductor film 6L ₁ is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of members of the thick conductor film, and not limited to TiN. Various changes are possible, for example, tungsten, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN may be used.

Next, a thick conductor film 6L ₂ made of, for example, Cu or the like is deposited on the thin conductor film 6L ₁ by the CVD method, the sputtering method, the plating method, or a combination thereof. In the film formation of Cu or the like, it is preferable to adopt a method with a small overhang and a good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is more than the radius of the semiconductor wafer is suitable. The thick conductor film 6L ₂ is not limited to Cu and can be variously modified. For example, a Cu alloy, an Al alloy, an Al alloy, tungsten or a tungsten alloy may be used.

In the case where the above-mentioned wiring conductor film is formed by sputtering, in particular, the semiconductor substrate 1 is subsequently subjected to a heat treatment, whereby a member (for example, Cu) of the thick conductor film 6L ₂ is made to flow. The member 5 is sufficiently supplied with the member 5 in the groove 5a. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. Moreover, you may employ | adopt what is called the reflow sputtering method which performs this heat processing in the middle of sputtering of Cu. By these, the EM characteristic of Cu wiring can be improved.

After that, the CMP process is performed on the semiconductor substrate 1 to form a thick conductor film 6L ₂ on the interlayer insulating film 4a in regions other than the wiring grooves 5a and 5b (see FIG. 1). And the thin conductor film 6L ₁ is removed to form the first layer wiring 6L shown in FIG. 2 and the like.

The semiconductor substrate 1 may be heat-treated after this CMP treatment or before the treatment. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. In the heat treatment step after the CMP treatment, the Cu particles of the thick conductor film 6L ₂ are promoted to improve EM resistance, and at the same time, the thin conductor film 6L ₁ and the thick conductor film 6L ₂ are subjected to CMP treatment. The surface is smoothed by removing any damage or oxide film on the surface. At the same time, surface contamination of the insulating film 4a is eliminated and reduced. As a result, the reliability of the wiring can be improved.

Next, a method of forming a buried wiring made of conductor materials having different materials in the same buried wiring layer will be described with reference to FIGS. 13 to 18. This corresponds to the example of the formation method in the case where the wiring which consists of conductor materials from which material differs exists in the same wiring layer mentioned above. In addition, in Example 1, the case where the 1st layer wiring 6L which consists of conductor materials from which material differs in the wiring groove 5a, 5b is formed as a representative example.

13 is a principal perspective view of the interlayer insulating film 4a during the manufacturing process of the semiconductor integrated circuit device. On the upper portion of the interlayer insulating film 4a, a wiring groove 5a is formed by a photolithography technique and a dry etching technique.

Subsequently, as shown in Fig. 14, for example on the surface of the interlayer insulating film (4a) comprising a wiring trench (5a) is deposited by a thin film conductor (6L ₁₎ consisting of TiN, such as a sputtering method. The thin conductor film 6L ₁ is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of members of the thick conductor film, and not limited to TiN. Various changes are possible, for example, tungsten, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN may be used.

Thereafter, a thick conductor film 6L ₂ made of, for example, Cu or the like is deposited on the thin conductor film 6L ₁ by a CVD method, a sputtering method, a plating method, or the like. In the film formation of Cu or the like, it is preferable to adopt a method with as few overhangs as possible and having a good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is more than the radius of the semiconductor wafer is suitable. The thick conductor film 6L ₂ is not limited to Cu and can be variously modified. For example, a Cu alloy, an Al alloy, an Al alloy, tungsten or a tungsten alloy may be used.

In the case where the above-mentioned wiring conductor film is formed by sputtering, in particular, the semiconductor substrate 1 is subsequently subjected to heat treatment, whereby a member (for example, Cu) of the thick conductor film is flowed into the wiring groove 5a. Sufficiently supply the members and bury them. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. Moreover, you may employ | adopt what is called the reflow sputtering method which performs this heat processing in the middle of sputtering of Cu. As a result, the EM characteristics of the Cu wiring can be improved.

Subsequently, the CMP process is performed on the semiconductor substrate 1, so that the thick conductor film 6L ₂ and the thin conductor film 6L ₁ on the interlayer insulating film 4a in the region other than the wiring groove 5a. As shown in Fig. 15, the first layer wiring 6L is formed in the wiring groove 5a.

The semiconductor substrate 1 may be heat-treated after this CMP treatment or before the treatment. At this time, the heat treatment atmosphere is one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or a combination of two or more thereof. In the heat treatment step after the CMP treatment, the Cu particles of the thick conductor film 6L ₂ are promoted to improve EM resistance, and at the same time, the thin conductor film 6L ₁ and the thick conductor film 6L ₂ are subjected to CMP treatment. The surface is smoothed by removing any damage or oxide film on the surface. At the same time, surface contamination of the insulating film 4a is eliminated and reduced. As a result, the reliability of the wiring can be improved.

Then, as shown in FIG. 16, a wiring groove 5b that is narrower or shorter in length than the wiring groove 5a is formed in the upper portion of the interlayer insulating film 4a by photolithography and dry etching techniques. do. At this time, the depth of the wiring groove 5b may be the same as the wiring groove 5a, but may be set to a depth different from the depth of the wiring groove 5a. For example, as shown in FIG. 17, the depth of the wiring groove 5b may be made deeper than the depth of the wiring groove 5a. In this case, since the wiring groove 5b is narrow but deep, the wiring resistance of the conductor film embedded in the wiring groove 5b can be reduced. Alternatively, the wiring groove 5b may be deepened to reach the lower wiring layer or the semiconductor substrate and used for connection.

Next, sputtering a thin conductor film made of, for example, tungsten or the like on the surface of the interlayer insulating film 4a including the upper surface of the first layer wiring 6L and the wiring groove 5b in the wiring groove 5a as described above. We are deposited by law. The thin conductor film is made of a material having a function of improving adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of members of the thick conductor film, and not limited to tungsten, and can be variously modified. For example, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN may be used.

Subsequently, a thick conductor film made of, for example, tungsten or the like is deposited on the thin conductor film by CVD or the like. In the film formation of tungsten or the like, it is preferable to adopt a method with a small overhang and a good step coverage. As a result, even in the narrow wiring groove 5b and as shown in FIG. 17, the wiring conductor can be satisfactorily filled in the wiring groove 5b deeper than the wiring groove 5a. This thick conductor film is not limited to tungsten, but can be variously modified. For example, a tungsten alloy, an Al or Al alloy may be used.

Next, the CMP process is performed on the semiconductor substrate 1 to remove the thick conductor film and the thin conductor film in the region other than the wiring groove 5b. As shown in FIG. The thin conductor film 6L ₁ and the thick conductor film 6L _{2 in the} wiring groove 5a in the wiring groove 5b narrower in width than the 5a are made of a thin conductor film 6L ₁ made of a conductor material of different materials and A first layer wiring 6L made of a thick conductor film 6L ₂ is formed.

Thus, according to the first embodiment, the following effects can be obtained.

[One]. After filling the conductor film in the fine connection holes 8a to 8f by using the CVD method or the like, the wiring grooves 5a to 5f having a larger plane dimension than the connection holes 8a to 8f are formed. By filling the conductor film in the wiring grooves 5a to 5f, the first layer wiring 6L, the connection conductor portion 7C, the second layer wiring 9L, the connection conductor portion 10C, and the first structure of the buried structure By forming the three-layer wiring 11L and the connection conductor portion 12C, the conductor film can be satisfactorily embedded in both the wiring grooves 5a to 5f and the finer connection holes 8a to 8f. It becomes possible.

[2]. In the case of having wiring grooves having different dimensions in the same wiring layer, the conductive film is buried in both wiring grooves by selecting a method which is easy to embed into fine wiring grooves or larger wiring grooves. It becomes possible.

[3]. [1] or [2] can improve the reliability of the connection between the wiring layers. Therefore, the manufacturing efficiency and reliability of the semiconductor integrated circuit device can be improved.

[4]. [1] or [2] enables the miniaturization of the buried wiring to be promoted. Therefore, it is possible to promote miniaturization or high integration of the semiconductor integrated circuit device.

[5]. [1] or [2] above allows the conductor film to be well embedded in the wiring grooves 5a to 5f and the connection holes 8a to 8f without employing a difficult technique.

[6]. [1] or [2] above makes it possible to improve the embedded state even when Cu, Cu alloy, or the like is used as the embedding wiring material.

[7]. The connection conductor portion 7C in direct contact with the semiconductor substrate 1 is made of a tungsten-based (tungsten or tungsten alloy) conductor material, and the first layer wiring 6L connected to the connection conductor portion 7C is low. Consisting of the Cu-based conductor material of resistance prevents the diffusion of Cu atoms to the semiconductor substrate 1 side while maintaining the state of embedding of the conductor film in the connection hole 8a well, resulting in poor connection due to the diffusion phenomenon. In addition, it is possible to reduce the wiring resistance of the first layer wiring 6L and improve the signal propagation speed.

[8]. By constructing the uppermost 4th layer wiring 13L from the conductor material of AL system (Al or AL alloy), assembly techniques, such as a conventional wire bonding technique and a bump electrode formation technique, can be followed as it is. Therefore, the semiconductor integrated circuit device having the Cu-based buried wiring can be easily introduced into the assembly process.

[9]. The connection conductor part 14C which consists of tungsten-type conductor materials was provided between the 4th layer wiring 13L which consists of AL type conductor materials, and the 3rd layer wiring 11L which consists of Cu-based conductor materials below. As a result, the Al-based conductor material and the Cu-based conductor material can be separated by a thick barrier metal. Therefore, when the Al-based conductor material is directly contacted with the Cu-based conductor material, an alloy layer having a high resistivity is formed at the contact portion. Since discarding can be prevented, the resistance between wiring layers can be reduced.

[10]. By heat-treating the semiconductor substrate 1 after the CMP treatment for forming the buried wiring made of the Cu-based conductor material, Cu growth of particles is promoted to improve EM resistance and wiring at the time of CMP treatment. It is possible to eliminate the damage or oxide film generated on the surface of the conductor film, to smooth the surface thereof, and to reduce and reduce the surface contamination of the insulating film exposed during CMP, thereby improving the reliability of the buried wiring made of the Cu-based conductor material. .

Example 2

19 to 23 are main sectional views of the semiconductor integrated circuit device in accordance with another embodiment of the present invention during the manufacturing process, and FIG. 24 is a sectional view of the main integrated circuit device.

In the second embodiment, the structure of the connecting conductor portion and the formation method thereof are different from those in the first embodiment.

First, as shown in FIG. 19, after forming the wiring groove forming photoresist pattern 17b on the upper surface of the interlayer insulating film 4a, the etching process is performed using the photoresist pattern 17b as an etching mask. Thus, the wiring groove 5a is formed on the interlayer insulating film 4a.

Subsequently, after removing the photoresist pattern 17b, as shown in FIG. 20, after forming the connection hole forming photoresist pattern 17c on the interlayer insulating film 4a, the photoresist pattern 17c is removed. By performing an etching process as an etching mask, the connection hole 8a extending from the bottom surface of the wiring groove 5a toward the semiconductor substrate 1 and exposing a part of the upper surface of the semiconductor substrate 1 is exposed. Perforations are made with the interlayer insulating film 4a.

After that. After removing the photoresist pattern 17c, as shown in FIG. 21, a connection conductor portion 7C made of, for example, tungsten or the like is formed in the connection hole 8a by a selective CVD method or the like. At this time, the upper portion of the connection conductor portion 7C may protrude into the wiring groove 5a. The material of the connection conductor portion 7C is not limited to tungsten, but can be variously changed. For example, a tungsten alloy, an Al or an Al alloy may be used.

Next, as shown in FIG. 22, the thin conductor film 6L ₁ which consists of TiN etc. on the surface of the interlayer insulation film 4a containing the wiring groove 5a, and the exposed surface of the connection conductor part 7C, for example. ) Is deposited by sputtering or the like. The thin conductor film 6L ₁ is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of members of the thick conductor film, and not limited to TiN. Various changes are possible, for example, tungsten, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN may be used.

Subsequently, a thick conductor film 6L ₂ made of, for example, Cu or the like is deposited on the thin conductor film 6L ₁ by the CVD method, the sputtering method or the plating method. In the film formation of Cu or the like, it is preferable to adopt a method with a small overhang and a good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is more than the radius of the semiconductor wafer is suitable. The thick conductor film 6L ₂ is not limited to Cu and can be variously modified. For example, a Cu alloy, an Al alloy, an Al alloy, tungsten or a tungsten alloy may be used.

In the case where the above-mentioned wiring conductor film is formed by sputtering, in particular, the semiconductor substrate 1 is subsequently subjected to heat treatment, whereby a member (for example, Cu) of the thick conductor film is made to flow in the wiring groove 5a. Sufficiently supply the members and bury them. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. Moreover, you may employ | adopt what is called the reflow sputtering method which performs this heat processing in the middle of sputtering of Cu. As a result, the EM characteristics of the Cu wiring can be improved.

Subsequently, the CMP process is performed on the semiconductor substrate 1, so that the thick conductor film 6L ₂ and the thin conductor film 6L ₁ on the interlayer insulating film 4a in the region other than the wiring groove 5a. 23, the first layer wiring 6L is formed in the wiring groove 5a as shown in FIG.

The semiconductor substrate 1 may be heat-treated after this CMP treatment or before the treatment. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. In the heat treatment step after the CMP treatment, the Cu particles in the thick conductor film 6L ₂ are promoted to improve EM resistance, and at the same time, the thin conductor film 6L ₁ and the thick conductor film 6L ₂ are subjected to CMP treatment. The surface is smoothed without any damage or oxide film on the surface. At the same time, surface contamination of the insulating film 4a is eliminated and reduced. As a result, the reliability of the wiring can be improved.

Further, such a buried wiring structure is as shown in FIG. You may apply to 9L of 2nd layer wiring. That is, the connection conductor portion 10C has a structure made of a conductor film such as tungsten, tungsten alloy, A1, A1 alloy, Cu, or Cu alloy formed by selective CVD.

According to this second embodiment, the same effect as in the first embodiment can be obtained.

Example 3

25 to 28 and 29 to 32 are cross-sectional views of major parts in the manufacturing process of the semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 33 is a cross-sectional view of main parts of the semiconductor integrated circuit device.

25 shows a semiconductor integrated circuit device in the manufacturing process. In the interlayer insulating film 4a, the wiring groove 5a and the connection hole 8a are formed by the method described in the second embodiment.

First, in the third embodiment, as shown in Fig. 26, a connection conductor portion 7C made of, for example, tungsten or the like is formed in the connection hole 8a by the selective CVD method. At this time, in the third embodiment, the film forming process is performed such that the upper portion of the connection conductor portion 7C protrudes outward from the wiring groove 5a. The material of the connection conductor portion 7C is not limited to tungsten, but can be variously changed. For example, a tungsten alloy, an Al or an Al alloy may be used.

Subsequently, as shown in FIG. 27, the thin conductor film 6L ₁ which consists of TiN etc. on the surface of the interlayer insulation film 4a containing the wiring groove 5a, and the surface of the connection conductor part 7C, for example. Is deposited by the sputtering method or the like. The thin conductor film 6L ₁ is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of the members of the thick conductor film. The present invention is not limited to TiN, and various modifications are possible, for example tungsten, Ti, Ta, WN, WSiN. TiSiN, TaN, TaSiN, or the like may be used.

Subsequently, a thick conductor film 6L ₂ made of, for example, Cu or the like is deposited on the thin conductor film 6L ₁ by the CVD method, the sputtering method or the plating method. In the film formation of Cu or the like, it is preferable to adopt a method with a small overhang and a good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is more than the radius of the semiconductor wafer is suitable. This thick conductor film 6L ₂ is not limited to Cu but can be modified in various ways. For example, a Cu alloy, A1, A1 alloy, tungsten or tungsten alloy may be used.

In the case where the above-mentioned wiring conductor film is formed by sputtering, in particular, the semiconductor substrate 1 is subsequently subjected to heat treatment, whereby a member (for example, Cu) of the thick conductor film is caused to flow and into the wiring groove 5a. Sufficiently supply the members and bury them. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, and a reducing gas atmosphere are combined. Moreover, you may employ | adopt what is called the reflow sputtering method which performs this heat processing in the middle of sputtering of Cu. Thereby, EM characteristic of Cu wiring can be improved.

Subsequently, the CMP process is performed on the semiconductor substrate 1, so that the thick conductor film 6L ₂ and the thin conductor film 6L ₁ on the interlayer insulating film 4a in the region other than the wiring groove 5a. As shown in Fig. 28, the first layer wiring 6L is formed in the wiring groove 5a, and at the same time, the connection conductor 7C is formed.

The semiconductor substrate 1 may be heat-treated after this CMP treatment or before the treatment. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. In the heat treatment step after the CMP treatment, the Cu conductive particles 6L ₂ promote the grain growth of Cu to improve EM resistance, and at the same time, the surface of the thin conductor film 6L ₁ and the thick conductor film 6L ₂ during CMP treatment. Removes any damage or oxide film on the surface and makes the surface smooth. At the same time, surface contamination of the insulating film 4a is eliminated and reduced. As a result, the reliability of the wiring can be improved.

Incidentally, in order to form a buried wiring as shown in the structure of FIG. 28, for example, it may be as follows.

First, as shown in FIG. 29, the connection hole 8a is formed by photolithography and dry etching so that a part of the upper surface of the semiconductor substrate 1 is exposed to the interlayer insulating film 4a.

Subsequently, as shown in FIG. 30, a connection conductor portion 7C made of, for example, tungsten or the like is formed in the connection hole 8a by selective CVD. At this time, the film forming process is performed such that the upper surface of the connection conductor portion 7C is approximately equal to the upper surface of the interlayer insulating film 4a. The material of the connection conductor portion 7C is not limited to tungsten, but can be variously changed. For example, a tungsten alloy, an Al or an Al alloy may be used.

Thereafter, as shown in FIG. 31, the wiring groove 5a is formed in the interlayer insulating film 4a by photolithography and dry etching techniques. At this time, the upper part of the connection conductor part 7C is exposed in the wiring groove 5a.

32, the thin conductor film 6L ₁ which consists of TiN etc. on the surface of the interlayer insulation film 4a containing the wiring groove 5a, and the exposed surface of the connection conductor part 7C, for example. ) Is deposited by sputtering or the like. The thin conductor film 6L ₁ is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4a and a barrier function of suppressing diffusion of members of the thick conductor film, and not limited to TiN. Various changes are possible, for example, tungsten, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN may be used.

Subsequently, a thick conductor film 6L ₂ made of, for example, Cu or the like is deposited on the thin conductor film 6L ₁ by the CVD method, the sputtering method or the plating method. In the film formation of Cu or the like, it is preferable to adopt a method with a small overhang and a good step coverage. For example, in the sputtering method, a sputtering apparatus in which the distance between the target and the semiconductor wafer is more than the radius of the semiconductor wafer is suitable. The thick conductor film 6L ₂ is not limited to Cu and can be variously modified. For example, a Cu alloy, an Al alloy, an Al alloy, tungsten or a tungsten alloy may be used.

In the case where the above-mentioned wiring conductor film is formed by sputtering, in particular, the semiconductor substrate 1 is subsequently subjected to heat treatment, whereby a member (for example, Cu) of the thick conductor film is made to flow in the wiring groove 5a. Sufficiently supply the members and bury them. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. Moreover, you may employ | adopt what is called the reflow sputtering method which performs this heat processing in the middle of sputtering of Cu.

Subsequently, the semiconductor substrate 1 is subjected to a CMP process so that the thick conductor film 6L ₂ and the thin conductor film 6L ₁ on the interlayer insulating film 4a in the regions other than the wiring grooves 5a are formed. By removing it, as shown in FIG. 28, 6L of 1st layer wirings are formed in the wiring groove 5a, and the connection conductor part 7C is formed.

The semiconductor substrate 1 may be heat-treated after this CMP treatment or before the treatment. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. In this heat treatment step, Cu grain growth of the thick conductor film 6L ₂ is promoted to improve EM resistance, and at the same time, it is generated on the surfaces of the thin conductor film 6L ₁ and thick conductor film 6L ₂ during CMP treatment. Remove the damage or oxide film and smooth the surface. At the same time, surface contamination of the insulating film 4a is eliminated and reduced. As a result, the reliability of the wiring can be improved.

Further, such a buried wiring structure may be applied to the second layer wiring 9L as shown in FIG. That is, the connection conductor portion 10C has a structure made of a conductor film such as tungsten, tungsten alloy, A1, A1 alloy or the like formed by, for example, selective CVD.

As described above, according to the third embodiment, the same effects as those of the first embodiment can be obtained.

Example 4

34 and 35 are cross-sectional views of principal parts of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the fourth embodiment, as shown in Figs. 34 and 35, the connection conductor portions 7C and 10C are composed of thin conductor films 7C ₁ and 10C ₁ . In other words, the connection holes 8a and 8b are embedded with the thin conductor films 7C ₁ and 10C ₁ .

The thin conductor films 7C ₁ and 10C ₁ have a function of improving the adhesion between the connection conductor portions 7C and 10C and the interlayer insulating films 4a and 4b or a barrier function of suppressing diffusion of members of the wiring. It is made of a material having, for example, made of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN and the like.

The diameter of the connection hole 8a is about 0.1-0.4 micrometer, for example, Preferably it is about 0.2 micrometer. The aspect ratio of the connection hole 8a is preferably about 2 to 10 and smaller than about 5 in consideration of satisfactory embedding of the connection conductor portion.

Moreover, the diameter of the connection hole 8b is about 0.1-0.4 micrometer, for example, Preferably it is about 0.2 micrometer. In addition, the aspect ratio of the connection hole 8b is preferably about 2 to 10 and smaller than about 5 in consideration of satisfactory embedding of the connection conductor portion.

The structure of the wirings is not limited to the structures shown in FIGS. 33 and 34 and can be variously changed. For example, the structures shown in FIGS. 3 to 5 described in the first embodiment may be used.

Such a method of forming the buried wiring is the same as that described with reference to FIGS. 8 to 12 of the first embodiment. That is, the method of forming the first layer wiring 6L is as follows.

First, after connecting the connection hole 8a to the interlayer insulating film 4a, a thin conductor film 7C ₁ is deposited by sputtering or the like so as to fill the connection hole 8a on the interlayer insulating film 4a. Subsequently, by performing the CMP method or the like on the semiconductor substrate 1, a portion of the thin conductor film 7C ₁ other than the region of the connection hole 8a is removed, and the thin conductor in the connection hole 8a is removed. A connecting conductor portion 7C composed of only the film 7C ₁ is formed. After that, the wiring groove 5a is formed in the interlayer insulating film 4a, and then the wiring conductor film is deposited by sputtering, CVD, plating, or the like so as to embed the wiring groove 5a on the interlayer insulating film 4a. Subsequently, by performing the CMP method or the like on the semiconductor substrate 1, the portion of the wiring conductor film except for the region of the wiring groove 5a is removed to make the first layer wiring 6L in the wiring groove 5a. ).

The semiconductor substrate 1 may be heat-treated after the formation of the thick conductor film 6L ₁ or after the CMP treatment. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. The heat treatment promotes the growth of Cu in the thick conductor film 6L ₂ to improve EM resistance, and at the same time, the thin conductor film 6L ₁ and the thick conductor film 6L ₂ during CMP treatment. It is possible to eliminate the damage or oxide film generated on the surface, to smooth the surface thereof, and to eliminate and reduce the surface contamination of the insulating film 4a, thereby improving the reliability of the wiring.

According to this fourth embodiment, the same effect as in the first embodiment can be obtained.

Example 5

36 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. 37 is an enlarged cross-sectional view of a main part of the semiconductor integrated circuit device of FIG. 36, and FIG. 38 is a modified example of the main part of the semiconductor integrated circuit device shown in FIG. 39 is an enlarged cross-sectional view of an essential part, FIG. 39 is an enlarged cross-sectional view of an essential part of the semiconductor integrated circuit device shown in FIG. 37, FIG. 40 is an explanatory diagram schematically showing an essential part of the semiconductor integrated circuit device of FIG. 39, and FIG. Explanatory drawing which shows a modification typically, FIGS. 42 and 43 are explanatory drawing which shows a modification of FIG. 40, and FIGS. 44-48 show a modification of the principal part of the semiconductor integrated circuit device of FIG. It is an enlarged sectional view of the main part shown.

First, the structure of the semiconductor integrated circuit device of the fifth embodiment will be described with reference to Figs. The basic overall structure of the fifth embodiment is as follows, for example.

First, as the constituent material of the first layer wiring 6L, a conductor material other than Cu or Cu alloy such as tungsten, tungsten alloy, Al or Al alloy is used. As a result, the structure in which the Cu wiring is not brought into direct contact with the semiconductor substrate 1 can be obtained. Therefore, element defects caused by diffusion of Cu atoms toward the semiconductor substrate 1 can be suppressed, and the reliability of the semiconductor integrated circuit device can be suppressed. It will be possible to improve. In addition, the distance between the second and third layer wirings 9L and 11L made of Cu wiring and the semiconductor substrate 1 can be reduced to reduce diffusion of Cu atoms into the semiconductor substrate 1. .

Secondly, for example, A1 or A1 alloy is used as the constituent material of the highest fourth layer wiring 13L. As a result, the conventional bonding technology for bonding wires and the bump electrode forming technology can be followed. In other words, the best wiring layer is bonded wire or bump electrode. By making the best wiring material A1 or A1 alloy conventionally used, it is possible to use the prior art on the bonding wire and bump electrode as it is. For this reason, a semiconductor integrated circuit device having a buried wiring structure made of Cu-based material can be introduced into the assembly line without involving technical changes in the assembly process (wire bonding process or bump electrode forming process). Therefore, the cost reduction of the semiconductor integrated circuit device having the buried wiring made of Cu-based material can be promoted, and the manufacturing and development time can be shortened.

Third, for example, Cu or Cu alloy is used for the constituent material of the intermediate wiring layer (the second layer wiring 9L and the third layer wiring 11L) between the uppermost wiring layer and the lowermost wiring layer. As a result, the wiring resistance and the wiring capacitance can be reduced, and the signal propagation speed in the semiconductor integrated circuit device can be improved, and the operation speed thereof can be improved.

Fourth, the connecting conductor portions 18C and 19C for connecting the wiring layers made of Cu-based materials are made of a material made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. do. As a result, the conductive film can be satisfactorily embedded in the fine connection holes 8g and 8h, so that the reliability of the electrical connection between the wiring layers can be improved.

Fifth, the fourth layer wiring 13L made of AL-based material and the third layer wiring 11L made of Cu-based material are not in direct contact with each other, and a barrier layer (connection conductor portion 20C, etc.) is interposed therebetween. Intervene. As a result, the phenomenon in which an alloy layer having a high specific resistance is formed when the A-based material and the Cu-based material are in direct contact with each other can be suppressed, so that the propagation speed of the signal flowing through the wiring can be improved.

Sixth, the connection use formed in the wiring layer located in the part where the connection conductor part 19C and the connection conductor part 20C are connected at least planarly longer than the connection conductor parts 19C and 20C along the longitudinal direction of wiring. 21 C of body parts (relay connection conductor parts) were provided, and the said connection conductor parts 19C and 20 C of connection conductor parts were electrically connected. As a result, the planar area of the connection groove 5g in which the connection conductor portion 21C is formed can be made relatively large, so that the wiring conductor film can be satisfactorily embedded in the groove. Further, the planar alignment margin in the longitudinal direction of the wiring of the connection conductor portion 19C and the connection conductor portion 20C can be increased. Therefore, the reliability of the connection of the upper and lower connection conductor parts 19C and 20C can be improved.

Next, each component in the semiconductor integrated circuit device of the fifth embodiment will be described in detail.

The first layer is embedded in the wiring trench (5a), (5b) formed in the wiring (6L) is lower and relatively thin conductor film with a side portion (6L ₁₎ and the thin conductor film (6L ₁₎ relatively thick conductive film surrounded by the It consists of (6L _2). The thin conductor film 6L ₁ is made of a material having a function of improving the adhesion between the first layer wiring 6L and the interlayer insulating film 4a or a barrier function of suppressing diffusion of members of the thick conductor film 6L ₂ . For example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN and the like.

When the thin conductor film 6L ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case of being made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the fifth embodiment, the thin conductor film 6L ₁ is made of, for example, tungsten.

Further, the thick conductor film 6L ₂ is a member constituting the main body of the first layer wiring 6L, and is made of a low resistance material such as, for example, A1, A1 alloy, tungsten or tungsten alloy. Although not particularly limited, in the fifth embodiment, the thick conductor film 6L ₂ is made of, for example, tungsten.

However, the structure of the first layer wiring 6L is not limited to the structure shown in Figs. 36 and 37, and can be variously changed, and the structure described with reference to Figs. . That is, a structure in which a cap conductor film is provided on the thick conductor film 6L ₂ and the thin conductor film 6L ₁ , a cap conductor film is provided on the thick conductor film 6L ₂ , and the upper surface of the cap conductor film and the interlayer insulating film 4a are provided. ) there is a structure, a thick conductive film (6L ₂₎ constituting the structure of only the wiring structure to raise the cap film conductors on the upper surface of the case is configured for interconnection only with a thick conductive film (6L ₂₎ such as to substantially match the top surface of the. The cap conductor film is made of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN, for example.

The first layer wiring 6L of the wiring groove 5a is electrically connected to the semiconductor region 3nd of the nMOS 3n or the semiconductor region 3pd of the pMOS 3p through the connection hole 8a. In the fifth embodiment, the conductor film for wiring formation is integrally embedded in the wiring groove 5a and the connection hole 8a.

Such a method of forming the first layer wiring 6L is the same as, for example, the following method of forming a conventional buried wiring. That is, the wiring grooves 5a, 5b and the connection holes 8a are formed in the interlayer insulating film 4a by photolithography and dry etching, respectively, and then a thin conductor film 6L made of, for example, tungsten or the like. ₁ ) is deposited by the sputtering method, and a thick conductor film 6L ₂ made of, for example, tungsten or the like is formed on the thin conductor film 6L ₁ by the CVD method or the like. As a result, the conductor film can be satisfactorily embedded in the fine connection hole 8a. Thereafter, CMP processing is performed to remove conductor films other than the wiring grooves 5a, 5b and the connection holes 8a to form the first layer wiring 6L of the buried structure.

Claim is embedded in the wiring trench (5c), (5d) are formed two-layer wiring (9L) is lower and relatively thin conductor film with a side portion (9L ₁₎ and the thin conductor film (9L ₁₎ relatively thick conductive film surrounded by the It consists of (9L _2). The thin conductor film 9L ₁ is made of a material having a function of improving the adhesion between the second layer wiring 9L and the interlayer insulating film 4b or a barrier function of suppressing diffusion of members of the thick conductor film 9L ₂ . For example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN and the like.

In the case where the thin conductor film 9L ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case of being made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. Although not particularly limited, in the fifth embodiment, the thin conductor film 9L ₁ is made of TiN, for example.

The thick conductor film 9L ₂ is a member constituting the main body of the second layer wiring 9L, and is made of a low resistance material such as Cu or Cu alloy. only. The structure of the second layer wiring 9L is not limited to the structure shown in FIG. 36 and can be variously changed, and may be the structure described with reference to FIGS. 3 to 5 in the first embodiment. That is, the structure in which the cap conductor film is provided on the thick conductor film 9L ₂ and the thin conductor film 9L ₁ , the cap conductor film is provided on the thick conductor film 9L ₂ , and the top surface of the cap conductor film and the interlayer insulating film 4b are provided. ) there is a structure, a thick conductive film (9L ₂₎ constituting the structure of only the wiring structure to raise the cap film conductors on the upper surface of the case is configured for interconnection only with a thick conductive film (9L ₂₎ such as to substantially match the top surface of the. The cap conductor film is made of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN, for example.

The second layer wiring 9L of the wiring groove 5c is electrically connected to the first layer wiring 6L through the connection hole 8g. The connection hole 8g is formed such that a part of the upper surface of the first layer wiring 6L is exposed from the bottom surface of the wiring groove 5c toward the upper surface of the first layer wiring 6L. For example, the connection conductor part 18C which consists of tungsten, a tungsten alloy, A1, A1 alloy, etc. is provided.

In addition, the third layer wiring 11L formed by filling in the wiring groove 5e has the same structure as the second layer wiring 9L, and the relatively thin conductor film 11L _{1 at the} lower part and the side thereof and the thin conductor film thereof. It consists of a (11L ₁₎ relatively thick conductive film (11L ₂₎ surrounded by the. The thin conductor film 11L ₁ is made of a material having a function of improving the adhesion between the third layer wiring 11L and the interlayer insulating film 4c or a barrier function of suppressing diffusion of the members of the thick conductor film 11L ₂ . For example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN and the like.

When the thin conductor film 11L ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case of the thin conductor film 11L ₁ made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. Although not particularly limited, in the fifth embodiment, the thin conductor film 11L ₁ is made of TiN, for example.

The thick conductor film 11L ₂ is a member constituting the main body of the third layer wiring 11L, and is made of a low resistance material such as Cu or Cu alloy. However, the structure of the third layer wiring 11L is not limited to the structure shown in FIG. 36, and can be variously changed, and the structure described with reference to FIGS. 3 to 5 in the first embodiment may be used. That is, the structure in which the cap conductor film is provided on the thick conductor film 11L ₂ and the thin conductor film 11L ₁ , the cap conductor film is provided on the thick conductor film 11L ₂ , and the upper surface of the cap conductor film and the interlayer insulating film 4b are provided. ) there is a structure, a thick conductive film (11L ₂₎ constituting the structure of only the wiring structure to raise the cap film conductors on the upper surface of the case is configured for interconnection only with a thick conductive film (11L ₂₎ such as to substantially match the top surface of the. The cap conductor film is made of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN, for example.

The third layer wiring 11L of the wiring groove 5e is electrically connected to the second layer wiring 9L through the connection hole 8h. The connection hole 8h is formed such that a part of the upper surface of the second layer wiring 9L is exposed from the bottom surface of the wiring groove 5e toward the upper surface of the second layer wiring 9L. For example, a connecting conductor portion 19C made of tungsten, a tungsten alloy, an Al or Al alloy is provided. As shown in FIG. 39A described later, the second layer wiring 9L extends in the Y direction, for example, and the pitch between the second layer wiring 9L is designed to a predetermined value in the X direction. The third layer wiring 11L extends in the X direction perpendicular to the Y direction, for example, and the pitch P between the third layer wiring 11L is designed to a predetermined value in the Y direction.

Such a method of forming the second layer wiring 9L and the third layer wiring 11L is the same as the conventional method of forming the buried wiring, for example. That is, the method for forming the second layer wiring 9L will be described as an example.

First, the wiring grooves 5c, 5d and the connection holes 8g are formed in the interlayer insulating film 4b by respective photolithographic and dry etching techniques, and then a conductor film made of, for example, tungsten or the like is selected. By the method or the like, it is selectively grown in the connection hole 8g to form the connection conductor portion 18C.

Subsequently, a thin conductor film 9L ₁ made of, for example, TiN or the like is deposited by sputtering, and a thick conductor film made of, for example, Cu or Cu alloy, is formed on the thin conductor film 9L ₁ . 9L ₂ ) is formed by sputtering, CVD or plating. After this step, heat treatment may be performed to satisfactorily fill the Cu atoms in the wiring grooves 5c and 5d. As a result, the conductor film can be satisfactorily embedded in the fine connection hole 8g.

Thereafter, CMP processing is performed on the semiconductor substrate 1 to remove conductor films other than the grooves 5c and 5d for the wirings, thereby forming the second layer wiring 9L of the buried structure. The semiconductor substrate 1 may be heat-treated after the formation of the thick conductor film 9L ₂ or after the CMP treatment. At this time, the heat treatment atmosphere is an atmosphere in which any one or two or more of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere is combined. By performing heat treatment, Cu grain growth of the thick conductor film 9L ₂ is promoted to improve EM resistance, and at the same time, the surface of the thin conductor film 6L ₁ and the thick conductor film 9L ₂ during CMP treatment. The surface of the insulating film 4a can be eliminated and reduced by eliminating the damage or oxide film formed on the surface and smoothing the surface thereof. Thus, the reliability of the wiring can be improved.

However, the buried structures of the connection holes 8g and 8h are not limited to the structures shown in FIG. 36 and the like, and can be variously changed. For example, the structures shown in FIG. 38 may be used. That is, in Fig. 38, the connection holes 8g and 8h are filled with the thin conductor films 9L ₁ and 11L ₁ . The constituent material of the thin conductor film 11L _{1 in} this case is the same as the above-mentioned material, for example, and consists of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. The thick conductor films 9L ₂ and 11L ₂ are made of Cu or Cu alloy, for example.

Moreover, the connection holes 8g and 8h may be comprised with the comparatively thin conductor film of the lower part and the side part, and the comparatively thick conductor film surrounded by the thin conductor film. In this case, the thin conductor film is made of tungsten, TiN or the like, for example, and the thick conductor film is made of tungsten or the like.

On the other hand, in the upper portion (third layer wiring) of the interlayer insulating film 4c, a connection groove 5g having the same depth as that of the wiring groove 5e is formed. The connection groove 5s is formed at the same time as the wiring groove 5e.

As described above, the connecting groove 5g is formed to extend along the longitudinal direction of the wiring. As a result, the conductor film can be satisfactorily embedded in the connection groove 5g. In other words, when the conductor film is embedded in the connection groove 5g in the same wiring layer at the same time when the conductor film is embedded in the wiring groove 5e, the planar shape and dimensions of the connection groove 5g in the lower layer of the connection conductor portion 19C are When the planar shape and the dimension of the upper surface are set, the connection groove 5g is fine, and thus the conductor film cannot be sufficiently embedded. In order to avoid such an irrationality, the connection groove 5g has a shape in which its planar shape is lengthened along the longitudinal direction of the wiring, so that the conductor film can be buried satisfactorily while preventing a decrease in the mounting density of the wiring. It is. Therefore, the upper and lower wiring layers can be satisfactorily connected.

In the groove 5g for connection, as shown in FIGS. 36, 39, and 40, a connection conductor portion 21C is provided. FIG. 39A is a main part plan view showing a part of the second layer wirings 9L to 4th layer wiring 13L, FIG. 39B is a main part cross sectional view along the line BB of FIG. 39A, and FIG. 39C is a view of the CC line of FIG. 39A. The main part cross section according to. 39B is sectional drawing when the part of 2nd layer wiring 9L-4th layer wiring 13L of the right side of FIG. 36 is cut | disconnected in the direction perpendicular to the ground.

Connection purposes body (21C) is a third-layer wiring (11L) and may be of the same structure, the lower portion and a relatively thin conductive film on the side (21C ₁₎ and the thin conductor film (21C ₁₎ relatively thick conductive film surrounded by the It consists of (21C _2). That is, the connection conductor portion 21C is constituted of the same wiring W as the third layer wiring 11L. The thin conductor film 21C ₁ is made of a material having a function of improving the adhesion between the connecting conductor portion 21C and the interlayer insulating film 4c and a barrier function of suppressing diffusion of members of the thick conductor film 21C ₂ , For example, it consists of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN.

In the case where the thin conductor film 21C ₁ is made of tungsten or the like, the wiring resistance can be lowered as compared with the case of being made of TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. Although not particularly limited, in the fifth embodiment, the thin conductor film 21C ₁ is formed of the same material as the thin conductor film 11L ₁ of the third layer wiring 11L and is made of, for example, TiN. have.

The thick conductor film 21C ₂ is a member constituting the main body of the connecting conductor portion 21C, and is made of a low resistance material such as Cu or a Cu alloy. However, the structure of the connection conductor portion 21C is not limited to the structure shown in FIGS. 36 to 41, and can be variously changed, and may be the structure described with reference to FIGS. 3 to 5 in the first embodiment.

That is, a structure in which a cap conductor film is provided on the thick conductor film 21C ₂ and the thin conductor film 21C ₁ , and a cap conductor film is provided on the thick conductor film 21C ₂ , and the upper surface of the cap conductor film and the interlayer insulating film 4c are provided. ) there is a structure, a thick conductive film (21C ₂₎ constituting the structure of only the wiring structure to raise the cap film conductors on the upper surface of the case is configured for interconnection only with a thick conductive film (21C ₂₎ such as to substantially match the top surface of the. The cap conductor film is made of tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN, for example. 39 and 40, the planar shape of the connecting conductor portion 21C is configured such that the longitudinal direction (X direction) of the wiring is larger than the wiring width in the Y direction, thereby connecting the upper and lower connecting conductor portions 19C. , The positioning margin of (20C) can be increased in the X direction. As a result, even if the wiring pitch P in the Y-direction of the third layer wiring 11L is increased, the alignment margins of the upper and lower connection conductor portions 19C and 20C can be increased in the X-direction, resulting in higher density and higher integration of the wiring. can do. In addition, the wiring length in the longitudinal direction of the wiring is larger than the wiring width and less than about twice the wiring width, thereby making it possible to increase the fit margin without using a dog bone and to increase the filling gap. can do. The wiring pitch does not need to be enlarged and can be highly integrated.

As shown in Fig. 41, the planar shape of the connection conductor portion 21C may be a shape that is elongated in the longitudinal direction of the wiring and the direction crossing the direction (wiring width direction, that is, Y direction). However, also in this case, it is comprised so that the longitudinal direction (X direction) of wiring may become larger than the wiring width of a Y direction. In this case, the alignment margin of the upper and lower connection conductor portions 19C and 20C can be increased in both the longitudinal direction and the width direction of the wiring. For this reason, since the alignment precision at the time of formation of the connection hole 8f which fills in the connection conductor part 20C can be relaxed, the connection hole 8f can be formed easily. Further, even if the planar position of the connection hole 8f is slightly shifted from the design value, the connection conductor portion 20C and the connection conductor portion 21C can be satisfactorily connected.

42 and 43, the structure described in the first embodiment may be used. In other words, the upper portion of the connection conductor portion 19C protrudes into the connection conductor portion 21C. This case is formed by the same method as described in the first embodiment and the like. That is, after the connection conductor portion 19C is formed in the connection hole 8h (see Fig. 36) formed in the interlayer insulating film 4c, the connection groove 5g (see Fig. 36) is formed. The conductor film is deposited and subjected to CMP treatment to form the connection conductor portion 21C in the connection groove 5g.

The fourth layer wiring 13L has a normal wiring structure similarly to the first embodiment. The fourth layer wiring 13L is electrically connected to the third layer wiring 11L or the connecting conductor portion 21 through the connection conductor portion 20C in the connection hole 8f. The connecting conductor portion 20C is made of tungsten or tungsten alloy formed by, for example, selective CVD.

That is, in the fifth embodiment, the fourth layer wiring 13L made of A1 based material and the third layer wiring 11L made of Cu based material or the connecting conductor portion 21C are not made to directly contact each other. It is structured to electrically connect via the connection conductor part 20C. This prevents the direct contact between Al and Cu and prevents the formation of an alloy layer having a high resistivity at the contact portion.

However, the structure which prevents such an alloy layer from being formed is not limited to the structure shown in FIG. 36, It can variously change, It is good also as a structure shown to FIGS. 44-52. That is, Figure 44 is a structure consisting of the fourth wiring layer conductive film (13L) is thin (13L ₁₎ and a thick conductive film (13L ₂₎ laminated on the upper layer. The thin conductor film 13L ₁ is made of a material having a function of improving adhesion between the fourth layer wiring 13L and the interlayer insulating film 4d or a barrier function of suppressing diffusion of members of the thick conductor film 13L ₂ . For example, tungsten (W), TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN and the like. The thick conductor film 13L ₂ is made of, for example, A1 or A1 alloy.

In the structure shown in Fig. 45, a connection conductor portion 20C ₁ made of tungsten, tungsten alloy or the like formed by, for example, selective CVD is provided on the exposed surface of the third layer wiring 11L exposed by the connection hole 8f. and, also the connection hole connected purpose body (20C _2), within (8f), for example in the connection purpose body (20C ₁₎ made of such as Aℓ or Aℓ alloy are provided. The third wiring layer (13L) is electrically connected to the connection purpose body _{(20C) (20C 2, 20C} 1) a third-layer wiring (11L) via a. In addition, you may form (13L) and (20C) simultaneously. That is, in this structure, the contact portion between the fourth layer wiring 13L made of AL-based material and the connecting conductor portion 20C ₂ and the third layer wiring 11L made of Cu-based material is made of tungsten or the like. is a (20C ₁₎ provided with a structure. As a result, it is possible to prevent the alloy layer having a high specificity from being formed at the contact portion. In addition, the connection conductor portion 20C ₂ constituting most of the connection conductor portion 20C is made of a low-resistance AL-based material, so that the entire connection conductor portion is connected in comparison with the structure of FIG. 36 composed of tungsten or the like. The resistance of the application body portion 20C can be lowered.

In the structure of Figure 46. The cap is provided with a second upper conductive film on the wiring layer (11L) (11L _3). The cap conductor film 11L ₃ is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. The thick conductor film 13L ₂ is made of, for example, A1 or A1 alloy. In the connection hole 8f, a conductor film made of Al or Al alloy formed integrally with the fourth layer wiring 13L is embedded. Also in this case, a thin conductor film 11L ₃ made of tungsten or the like is provided at the contact portion of the fourth layer wiring 13L made of the A1 based material and the third layer wiring 11L made of the Cu based material. Since the alloy layer with a high specific resistance can be prevented from being formed, and the connection hole 8f is embedded with a low-resistance AL-based material, the resistance between the interlayer connections can be lowered as compared with the case of FIG.

In the structure of FIG. 47, the connection hole 8f is filled with the thin conductor film 13Ll. In this case, the constituent material of the thin conductor film 13L ₁ is the same as that described above, and is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN. The thick conductor film 13L ₂ is made of, for example, A1 or A1 alloy.

In the structure of FIG. 48, in the structure of FIG. 47, thick conductor films 13L _2a and 13L _2b are laminated sequentially from the lower layer on the thin conductor film 13L ₁ . The thick conductor film 13L _2a on the lower layer side is made of, for example, tungsten or a tungsten alloy, and is formed by, for example, CVD or sputtering. The thick conductor film 13L _2b on the upper side is made of, for example, A1 or A1 alloy, and is formed by, for example, CVD or sputtering.

In the structure of FIG. 49, W, TiN, etc. which formed 14 C of connection body parts which connect the 4th layer wiring 13L which consists of AL system, (BP), and the 3rd layer wiring 11L which consists of Cu system by sputtering method etc. A barrier metal (thin conductor film) 14C ₁ and a plug (thick conductor film) 14C ₂ such as W formed by the CVD method. This structure can reduce the contact resistance.

This structure was deposited after the barrier metal was deposited by sputtering. By depositing W in the connection hole 8f by the CVD method, the barrier metal 14C ₁ and the plug 14C ₂ can be formed only in the connection hole 8f by CMP or etch back.

The connecting conductor portion 14C may be constituted only of the plug 14C ₂ in which TiN is embedded by the CVD method.

In the structure shown in FIG. 49, in the structure shown in FIG. 49, a thin conductor film 13L ₂ having the fourth layer wirings 13L and (BP) formed of AL and a thin film formed by forming a high melting point metal or a metal compound such as TiN or W is formed. It is composed of a conductor film (13L _1). This can further improve the reliability.

In the structure of FIG. 51, in the structure of FIG. 49, barrier metal and W, such as W and TiN, are deposited by depositing the barrier metal and W in the connection hole 8f and then depositing the A-based material without plug processing. ) constitute the (13L _1), a fourth wiring layer (13L) with a thick film conductor (13L _2a) and Aℓ thick conductive film (13L made to step _2b) made of W, (BP). In this way, it is possible to simplify the plug polishing step and to improve the reliability of the laminated structure by using the laminated wiring with the Al alloy without leaving the plug processing.

In the structure shown in FIG. 51, in the structure shown in FIG. 51, the thick conductor film 13L _2a made of TiN formed by the CVD method and the thick conductor film made of A1 system are not provided without the barrier metal (thin conductor film) 13L ₁ . The fourth layer wirings 13L and BP are formed by 13L _2b . Since the TiN film 13L _2b formed by the CVD method has better adhesion to the interlayer insulating film than the W film, it is not necessary to provide the barrier metal 13L ₁ and the manufacturing process can be reduced. It leaves it without a plug process similarly to the structure of FIG. By using the laminated wiring with the A1 alloy, it is possible to simplify the plug polishing process and improve the reliability of the laminated structure.

The structure of the connection conductor portion 14C shown in FIG. 49 may be applied to the connection conductor portions 10C, 12C, 18C, 19C, and 20C. FIG. 53 shows a structure in which the structures of the connecting conductor portions 14C shown in FIG. 49 are applied to the connecting conductor portions 19C and 20C shown in FIGS. 39 and 40. The thin conductor films 19C ₁ and 20C ₁ are configured similarly to the barrier metal 14C ₁ , and the thick conductor films 19C ₂ and 20C ₂ are configured similarly to the plug 14C ₂ .

FIG. 54 is a view showing a structure in which the third layer wirings 11L and 21C shown in FIG. 53 are formed by a double machine. In this structure, after forming the connection holes 5g and 8h, the barrier metal is deposited by the sputtering method, and then Cu is thinly formed by, for example, the sputtering method, and then the connection hole (using electroplating method) is used. 5g) and (8h). Thereafter, CMP forms third layer wirings 11L and 21C composed of a thin conductor film 21C ₁ made of a barrier metal and a thick conductor film 21C ₂ made of Cu. By forming (21C) planarly longer than (8h) along at least the longitudinal direction of the wiring, the effective aspect ratio when the (5g) and (8h) are buried in Cu at the same time can be reduced, and the It becomes easy to plan.

55A and 55B are views showing a modification in which the connecting conductor portion 21C shown in FIG. 39 is shifted in the longitudinal direction (X direction). FIG. 55A is a main part plan view showing a part of the second layer wiring 9L to the fourth layer wiring 13L, and FIG. 55B is a main part cross sectional view along the CC line of FIG. 55A. Thus, even when the second layer wiring 9L is formed at the position of the pitch P ₁ of the adjacent second layer wiring 9L, the connection conductor portion 21C can be provided.

FIG. 56 shows a modification in which the connecting conductor portion 21C shown in FIG. 39 is thickened so as not to change the pitch P in the direction perpendicular to the longitudinal direction (X direction) only when the connecting hole 8f is disposed. Drawing. The connecting conductor portion 21C shown in FIG. 56 may be applied to the connecting conductor portion 21C shown in FIGS. 55A and 55B.

Example 6

Fig. 57 is a sectional view of the main part of a semiconductor integrated circuit device according to another embodiment of the present invention. Figs. 58 and 59 are sectional views of the main part in the manufacturing process of the semiconductor integrated circuit device of Fig. 57.

First, the structure of the semiconductor integrated circuit device of the sixth embodiment will be described with reference to FIG.

The first layer wiring 6L is made of a conductive material other than the Cu (copper) system such as W (tungsten), and the second layer wiring 9L and the third layer wiring 11L are Cu-based, as in the fifth embodiment. It consists of a conductive material.

6L of 1st layer wiring is used for the wiring which connects in the logic circuit comprised by MISFET, and the wiring between logic circuits, for example, and is comparatively compared with 2nd layer wiring 9L and 3rd layer wiring 11L. It consists of short wiring length.

The 2nd layer wiring 9L and the 3rd layer wiring 11L are used for the wiring which connects between logic circuits, for example, and is comprised so that one side may extend in an X direction, and the other may extend in a Y direction.

By constituting the first layer wiring 6L with the W film, the first layer wiring 6L can be formed in a fine pattern, high integration can be achieved, and electron transfer resistance can be enhanced.

In addition, since Cu-based conductive materials are not used for the first layer wiring 6L, diffusion of Cu into the semiconductor substrate 1 can be reduced and reliability can be improved.

By configuring the second layer wiring 9L and the third layer wiring 11L with a Cu-based conductive material, the specific resistance of the wiring is reduced and high-speed operation is possible.

The connecting conductor portions 7C, 18C, 19C, 20C, and 21C are made of W, formed by sputtering, similarly to the connecting conductor portion 14C shown in FIG. 49 (thin). Conductor film) 14C ₁ and a plug (thick conductor film) 14C ₂ composed of W.

The fourth layer wiring 13L and the fifth layer wiring 102 are made of, for example, an aluminum-based conductive material.

The fourth layer wiring 13L has a laminated structure in which a thick conductor film 13L ₂ made of Al or Al alloy is disposed between barrier metals (thin conductor films 13L ₁ and 13L ₃ ) such as W and TiN. do.

By electrically connecting the fourth layer wiring 13L made of the Al-based conductive material and the third layer wiring 11L made of the Cu-based conductive material through the connection conductor portion 20C made of W, It is possible to prevent the formation of an alloy layer having a high resistivity at the contact portion by Al and Cu. The fourth layer wiring 13L may be configured by the wiring structure shown in FIGS. 44 to 52.

In addition, although the fifth layer wiring 102 is electrically connected to the fourth layer wiring 13L without passing through the connecting conductor portion, the fifth layer wiring 102 is not limited to this, and is arranged between the fourth layer wiring 13L and the third layer wiring 11L. The fifth layer wiring 102 and the fourth layer wiring 13L may be electrically connected to each other via the connection conductor portion having the same structure as the connection conductor portion 20C.

In addition, the fifth layer wiring 102 may be formed in a stacked structure similarly to the fourth layer wiring 13L.

An insulating film 104 made of, for example, a silicon oxide film is formed on the fifth layer wiring 102, and a lower electrode 106 is formed in an opening formed in the insulating film 104. The fifth layer wiring 102 is electrically connected to the bump electrode 108 made of solder bumps via the lower electrode 106, and the lower electrode 106 is made of, for example, a barrier metal.

A method of forming the first layer wiring 6L and the connecting conductor portion 7C will be briefly described below with reference to FIGS. 58 and 59.

As shown in Fig. 8, after the connection holes 8a are formed in the interlayer insulating film 4a, as shown in Fig. 58, a thin conductor film 7C ₁ made of W is deposited by sputtering, followed by the CVD method. The thick conductor film 7C ₂ made of W is deposited so as to fill the connection hole 8a.

Next, as shown in Figure 59, a film is deposited for example by polishing by CMP thick conductor made of a thin conductive film (7C ₁₎ and W made of W in the connection hole (8a) film (7C ₂₎ Landfill.

Next, the W film is deposited by, for example, PVD, and then patterned by etching to form the first layer wiring 6L. In addition, although (6L) was formed by the W film | membrane by PVD method here, various changes, such as a laminated structure in which the W film | membrane by CVD method was formed on the W film | membrane by PVD method, are possible.

Next, after the silicon oxide film is deposited by, for example, CVD, the silicon oxide film is polished by the CMP method to form an interlayer insulating film 4b having a flattened surface.

Subsequent processes are formed similarly to Examples 1-5 mentioned above.

The semiconductor integrated circuit device of the sixth embodiment uses the bump electrode 108, but as shown in FIG. 60, the bonding wire 110 is electrically connected to a bonding pad composed of the fifth layer wiring 102. As shown in FIG. You may also

The semiconductor integrated circuit device according to the sixth embodiment is composed of five wiring layers, but is composed of seven wiring layers, and the second to fifth layer wirings are made of a Cu-based conductive material, and the sixth layer. The wiring to the seventh layer wiring may be made of an Al-based conductive material. In this case, the second layer wiring and the fourth layer wiring are configured to extend in the same direction, and the third layer wiring and the fifth layer wiring are configured to extend in the same direction and used as wiring for connecting the logic circuits. Further, in the sixth embodiment, the third-layer wiring layer located at the portion where the connection conductor portion 19C and the connection conductor portion 20C are connected is at least planar than the connection conductor portions 19C and 20C along the longitudinal direction of the wiring. Although the connection conductor part 21C formed long was provided, the structure with respect to the connection conductor part 21C may be provided in 2nd, 3rd, 4th, and 5th layer.

61 shows the planar layout of the semiconductor integrated circuit device described in Embodiments 1 to 6. FIG.

The gate array 200 is repeatedly arranged, and integrated circuit elements such as MISFETs, bipolars, resistors, and the like are arranged in each gate array 200.

By changing the wiring patterns of the first to fifth layer wirings, various logic circuits are formed, and a semiconductor integrated circuit device having predetermined logic is formed.

FIG. 62 shows a semiconductor integrated circuit device having a gate array 200 and a RAM 400 as a memory.

63, the units 400, 500, 600, and 700 having various functions may be freely arranged in accordance with the performance of the LSI.

As described above, according to the fifth and sixth embodiments, the following effects can be obtained in addition to the effects of [8] to [10] obtained in the first embodiment.

[One]. Filling the conductor film in the fine connection holes 8a to 8f by using the CVD method or the like, and then filling the conductor film into the wiring grooves 5a to 5f having a larger plane dimension than the connection holes 8a to 8f. By forming the first layer wiring 6L, the second layer wiring 9L, and the third layer wiring 11L of the buried structure, the wiring grooves 5a to 5f and finer connection holes ( The conductor film can be satisfactorily embedded in both 8a) to (8f). In addition, the wiring grooves 5a to 5f are simultaneously filled in the fine connection holes 8a to 8f and the wiring grooves 5a to 5f positioned thereon by using the CVD method or the plating method. By increasing the planar dimension than the connection holes 8a to 8f, the conductor film can be well buried.

[2]. By the above [1], the reliability of the connection between the wiring layers can be improved. Therefore, the manufacturing efficiency and reliability of the semiconductor integrated circuit device can be improved.

[3]. [1] enables the miniaturization of the buried wiring to be promoted. Therefore, it is possible to promote miniaturization or high integration of the semiconductor integrated circuit device.

[4]. [1], the conductor film can be well embedded in the wiring grooves 5a to 5f and the connection holes 8a to 8f without employing a difficult technique.

[5]. According to the above [1], even when Cu, Cu alloy, or the like is used as the embedding wiring material, the state of the embedding can be improved.

[6]. The first layer wiring 6L, which is in direct contact with the semiconductor substrate 1, is made of a tungsten-based conductor material, so that the semiconductor substrate of Cu atoms can be maintained while maintaining the state of embedding of the conductor film in the connection hole 8a. It is possible to avoid device defects caused by diffusion phenomenon toward side 1). In addition, by configuring the first layer wiring 6L with a tungsten-based conductor material, the wiring resistance can be reduced and the EM resistance can be improved.

As mentioned above, although it demonstrated concretely according to the Example of this invention made by this inventor, this invention is not limited to the said Example, Of course, various changes are possible in the range which does not deviate from the summary.

For example, in a semiconductor substrate, a silicide layer such as tungsten silicide or titanium silicide may be provided at the contact portion with the connecting conductor portion.

The wiring layer is not limited to four to seven layers but can be variously changed, and may be three or four or more layers.

The effect obtained by the typical thing of the invention disclosed in this application is briefly described as follows.

[One]. According to the manufacturing method of the semiconductor integrated circuit device of the present invention, the connection hole is sufficiently filled with a conductor film, and then a wiring groove is formed and embedded in the conductor film, so that both the groove for the wiring and the finer connection hole than that are formed. The conductor film can be buried satisfactorily.

[2]. According to the manufacturing method of the semiconductor integrated circuit device of the present invention, in the case of having the wiring grooves having different dimensions in the same wiring layer, the method of embedding the conductor film by selecting a method which is easy to embed into a fine wiring groove or the like for the wiring grooves larger than that. As a result, the conductor film can be satisfactorily embedded in both wiring grooves.

[3]. [1] or [2] can improve the reliability of the connection between the wiring layers. Therefore, the manufacturing efficiency and reliability of the semiconductor integrated circuit device can be improved.

[4]. [1] or [2] enables the miniaturization of the buried wiring to be promoted. Therefore, it is possible to promote miniaturization or high integration of the semiconductor integrated circuit device.

[5]. [1] or [2] makes it possible to satisfactorily embed the conductor film in the wiring groove and the connection hole without employing any of the various techniques. therefore. The cost reduction of the semiconductor integrated circuit device having the buried wiring can be promoted.

[6]. According to the above [1] or [2], even when Cu or a Cu alloy or the like is used as a buried wiring material, the buried state can be improved.

[7]. According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a Cu-based conductor material in a region other than a wiring groove is formed by planarizing a Cu-based conductor material formed by a sputtering method or the like on an insulating film including a wiring groove. The heat treatment is performed after the removal and formation of the buried wiring, thereby promoting Cu particle growth to improve EM resistance, and at the same time, eliminating damage and oxide film, etc., generated on the surface of the Cu-based conductor film during planarization. It is possible to smoothen the surface of the insulating film exposed to CMP and to reduce and eliminate the contamination. Thus, the reliability of the buried wiring made of the Cu-based conductor material can be improved.

[8]. According to the semiconductor integrated circuit device of the present invention, a semiconductor integrated circuit device having a buried wiring in an upper wiring layer of a semiconductor substrate, wherein the wiring material of the portion where the buried wiring and the semiconductor substrate are in contact with each other is tungsten, tungsten alloy, aluminum or aluminum alloy. The upper layer is formed of copper or copper alloy in the wiring layer, thereby preventing the diffusion of Cu atoms to the semiconductor substrate side while maintaining the state of embedding of the conductor film in the connection hole. It is possible to avoid device defects caused and to reduce the overall wiring resistance of the semiconductor integrated circuit device, thereby improving the signal propagation speed.

[9]. According to the semiconductor integrated circuit device of the present invention, a semiconductor integrated circuit device having buried wiring in an upper wiring layer of a semiconductor substrate, wherein the wiring material of the uppermost wiring layer in the wiring layer is made of aluminum or aluminum alloy, By constituting the buried wiring in copper or copper alloy, conventional assembly techniques such as wire bonding technology and bump electrode formation technology can be followed. Therefore, the semiconductor integrated circuit device having the buried wiring made of the same conductor material can be easily introduced into the assembly process.

[10]. According to the semiconductor integrated circuit device of the present invention, a semiconductor integrated circuit device having a buried wiring in a wiring layer on an upper layer of a semiconductor substrate, and in the case of connecting wiring made of aluminum or aluminum alloy and wiring made of copper or copper alloy, By interposing a plug as a barrier conductor film, it is possible to prevent the formation of an alloy layer having a high specific resistance at the contact portion when the aluminum-based conductor material is brought into direct contact with the copper-based conductor material, thereby reducing the connection resistance between the wiring layers. You can do it.

[11]. [8] to [10] enables the embedded wiring made of the same conductor material to be assembled into the entire structure of the semiconductor integrated circuit device without causing irrationality.

[12]. In addition, according to the semiconductor integrated circuit device of the present invention, the relay connecting conductor portion is formed so that at least the length in the wiring extension direction of the predetermined buried wiring is longer than the length of the wiring extension direction of the connection hole. As a result, the connecting groove for forming the connecting conductor portion for relay can be made relatively large, so that the conductor film can be satisfactorily embedded in the connecting groove. Therefore, the reliability of the electrical connection between the upper and lower wiring layers can be improved, and the manufacturing efficiency and reliability of the semiconductor integrated circuit device can be improved.

1 is a cross-sectional view of an essential part of a semiconductor integrated circuit device according to an embodiment of the present invention;

2 is a cross-sectional view of an essential part showing a first layer wiring of a semiconductor integrated circuit device;

3 is a cross-sectional view showing a modification of the wiring structure of FIG.

4 is a cross-sectional view showing a modification of the wiring structure of FIG.

5 is a cross-sectional view showing a modification of the wiring structure of FIG.

6 is a cross-sectional view of an essential part showing a second layer wiring of the semiconductor integrated circuit device of FIG. 1;

FIG. 7 is a cross-sectional view of principal parts of a semiconductor integrated circuit device, illustrating a variation of interconnection between wiring layers of the semiconductor integrated circuit device of FIG. 1; FIG.

FIG. 8 is a cross-sectional view of principal parts in a manufacturing process of the semiconductor integrated circuit device of FIG. 1; FIG.

9 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step;

10 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step;

FIG. 11 is a cross sectional view of principal parts of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step; FIG.

12 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step;

13 is a partially cutaway perspective view of a main part in the manufacturing process of the semiconductor integrated circuit device of FIG. 1;

14 is a partially cutaway perspective view of a main part in the manufacturing process of the semiconductor integrated circuit device of FIG. 1;

15 is a partially cutaway perspective view of a main part in the manufacturing process of the semiconductor integrated circuit device of FIG. 1;

16 is a partially cutaway perspective view of a main part in the manufacturing process of the semiconductor integrated circuit device of FIG. 1;

FIG. 17 is a partially cutaway perspective view of a main part in the manufacturing process of the semiconductor integrated vapor path device of FIG. 1; FIG.

18 is a partially cutaway perspective view of a main part in the manufacturing process of the semiconductor integrated circuit device of FIG. 1;

Fig. 19 is a sectional view of the essential parts of the semiconductor integrated circuit device, which is another embodiment of the present invention, in the manufacturing process;

20 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 19;

21 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 19;

22 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 19;

FIG. 23 is a cross sectional view of principal parts of the semiconductor integrated circuit device during a manufacturing step following FIG. 19; FIG.

24 is a cross-sectional view of an essential part of a semiconductor integrated circuit device according to another embodiment of the present invention;

Fig. 25 is a cross sectional view of principal parts of a semiconductor integrated circuit device in accordance with another embodiment of the present invention during a manufacturing step thereof;

26 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 25;

27 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 25;

28 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 25;

29 is a cross sectional view of principal parts of a semiconductor integrated circuit device in accordance with another embodiment of the present invention during a manufacturing step thereof;

30 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 29;

31 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 29;

32 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 29;

33 is a cross-sectional view of an essential part of a semiconductor integrated circuit device according to another embodiment of the present invention;

34 is a cross-sectional view of an essential part of a semiconductor integrated circuit device according to another embodiment of the present invention;

35 is a cross-sectional view of an essential part of a semiconductor integrated circuit device according to another embodiment of the present invention;

36 is a cross-sectional view of an essential part of a semiconductor integrated circuit device according to another embodiment of the present invention;

37 is an enlarged cross-sectional view of a main part of the semiconductor integrated circuit device of FIG. 36;

38 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device shown in FIG. 37;

39A is an essential part plan view of the semiconductor integrated circuit shown in FIG. 37, and FIGS. 39B and 39C are enlarged cross-sectional views of an essential part of the semiconductor integrated circuit device shown in FIG. 39A;

40 is an explanatory diagram schematically showing a main part of the semiconductor integrated circuit device of FIG. 39;

FIG. 41 is an explanatory diagram schematically showing a modification of FIG. 40; FIG.

FIG. 42 is an explanatory diagram schematically showing a modification of FIG. 40; FIG.

43 is an explanatory diagram schematically showing a modification of FIG. 40;

44 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;

45 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;

46 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;

47 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;

48 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;

49 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;

50 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;

51 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;

52 is an enlarged cross-sectional view of a main part showing a modification of the main part of the semiconductor integrated circuit device of FIG. 36;

53 is a sectional view showing a modification to the semiconductor integrated circuit device of FIG. 39C;

54 is a sectional view showing a modification to the semiconductor integrated circuit device of FIG. 39C;

55A is a plan view showing a modification of the semiconductor integrated circuit device of FIG. 39A;

55B is an enlarged cross-sectional view of a main part of the semiconductor integrated circuit device shown in FIG. 55A;

56 is a plan view showing a modification of the semiconductor integrated circuit device of FIG. 39A;

57 is a sectional view of the main portion of a semiconductor integrated circuit device according to another embodiment of the present invention;

58 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 57 during a manufacturing step;

59 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 57 during a manufacturing step;

60 is a cross-sectional view of a main part showing a modification of the semiconductor integrated circuit device of FIG. 57;

61 is a plan layout view of a semiconductor integrated circuit device according to an embodiment of the present invention;

62 is a plan layout diagram showing a modification of the semiconductor integrated circuit device of FIG. 61;

FIG. 63 is a plan layout showing a modification of the semiconductor integrated circuit device of FIG. 61;

Claims (31)

A semiconductor integrated circuit device having a wiring layer on top of a semiconductor substrate, The wiring material of the uppermost wiring layer in the wiring layer is made of aluminum or aluminum alloy, and the buried wiring in at least one wiring layer of the lower wiring layer is made of copper or copper alloy, And the wiring for connecting the best wiring layer and the buried wiring comprises a TiN or Ti film having a barrier function and tungsten formed in the TiN or Ti film. A semiconductor integrated circuit device having a wiring layer on top of a semiconductor substrate, The wiring material of the part where the wiring and the semiconductor substrate contact is made of tungsten and tungsten alloy, The wiring material of the best wiring layer is composed of aluminum or aluminum alloy, The wiring in at least one wiring layer among the wiring layers between the uppermost wiring layer and the lowermost wiring layer is composed of copper or copper alloy, The wiring for connecting the best wiring layer and the wiring of copper or copper alloy and the wiring of the portion where the wiring is in contact with the semiconductor substrate are semiconductor integrated circuits composed of a TiN or Ti film having a barrier function and tungsten formed in the TiN or Ti film. Device. A semiconductor integrated circuit device having buried wiring in a wiring layer on an upper layer of a semiconductor substrate, From the first wiring to the wiring layer of the predetermined buried wiring in the case where the first wiring above the wiring layer of the predetermined buried wiring in the wiring layer and the second wiring below the wiring layer of the predetermined buried wiring are electrically connected. A groove for connection of the wiring layer of the predetermined buried wiring, the first connecting conductor portion provided in the connecting hole extending and the second connecting conductor portion provided in the connecting hole extending from the second wiring to the wiring layer of the predetermined buried wiring. It is provided with the structure electrically connected via the 3rd connection conductor part for relay provided in the inside, And the third connecting conductor portion is formed so that at least the length in the wiring extension direction of the predetermined buried wiring is longer than the length of the buried wiring extension direction of the first and second connection conductor portions. A semiconductor integrated circuit device having a wiring layer on top of a semiconductor substrate, A first wiring layer made of a copper material; A second wiring layer formed above the first wiring layer and made of an aluminum material; A third wiring layer formed below the first wiring layer and composed of aluminum, aluminum alloy, tungsten or tungsten alloy, The first wiring layer and the second wiring layer are electrically connected through a barrier conductor film formed of a tungsten-based conductive material and embedded in a connection hole formed in the interlayer insulating film between the first wiring layer and the second wiring layer, The second wiring layer is electrically connected to a bonding wire or a bump electrode, And the third wiring layer is connected to the semiconductor substrate. A semiconductor integrated circuit device having a wiring layer on top of a semiconductor substrate, A first wiring layer having a first wiring configured to extend in a first direction; A second wiring layer having a second wiring formed above the first wiring layer and extending in a second direction perpendicular to the first direction; It has a 3rd wiring layer formed in the upper layer rather than the said 2nd wiring layer, and has a 3rd wiring comprised extending in the said 1st direction, The second wiring layer electrically connects the first wiring and the second wiring. Including a conductor part for connection, A length in the second direction of the connecting conductor portion is greater than a length in the first direction of the connecting conductor portion and is less than twice the length of the first direction of the connecting conductor portion. [a] forming a groove in the insulating film on the upper layer of the semiconductor substrate; [b] forming a conductor film made of copper or copper alloy on the insulating film by sputtering or plating so that the groove is filled; [c] embedding the conductor film in the groove by performing a planarization treatment on the conductor film made of copper or copper alloy to remove the conductor film made of copper or copper alloy other than the groove; [d] a step of performing heat treatment after the step of planarizing the conductor film made of copper or copper alloy; [e] A method for manufacturing a semiconductor integrated circuit device having a step of performing a heat treatment after a step of forming a conductor film made of copper or copper alloy and before a planarization step.  The method of claim 6, And the heat treatment is performed in an atmosphere of reducing gas, inert gas, or oxidizing gas, or a combination of two or more thereof. The method of claim 6, And the heat treatment after the planarization treatment step is a heat treatment to promote grain growth of the conductor film. A first insulating film formed on the semiconductor substrate; A first wiring functioning as a wire wire and having a first conductor film and a second conductor film embedded in a groove of said first insulating film and made of a copper-based conductive material; A second insulating film formed on the first wiring and having a function of suppressing diffusion of copper; A third insulating film formed on the second insulating film; A second wiring functioning as a wire and made of aluminum or an aluminum alloy and formed on the third insulating film; A connection conductor buried in the second insulating film and the third insulating film, The second conductor film is interposed between the first conductor film and the first insulating film, and has a function of suppressing diffusion of copper; The connection conductor has a function of contacting the first wiring and the second wiring and suppressing diffusion of copper. And the second wiring has an electrode extension portion electrically connected to a wire line and a pad portion, and the electrode extension portion has a width larger than that of the wire line. The method of claim 9, And the electrode extension portion is electrically connected to the bonding wire via the opening formed in the passivation film. The method of claim 9, And the electrode extension portion is electrically connected to the bump electrode via the opening formed in the passivation film. The method of claim 9, And the electrode extension part comprises a pad part electrically connected to a bonding wire or a bump electrode. A first insulating film formed on the semiconductor substrate; A first wiring functioning as a wire wire and made of a copper conductive material, and embedded in a groove of the first insulating film; A second insulating film formed on the first wiring; A second wiring functioning as a wire wire and composed of aluminum or an aluminum alloy, and formed on the second insulating film; A connection conductor embedded in the second insulating film, the connection conductor electrically connecting the first wiring and the second wiring; The first wiring is covered with a barrier layer to suppress diffusion of copper, And the second wiring has an electrode extension portion electrically connected to a wire line and a pad portion, and the electrode extension portion has a width larger than that of the wire line. The method of claim 13, And the electrode extension portion is electrically connected to the bonding wire via an opening formed in the passivation film, including the pad portion. The method of claim 13, And the electrode extension portion includes the pad portion and is electrically connected to the bump electrode via an opening formed in a passivation film. The method of claim 13, And the electrode extension part includes the pad part electrically connected to a bonding wire or a bump electrode. A first interlayer insulating film formed on a semiconductor substrate and having a first groove: A first wiring functioning as a wire wire and formed in said first groove and having a first conductor film and a first barrier film; A second barrier film formed on the first wiring and having a function of suppressing diffusion of copper; A second interlayer insulating film formed on the second barrier film and the first interlayer insulating film; A second wiring functioning as a wire wire and formed on said second interlayer insulating film and composed of aluminum or an aluminum alloy; A surface passivation film formed on said second wiring; The first conductor film is made of a copper conductive material, The first barrier film is interposed between the first conductor film and the first interlayer insulating film, and has a function of suppressing diffusion of copper; The second wiring has a wire line and a bonding pad portion, and the bonding pad portion has a width larger than the width of the wire line, A connecting conductor is embedded in the second interlayer insulating film and electrically connects the first wiring and the second wiring. The method of claim 17, And the electrode extension portion includes the pad portion and is electrically connected to a bonding wire through an opening formed in the passivation film. The method of claim 17, And the electrode extension portion includes the pad portion and is electrically connected to the bump electrode through an opening formed in the passivation film. The method of claim 17, And the electrode extension part includes the pad part electrically connected to a bonding wire or a bump electrode. A first insulating film formed on the semiconductor substrate and having a first groove; A first wiring functioning as a wire wire and formed in said first groove and having a first conductor film and a first barrier film; A second barrier film formed on the first wiring and having a function of suppressing diffusion of copper; A second insulating film formed on the second barrier film and the first insulating film; A second wiring which functions as a wire and is formed on the second insulating film and composed of aluminum or an aluminum alloy, The first conductor film is made of a copper conductive material, The first barrier film is interposed between the first conductor film and the first insulating film and has a function of suppressing diffusion of copper; The second wiring has a pad portion for electrically connecting a bonding wire or a bump electrode, and is electrically connected to the first wiring via a barrier metal. And the pad portion has a width greater than a wire line of the second wiring. The method of claim 21, And the electrode extension portion is electrically connected to the bonding wire via the opening formed in the passivation film. The method of claim 21, And the electrode extension portion is electrically connected to the bump electrode via the opening formed in the passivation film. The method of claim 21, And the electrode extension part includes the pad part electrically connected to a bonding wire or a bump electrode. The method of claim 21, A third insulating film formed on the second wiring; A third wiring which functions as said pad portion and is formed on said third insulating film and composed of aluminum or an aluminum alloy, The pad part is electrically connected to a bonding wire or a bump electrode, And the third wiring is electrically connected to the electrode extension portion via an opening formed in the third insulating film. The method of claim 9, A fourth insulating film formed on said second wiring; A third wiring functioning as said pad portion and formed on said fourth insulating film and composed of aluminum or an aluminum alloy, The pad part is electrically connected to a bonding wire or a bump electrode, And the third wiring is electrically connected to the electrode extension portion via an opening formed in the fourth insulating film. The method of claim 13, A fourth insulating film formed on said second wiring; A third wiring functioning as said pad portion and formed on said fourth insulating film and composed of aluminum or an aluminum alloy, The pad part is electrically connected to a bonding wire or a bump electrode, And the third wiring is electrically connected to the electrode extension portion via an opening formed in the fourth insulating film. Forming a first wiring made of a copper-based conductive material in a groove of the first insulating film formed as a wire wire and formed on the semiconductor substrate; Forming a second insulating film having a hole on the first wiring; A switch for forming a connecting conductor in the hole for electrically connecting the first wiring. The tab and; Depositing a conductor film on the second insulating film, and patterning the conductor film to form a second wiring functioning as a wire and composed of aluminum or an aluminum alloy, The first wiring is covered with a barrier layer that suppresses diffusion of copper, The second wiring is electrically connected to the connection conductor, And the second wiring has an electrode extension portion electrically connected to a wire line and a pad portion, and the electrode extension portion has a width larger than that of the wire line. The method of claim 28, And the electrode extension portion includes the pad portion and is electrically connected to a bonding wire through an opening formed in a passivation film. The method of claim 28, And the electrode extension portion includes the pad portion and is electrically connected to the bump electrode through an opening formed in a passivation film. The method of claim 28, The electrode extending portion is the pad electrically connected to a bonding wire or a bump electrode. A method for manufacturing a semiconductor integrated circuit device comprising a chip portion.