JPH09213698A - Formation of wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the generation of such accidents as adhesive grains are left, the adhesion of metal wirings is impaired and the seams of the metal wirings for filling the interiors of wiring patterned grooves are opened by a method wherein a metal film is polished using an abrasive containing CuO grains as the adhesive grains to form the metal wirings in the wiring patterned grooves. SOLUTION: An etching of an interlayer insulating film 10 is performed to form wiring patterned grooves 10A by applying a resist process, which is executed applying a lithography technique, and an RIE method, which is executed using the mixed gas of CF4 +CHF3 as etching gas. A Cu film is deposited on the entire surface by applying a sputtering method. A heat treatment is performed and a reflow of the formed Cu film is performed to fill the grooves 10A. The re-flowed Cu film is polished until the film 10 is exposed by applying a polishing method using an adhesive containing CuO grains as adhesive grains and Cu wirings are respectively formed in the grooves 10A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a wiring forming method for forming a buried wiring in a semiconductor device by polishing.

At present, a groove is formed by etching a portion of the insulating film where a wiring is to be formed, and a metal is embedded in the groove to form a wiring, but there are still many problems. It has not yet been possible to obtain highly reliable wiring.

Therefore, while these problems must be solved, the present invention provides one means for improving the reliability of this type of wiring.

[0004]

2. Description of the Related Art In recent years, in semiconductor devices that are becoming finer, the ratio of the delay time due to wiring to the signal processing time is larger than the operation time of the semiconductor device. Therefore, in the future, in order to improve the signal processing speed in the semiconductor device, it is important to reduce the capacitance and the wiring resistance due to the interlayer insulating film of the wiring.

As a means for reducing the wiring resistance, copper (C
Although u) is being studied as a wiring material, the problem is that there is no suitable etching gas that enables Cu to be etched into a fine wiring pattern. Such a wiring forming method has been studied as a powerful technique. It should be noted that, for easy understanding of the explanation, FIG.
It is recommended to refer to FIG.

(1) A first interlayer insulating film is formed on a substrate in which a required element region is formed, and then the first interlayer insulating film is etched to form an element region formed on the substrate. An electrode contact hole that exposes a part of is formed.

(2) A TiN film and a first W film are formed on the entire surface including the inside of the electrode contact hole, and then the first W film and the TiN film are polished to form the electrode contact. Remove the others, leaving the ones in the hole. still,
The TiN film functions as a glue layer for compensating the adhesion between the W film and the interlayer insulating film (oxide film),
It is also used as the base of a Cu film.

(3) A second interlayer insulating film is formed on the entire surface including the top surface of the first W film contacting the element region, and then the second interlayer insulating film is etched to form a first interlayer insulating film. One W
A wiring pattern groove is formed which is exposed through the top surface of the film and extends in the lateral direction (direction along the substrate surface).

(4) After the first Cu film is formed on the entire surface, reflow by heat treatment is performed to fill Cu in the wiring pattern groove, and then the first Cu film is covered with Al ₂ O ₃ . The first Cu wiring is formed by polishing with an abrasive used as abrasive grains and removing the remaining ones in the wiring pattern groove while the others are removed. Subsequent cleaning is applied to the scrubber and HF
Immerse in + H ₂ O (1: 199) for 20 seconds.

(5) After heat treatment in a hydrogen atmosphere, a SiN film is formed on the entire surface. The SiN film is changed from the Cu film to the Cu film.
Acts to prevent the spread of.

(6) A third interlayer insulating film is formed on the entire surface of the SiN film which acts as a diffusion preventing film, and then the third interlayer insulating film is etched to form a vertical direction (direction intersecting with the substrate surface). A through hole having a pattern of a plug (a conductor connecting wiring layers) formed in the above is formed. A part of the first Cu wiring is exposed in this through hole.

(7) TiN is formed on the entire surface including the inside of the through hole.
A film and a second W film, and then a second W film and Ti
Polishing of the N film is performed, and the plugs are formed by removing the remaining ones in the through holes.

(8) A fourth interlayer insulating film is formed on the entire surface including the top surface of the first plug which is in contact with the first Cu wiring, and thereafter, the Cu wiring is formed and the interlayer insulating film is formed. The formation and the formation of the plug are repeated to form the multilayer wiring.

[0014]

In the above-mentioned conventional technique, when the Cu film is polished to form the Cu wiring, the abrasive grains are Al ₂ O ₃ and the oxidant is H ₂ O. _A mixture of ₂ was used, and potassium phthalate was added to it in order to reduce the polishing rate of the oxide film which is an insulating film.

Experiments have revealed that when the above-mentioned abrasive is used, various problems occur and a highly reliable wiring cannot be formed.

That is, after polishing the Cu film, even if the cleaning as described in the above-mentioned conventional technique is performed, Al ₂ O ₃ cannot be sufficiently removed, and H ₂ O ₂ is not removed. The TiN that is the glue layer is etched, and the potassium in the potassium phthalate added to reduce the polishing rate of the oxide film is between the TiN film and the oxide film, or the Cu film. It penetrates between the TiN film and the TiN film, which lowers the reliability of the device.

When the CVD method is applied to deposit Cu or W, for example, in the region where the groove exists, the deposition in the groove progresses from the edge of the groove toward the center, so that the deposited film is formed near the center. It is known that seams are created by abutting, and seams may also be created using sputter reflow.

Such a seam portion is easily etched by the oxidizing agent, and particularly when the oxidizing agent is a liquid, the etching proceeds rapidly and the seam expands, that is, opens.

As described above, when the seam is opened due to etching, impurities and abrasive grains penetrate into the seam, which makes cleaning difficult, which in turn lowers the reliability of the semiconductor device. I will end up.

According to the present invention, when the wiring is formed by embedding a metal in the wiring pattern groove, the abrasive grains are left and the adhesion of the wiring is improved by properly selecting the material of the polishing agent and the material of the cleaning agent. Do not damage or open the seam of the wiring that fills the groove.

[0021]

In the present invention, Cu, W,
Al or an alloy of Al, such as Al-SiTi or A
As a polishing agent such as l-Cu-Si, one containing abrasive grains made of CuO is used.
Basically, an acid or alkali having a function of dissolving uO, specifically, HCl, HNO ₃ , H ₂ SO ₄ , HF or the like is used, or H ₂ O ₂ is mixed with these solutions. Has become. Needless to say, the action becomes stronger when H ₂ O ₂ is added.

When the present invention is applied to deposited Cu, for example, the following reaction is considered to proceed.

During polishing Cu (deposition) + CuO → Cu _x O _y + Cu ₂ O

At the time of cleaning When using HCl: CuO + 2HCl → CuCl ₂ +
When H ₂ O HNO ₃ is used: CuO + 2HNO ₃ → Cu (N
When O ₃ ) ₂ + H ₂ OH ₂ SO ₄ is used: CuO + H ₂ SO ₄ → Cu
When (SO ₄ ) + H ₂ O HF is used: CuO + 2HF → CuF ₂ + H ₂ O

CuCl ₂ , Cu (NO ₃ ) ₂ and Cu
F ₂ etc. are all easily soluble in water.

From the above, in the wiring forming method according to the present invention, (1) Cu is formed on the insulating film (for example, the interlayer insulating film 10) in which the wiring pattern groove (for example, the wiring pattern groove 10A) is formed. A step of forming an oxidizable metal film (eg, Cu film) of W, Al, etc., and polishing the metal film with an abrasive having CuO as abrasive grains to form a metal wiring (eg, Cu film) in the wiring pattern groove. Or a step of forming a wiring 11), or

(2) In the above (1), the polished wafer is treated with an acid or an alkali (for example, HCl + H).
₂ O ₂ , HNO ₃ + H ₂ O ₂ , H ₂ SO ₄ + H ₂ O ₂ ,
HF + H ₂ O ₂ etc.) is included.

In the present invention, as described above, when the material of the polishing agent and the material of the cleaning agent are properly selected, when the metal is embedded in the wiring pattern groove to form the wiring,
Abrasive particles in the polishing agent may remain, the adhesion between the wiring and the base may be impaired, or the wiring seams that fill the groove may open, causing impurities and abrasive particles to enter, making cleaning difficult. Therefore, the semiconductor device having high reliability can be manufactured.

[0029]

1 to 7 are side sectional views showing essential parts of a semiconductor device in a process step for explaining an embodiment of the present invention. Refer to these drawings hereinafter. I will explain while doing it.

See FIG. 1A. 1- (1) Selective oxidation (1) using a Si ₃ N ₄ film or the like as an oxidation resistant mask.
ocal oxidation of silico
n: depending on the applying the LOCOS) method, an element isolation insulating film 2 of SiO ₂ is in the field region in the Si semiconductor substrate 1.

1- (2) After removing the Si ₃ N ₄ film used as the oxidation resistant mask to expose the active region of the Si semiconductor substrate 1, the thermal oxidation method and the chemical vapor deposition (chemical vapor deposition) are performed.
Emission (CVD) method is applied to the gate insulating film 3 made of SiO ₂ and the polycrystalline S
An i film is formed.

1- (3) Resist process in lithography technology, and
Reactive ion etching
By applying the etching (RIE) method,
The polycrystalline Si film and the gate insulating film 3 formed in step 1- (2) are etched to form the gate electrode 4 and the gate insulating film 3 is patterned into the same shape as the gate electrode 4.

1- (4) By applying the ion implantation method, n ^{− of} the LDD structure is obtained.
The source region 5 and the n ⁻ drain region 6 are formed.

1- (5) An insulating film made of SiO ₂ is formed by applying the CVD method, and then anisotropy of the insulating film made of SiO ₂ is obtained by applying the RIE method. Etching is performed to leave only those on the side surfaces of the gate electrode 4 and the gate insulating film 3 as the side walls 7, and remove the others.

1- (6) By applying the ion implantation method, n ^{+ of} the LDD structure is obtained ^.
A source region 5A and an n ⁺ drain region 6A are formed.

See FIG. 1B. 1- (7) By applying the CVD method, a thickness of, for example, 8 is formed on the entire surface.
An interlayer insulating film 8 made of SiO _{2 of} 00 [nm] is formed.

See FIG. 2A. 2- (1) Resist process in lithography technology, and
Etching gas is CF ₄ + CHF ₃ mixed gas R
By applying the IE method, the interlayer insulating film 8 is etched to form the electrode contact hole 8A.

See FIG. 2B. 2- (2) By applying the sputtering method, a TiN film having a thickness of 20 nm to 50 nm and a thickness of 300 nm to 400, for example. A W film of [nm] is formed.
For simplicity, the TiN film and the W film are collectively shown in the figure. Further, if the thickness of the W film is set to the above range, the electrode contact hole 8A can be sufficiently filled.

See FIG. 3A. 3- (1) By applying a polishing method using an abrasive made of alumina or MnO _2, the W film and the TiN film formed in the step 2- (2) are insulated from each other by interlayer insulation. Polish until the membrane 8 is exposed,
The extraction electrode 9 is formed by leaving only those existing in the electrode contact hole 8A.

See FIG. 3B. 3- (2) By applying the CVD method, the interlayer insulating film 10 made of SiO ₂ having a thickness of, for example, 500 [nm] to 600 [nm] is formed on the entire surface. To do.

See FIG. 4A. 4- (1) Resist process in lithography technology, and
Etching gas is CF ₄ + CHF ₃ mixed gas R
By applying the IE method, the interlayer insulating film 10 is etched to form the wiring pattern groove 10A.

4 (B). 4- (2) By applying the sputtering method, a Cu film having a thickness of 400 nm to 700 nm is deposited on the entire surface.

4- (3) Heat treatment is performed at a temperature of, for example, 350 [° C.] and a time of, for example, 4 [minutes], and the Cu film formed in step 4- (2) is reflowed to form the wiring pattern groove 10A. Fill in.

See FIG. 5A. 5- (1) Formed in step 4- (2) by applying a polishing method using an abrasive containing CuO as abrasive grains, and step 4
The Cu film reflowed in (3) is polished until the inter-layer insulating film 10 is exposed, and the Cu wiring 11 is formed while leaving only the wiring pattern groove 10A.

5- (2) After being immersed in a cleaning solution consisting of HCl + H ₂ O ₂ + H ₂ O (1: 1: 48) for 1 [minute], it was dipped in a scrubber, and finally HF + H ₂ O ₂ + H ₂ O ( It is dipped in a cleaning solution consisting of 1: 1: 198) for 20 seconds.

See FIG. 5B. 5- (3) By performing a heat treatment in a hydrogen atmosphere and then applying a sputtering method, a SiN film 12 having a thickness of, for example, 50 nm is formed. .

5- (4) By applying the CVD method, the thickness is, for example, 500.
An interlayer insulating film 13 made of SiO ₂ having a thickness of [nm] is formed.

See FIG. 6A. 6- (1) A resist process in the lithography technique, and
Etching gas is CF ₄ + CHF ₃ mixed gas R
By applying the IE method, the interlayer insulating film 13 is etched to form the plug hole 13A.

See FIG. 6B. 6- (2) By applying the sputtering method, a TiN film having a thickness of 20 nm to 50 nm and a thickness of 300 nm to 400, for example. A W film of [nm] is formed.
For simplicity, the TiN film and the W film are collectively shown in the figure.

See FIG. 7 7- (1) By applying a polishing method using an abrasive made of alumina or MnO _2, the W film and the TiN film formed in step 6- (2) are formed into the interlayer insulating film 13. Polishing is performed until it is exposed, and only the plug hole 13A is left to form the plug 14.

7- (2) After that, by repeating the above steps such as formation of an interlayer insulating film, a multi-layer wiring can be formed.

Since various experiments have been conducted on wiring during or after the steps described above, the main experimental results obtained will be described below.

Regarding the suppression of etching in the seam In the present invention, CuO used as the abrasive grains is Cu
Since it acts to oxidize and remove W and W, it can be considered as an oxidizer, but since it is poorly soluble in water, the seam that occurs in the wiring embedded in the wiring pattern groove progresses in etching. I confirmed that it was difficult.

That is, the state of seam etching after over-polishing was examined and found to be 0.4 [μm] when the abrasive MSW1000 (manufactured by RODEL, USA) containing Al ₂ O ₃ as abrasive grains was used. When over-polishing corresponding to No. 1 was performed, a number of holes produced by etching the seam portion were visually recognized. However, when using an abrasive containing CuO as abrasive grains, over-polishing equivalent to 0.6 [μm] I couldn't see the seam.

In general, when the seam expands, that is, opens due to etching, impurities and abrasive grains penetrate into the seam, making cleaning difficult, which in turn reduces the reliability of the semiconductor device. What happens is as described above.

○ Effect of Cleaning In order to examine the effect of cleaning, the sample shown in FIG. 8 was prepared. Samples A1, A2, A3 are the abrasives are commercially available MSW1000 (manufactured by U.S. RODEL Co.) H ₂ O
₂ shows the case of polishing by adding,
Nos. 1, B2, B3, and B4 indicate the cases of polishing with CuO.

In all the samples of the lines A and B,

1 is HCl + H ₂ O ₂ + H ₂ O (1: 1:
48) soak for 1 [min] → scrubbing → HF + H ₂ O
_It was immersed in ₂ + H ₂ O (1: 1: 198) for 20 [seconds].

2 is H ₂ SO ₄ + H ₂ O ₂ + H ₂ O (1:
1:48) dipping for 1 [minute] → scrubbing → HF + H
_It was immersed in ₂ O ₂ + H ₂ O (1 :: 1: 198) for 20 [seconds].

3 is HNO ₃ + H ₂ O ₂ + H ₂ O (1:
1:48) dipping for 1 [minute] → scrubbing → HF + H
_It was immersed in ₂ O ₂ + H ₂ O (1: 1: 198) for 20 [seconds].

4 is HF + H ₂ O ₂ + H ₂ O (1: 1: 4)
8) Immerse for 1 [minute] → scrubbing → HF + H ₂ O ₂
It was immersed in + H ₂ O (1: 1: 198) for 20 seconds.

Each sample was subjected to the above-mentioned treatment, and then the wafer surface was subjected to ICP-MS (inductively co
upped plasma mass spectro
Evaluation)

As a result, a sample of system A (MSW10
(Although it is polished with 00), Al remains, and the amount is 1
It is about 00 × 10 ¹⁰ [atoms / cm ² ], which indicates that the abrasive grains Al ₂ O ₃ remain on the wafer surface.

On the other hand, the amount of Cu remaining in the B system sample (polished with CuO) was only about 3 × 10 ¹⁰ [atoms / cm ² ], and it was judged that this did not remain. It is in good condition.

As described above, the reason why Cu does not remain is that C
uO is easily soluble in acid, and HCl, H ₂ SO ₄ , HNO ₃ ,
It is considered that it has dissolved in a solution such as HF or a solution of them and H ₂ O.

[0066]

According to the wiring forming method of the present invention,
Cu, W, Al on the insulating film where the wiring pattern groove is formed
Is formed, and the metal film is polished with an abrasive containing CuO as abrasive grains to form a metal wiring in the wiring pattern groove.

According to the present invention, the material of the polishing agent and the material of the cleaning agent are properly selected. Therefore, when the wiring is formed by embedding the metal in the wiring pattern groove, the abrasive grains in the polishing agent remain. Or the adhesion between the wiring and the base is impaired,
There is no problem that the seam of the wiring that fills the groove is opened and impurities and abrasive grains penetrate into the seam to make cleaning difficult. Therefore, a highly reliable semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is a cutaway side view of a main part of a semiconductor device in a process main part for explaining an embodiment of the present invention.

FIG. 2 is a side sectional view showing a main part of a semiconductor device in a process main part for explaining an embodiment of the present invention.

FIG. 3 is a cutaway side view of a main part showing a semiconductor device in a process main part for explaining an embodiment of the present invention.

FIG. 4 is a side sectional view showing a main part of a semiconductor device in process steps for explaining the embodiment of the invention.

FIG. 5 is a side sectional view showing an essential part of a semiconductor device in a process essential part for explaining an embodiment of the present invention.

FIG. 6 is a side sectional view showing a main part of a semiconductor device in a process main part for explaining an embodiment of the present invention.

FIG. 7 is a fragmentary side view showing a semiconductor device in a process essential part for explaining the embodiment of the invention.

FIG. 8 is a table in which data regarding samples for examining the effect of the present invention is summarized in a table.

[Explanation of symbols]

1 Si semiconductor substrate 2 element isolation insulating film 3 gate insulating film 4 gate electrode 5 n ^- source region 5A n ⁺ source region 6 n ^- drain region 6A n ⁺ drain region 7 side wall 8 interlayer insulating film 8A electrode contact hole 9 Lead Electrode 10 Interlayer Insulation Film 10A Wiring Pattern Groove 11 Cu Wiring 12 SiN Film 13 Interlayer Insulation Film 13A Plug Hole 14 Plug

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Akira Oishi, Akira Oishi, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Rentaro Taro, 1015, Uedanaka, Nakahara-ku, Kawasaki, Kanagawa, Fujitsu Limited (72) Inventor Yoshihiro Arimoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor Shigeo Ueda 4-12-25 Fujimi, Kitadachi-gun Fukiage-cho, Saitama Prefecture (72) Inventor Kenzo Hanawa 1380-1 Hara City, Ageo City, Saitama Prefecture

Claims (2)

[Claims] 1. C is formed on an insulating film having a wiring pattern groove formed therein.
a step of forming an oxidizable metal film of u, W, Al, etc .; and a step of polishing the metal film with an abrasive having CuO as abrasive grains to form a metal wiring in the wiring pattern groove. A wiring forming method characterized by being included. 2. The wiring forming method according to claim 1, further comprising a step of washing the polished wafer with an acid or an alkali.