KR100845806B1 - Semiconductor device having probing pads, which improved integrated efficiency - Google Patents

Abstract

A semiconductor device including a probing pad having an improved degree of integration is provided to shorten the lengths of data lines arranged in a peripheral region by changing the position of a probing pad. A peripheral circuit part and a plurality of data lines are arranged in a first peripheral region(110a). A second peripheral region(110b), arranged adjacent to the first peripheral region, includes a bonding pad array region and an eccentric securing region(110c). A probing pad(150) is arranged in the eccentric securing region. In the bonding pad array region, a plurality of bonding pads are composed of data input/output pads and power pads. The probing pad of the eccentric securing region corresponds to the power pad.

Description

Semiconductor devices having probing pads, which improved integrated efficiency

1 is a plan view of a semiconductor device having a general peripheral region,

2 is a diagram illustrating an arrangement of data wires in a peripheral area of the semiconductor device of FIG. 1;

3 is a plan view of a semiconductor device having a probing pad in an eccentric amount securing region according to an embodiment of the present invention;

4 is a plan view of a semiconductor device having a probing pad in an eccentricity securing region according to another embodiment of the present invention;

5 is an enlarged plan view illustrating a region around the DQ of FIG. 4.

<Explanation of symbols for main parts of the drawings>

110: peripheral region 110a: first peripheral region

110b: second peripheral region 110c: eccentricity securing region

130: bonding pad 150: probing pad

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a probing pad with improved integration efficiency.

Typically, a semiconductor device has pads for enabling electrical connection between the semiconductor device and the outside. Such pads include pads for inputting and outputting commands or data for operation of the semiconductor device (hereinafter, referred to as data input / output pads), pads provided with a power supply voltage and a ground voltage (hereinafter referred to as power supply pads), and probing pads.

Here, the probing pad is electrically connected to each part of the semiconductor device similarly to the data entry pad and the power pad, but is used to test whether the semiconductor devices integrated on the wafer are normally formed before the sawing. This test may be conducted by a probing device, whereby a probe of the probing device contacts the probing pad to perform the test.

1 is a plan view of a semiconductor device having a general probing pad.

Referring to the drawings, the semiconductor device 10 may include a plurality of banks BANK0-BANK7, and the plurality of banks BANK0-BANK7 may be arranged in two rows, for example. Here, L1 represents a first column in which banks are arranged, and L2 represents a second column disposed under the first column L1 and composed of a plurality of banks.

The first row L1 and the second row L2 are spaced apart from each other with the peripheral area 20 interposed therebetween, and the Y fuse part between the peripheral area 20 and the first and second rows L1 and L2. 30a and 30b are positioned to provide an extra circuit pattern (not shown) common to the banks BANK0-BANK7 located in the same column L1, L2.

Here, the peripheral region 20 may be divided into a first peripheral region 21 adjacent to the first column L1 and a second peripheral region 23 adjacent to the second column L2. Peripheral area 21 is a peripheral circuit block 41 consisting of a unit cell (not shown) and a block cell (not shown), data wiring such as a global line, and probing pads for probe testing. All 43 are arranged. In the second peripheral region 23, data input / output pads and power pads 48a and 48b are arranged as bonding pads. In this case, the data input / output pads and the power pads 48a and 48b are parts to be molded at the time of packaging. In order to secure a molding area, the data input / output pads and the power pads 48a and 48b include a Y fuse 30b. It should be spaced apart from the second column L2 by a predetermined distance. Reference numeral 50 denotes an X fuse disposed between banks formed in the same column.

Recently, the manufacturing technology of semiconductor memory devices is on the trend of high integration due to the reduction of design rules. This high integration reduces the size of the semiconductor memory device and increases the number of net dies produced in the semiconductor wafer, thereby reducing the cost.

By the way, although the degree of integration of the devices mounted in the semiconductor memory device is increased exponentially, the size of each pad should maintain the previous size for probing test and wire bonding. Therefore, the area occupied by the pads in the semiconductor device is relatively increased. Accordingly, in order to manufacture a semiconductor memory device having a higher degree of integration, the area occupied by the pads must be reduced.

In addition, as described above, the probing pads 43 are disposed in the first peripheral area 21 together with the global line 45 as shown in FIG. 2. As the global line 45 and the probing pad 43 are disposed in the same peripheral area 21, the global lines 45 extend in a straight line, and the probing pad 43 is disposed at the portion where the probing pad 43 is disposed. It should be bent to pass the outside of the pad 43. 45a in the figure indicates the bent portion. The bending of the global line 45 substantially extends the length of the global line 45, which may increase wiring resistance, and cause disconnection of the global line 45 at the bent portion 45a. .

Accordingly, it is an object of the present invention to provide a semiconductor device capable of securing an area of a peripheral region.

Further, another object of the present invention is to provide a semiconductor device capable of reducing the resistance of data wirings arranged in the peripheral area and preventing disconnection.

In order to achieve the above object of the present invention, the semiconductor device of the present invention includes a first peripheral region in which peripheral circuit portions and data lines are arranged, and an area and an eccentric amount in which bonding pads are arranged adjacent to the first peripheral region. And a second peripheral region including the securing region. A probing pad is disposed in the eccentric amount securing area.

In addition, a semiconductor device according to another exemplary embodiment of the present invention may include a first bank column including a plurality of banks, a second bank disposed in parallel with a predetermined distance from the first bank column, and configured as a plurality of banks. A column, and a peripheral region disposed between the first bank column and the second bank column. The peripheral area includes a first peripheral area in which peripheral circuit blocks and data wires are arranged, and a second peripheral area disposed adjacent to the first peripheral area and configured as an eccentric amount securing area in which probing pads are arranged. It is composed of areas.

In an embodiment, a semiconductor device may include a first bank column including a plurality of banks, a second bank column disposed in parallel with a predetermined distance from the first bank column, And a peripheral area disposed between the first bank row and the second bank row, the peripheral area including a DQ peripheral area and an address peripheral area. In this case, each of the DQ peripheral area and the address peripheral area is a first peripheral area in which peripheral circuit blocks and data lines are arranged, and an eccentric amount in which a probing pad and an area formed of bonding pads are arranged adjacent to the first peripheral area. It consists of a 2nd peripheral area | region comprised of a securing area | region.

Here, in the second peripheral region of the DQ peripheral region, the bonding pads are data input / output pads and power pads, and the probing pads are positioned to correspond to the power pads.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings.

Referring to FIG. 3, the semiconductor device 100, for example, the semiconductor memory device, includes a plurality of banks BANK0-BANK7. The banks BANK0-BANK7 are known as a collection of a plurality of memory cells, and may be a plurality, for example, four, eight or more. In this embodiment, a semiconductor memory device having eight banks will be described as an example. Eight banks BANK0-BANK7 may be arranged in two rows. That is, four banks may form one bank line, such that two bank columns bL1 and bL2 may be arranged in parallel with each other. In this case, the first bank column bL1 may be composed of the 0th, 1st, 4th, and 5th banks BANK0, BANK1, BANK4, and BANK5, and the second bank column bL2 is the 2nd and 3rd banks. And 6th and 7th banks (BANK2, BANK3, BANK6, BANK7).

Here, the first X fuse part 105a is positioned between the 0th and 1st banks BANK0 and BANK1 so that the first X fuse part 105a is the X of the 0th and 1st banks BANK0 and BANK1. Relieve this in case of disconnection of axis wiring, ie word line. A second X fuse part 105b is also located between the second and third banks BANK2 and BANK3, and the second X fuse part 150b has X-axis wiring of the second and third banks BANK2 and BANK3. Relieve this in case of disconnection. Similarly, the third X fuse part 105c and the fourth fuse part 105d are located between the fourth and fifth banks and between the sixth and seventh banks BANK6 and BANK7, respectively.

The peripheral region 110 is positioned between the first bank column bL1 and the second bank column bL2. The peripheral region 110 may include a first peripheral region 110a disposed adjacent to the first bank column bL1 and a second peripheral region 110b disposed adjacent to the second bank column bL2. At this time, between the first bank column bL1 and the first peripheral region 110a, the Y-axis wiring of the banks BANK0, BANK1, BANK4, and BANK5 constituting the first bank column bL1, for example, a bit line The first Y-fuse part 120a is inserted and arranged to relieve this when the wires are disconnected. In addition, between the second peripheral region 110b and the second bank column bL2, the Y-axis wiring of the banks BANK2, BANK3, BANK6, and BANK7 constituting the second bank column bL2, for example, disconnection of the bit lines. The second Y-fuse part 120b is inserted into and disposed to relieve the tooth.

The first peripheral area 110a may include a peripheral circuit block 114 and a data line (not shown) including a unit cell (not shown) and a block cell (not shown). Here, the unit cell may be a unit element constituting the block cell, for example, may be a power supply circuit. In addition, the data line may be a global line 116 for transferring power or a predetermined signal to each bank.

Meanwhile, the second peripheral region 110b is insulated between the bonding pads 130 and the second bank row 120b including the bonding pads 130 and the second Y-fuse part 120b. It may be configured as an eccentric amount securing area (110c) for providing. The bonding pad 130 may be, for example, the data input / output pad 130a and the power pads 130b, and for example, the data input / output pad 130a and the power pad 130b may be alternately arranged. The eccentricity secured area 110c, as the name implies, is an area left blank to provide a sufficient eccentric amount P. Here, the eccentric amount P is a distance between the bonding pad 130 and the center of the first peripheral region 110a and is a region where wire bonding is performed. Therefore, the amount of eccentricity P is also a part to be molded in a later package process. Accordingly, a certain space is required to reduce electrical crosstalk between the wire (not shown) in contact with the bonding pads 130 and the second bank row bL2 including the Y fuse part 120b. This space is referred to as an eccentricity securing region 110c. In this embodiment, the probing pads 150 for the probe test are disposed in the empty eccentricity securing region 110c. Since the eccentricity securing region 110c of the general semiconductor memory device has an area sufficient to accommodate the probing pad 150, the probing pads 150 may be disposed in the eccentricity securing region 110c.

Accordingly, since the probing pad is not positioned in the first peripheral region 110a of the present embodiment, the unit cell area and the block cell area 114 can be sufficiently secured, and as much as the area occupied by the probing pad is obtained. The area of the first peripheral region 110a may be reduced. In addition, since the probing pad is not positioned in the first peripheral region 110a, the global line 116 extends in a straight line as shown in the figure, thereby reducing the length of the global line 116 and preventing disconnection. Can be.

As shown in FIG. 4, the peripheral region 110 may be divided into a DQ peripheral region 200a and an address peripheral region 200b. The DQ peripheral area 200a and the address peripheral area 200b may be formed by dividing the peripheral area 110 from side to side, for example, and each of the DQ peripheral area 200a and the address peripheral area 200b may be a first peripheral area ( 110a) and a second peripheral region 110b.

Although not shown in FIG. 4, each of the first peripheral regions 110a and 110a ′ of the DQ peripheral region 200a and the address peripheral region 200b includes peripheral circuit blocks and global lines composed of unit cells and block cells; The same data wiring can be arranged.

As described above, each of the second peripheral regions 110b and 110b 'of the DQ peripheral region 200a and the address peripheral region 200b includes the region where the bonding pads 130 are disposed and the eccentricity securing region 110c and 110c'. Probing pads 150 are disposed in each of the eccentricity securing regions 110c and 110c '. In this case, the bonding pads 130 of the DQ peripheral area 200a may be a data input / output pad 130a and a power pad 130b, and the bonding pads 130 of the address peripheral area 200b may be an address pad. 130c.

As shown in FIG. 5, the DQ peripheral region 200a includes a peripheral circuit block (not shown) including a unit cell 112 and a block cell (not shown) in its first peripheral region 110a. And data lines (not shown) such as a global line are arranged, and data input / output pads 130a and power pads 130b are alternately arranged side by side in the second peripheral region 110b thereof. However, typically, an electrostatic discharge (ESD) circuit unit 140 is disposed around the data input / output pad 130a to discharge the electrostatic or sudden high voltage or low voltage. Therefore, the space enough to position the probing pad 150 is not provided in the eccentricity secured area 110c around the data input / output pad 130a. Accordingly, in this embodiment, the probing pad 150 in the DQ peripheral area 200a is preferably disposed in the eccentric amount securing area 110c corresponding to the power pad 130b.

On the other hand, since the address peripheral area 200b does not include the ESD circuit unit 140 described above, the probing pad 150 may be arranged anywhere in the eccentricity securing area 110c 'in the address peripheral area 200b.

According to this embodiment, by arranging the probing pad 150 in the eccentricity secured area 110c of the peripheral area, which is empty, the area of the first peripheral area 110a in which the conventional probing pad 150 has been arranged can be reduced. As a result, high integration of semiconductor devices can be achieved.

In addition, as the probing pad 150 is disposed in the eccentricity securing region 110c as in the present embodiment, it is not necessary to bend the global line 116 to surround the outside of the probing pad 150, thereby substantially the global line. 116 can be reduced in length.

This embodiment is not limited to the above embodiment.

For example, the present embodiment has described a memory device having eight BANKs by way of example, but the present invention is not limited thereto, and any semiconductor device including an eccentricity securing region and in which a probing pad may be disposed in the eccentricity securing region is here. Included in

In the present embodiment, two bank columns have been described as an example, but all semiconductor devices having more bank columns are included in the present invention.

In this embodiment, the wiring extending to the X axis is a word line, the wiring extending to the Y axis is a bit line, the X fuse part is a word line relief part, and the Y fuse part is a bit line relief part. It is a matter of course that the wiring extending to the X-axis may be a bit line, the wiring extending to the Y-axis may be a word line, the X fuse portion may be a bit line relief portion, and the Y fuse portion may be a word line relief portion.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. Do.

As described in detail above, according to the present invention, by arranging the probing pads in the eccentric amount securing region, the area of the peripheral region can be secured and higher integration can be achieved.

In addition, by changing the position of the probing pad, the length of the data wires disposed in the peripheral area can be shortened, thereby improving the speed characteristic of the semiconductor device.

Claims (10)

A first peripheral region in which peripheral circuit portions and data wires are arranged; And A second peripheral area disposed adjacent to the first peripheral area and including an area in which bonding pads are arranged and an eccentricity securing area; A probing pad is disposed in the eccentric amount securing region. The method of claim 1, The bonding pads include data input / output pads and power pads. The probing pad is disposed in the eccentricity securing region corresponding to the power pad. The method according to claim 1 or 2, A first bank row arranged side by side outside the first peripheral region and composed of a plurality of banks, and A second bank row arranged side by side outside of the second peripheral region, the second bank row comprising a plurality of banks; The eccentricity secured area is an area between the bonding pad area of the second peripheral area and the second bank row to exclude electrical crosstalk between the banks constituting the bonding pad and the second bank row. Semiconductor device. The method of claim 3, wherein And the data line extends substantially straight. The method of claim 1, The first peripheral area and the second peripheral area are divided into a DQ peripheral area and an address peripheral area, respectively. A data input / output pad and a power pad are arranged in a portion corresponding to the second peripheral region of the DQ peripheral region, The probing pad is located in the eccentric amount securing area of the second peripheral area corresponding to the power pad. And an ESD pad disposed in a second peripheral region corresponding to the data input / output pad. The method of claim 5, wherein And an address pad further positioned in a second peripheral region of the address peripheral region. A first bank column composed of a plurality of banks; A second bank column disposed parallel to the first bank row and spaced apart from the first bank row by a plurality of banks; And A peripheral region disposed between the first and second bank columns, the peripheral region including a DQ peripheral region and an address peripheral region; Each of the DQ peripheral area and the address peripheral area includes a first peripheral area in which peripheral circuit blocks and data wires are arranged, and an eccentric amount securing area in which an area formed of bonding pads and an eccentric pad are arranged adjacent to the first peripheral area. A semiconductor device comprising a second peripheral region constituted by. The method of claim 7, wherein And a fuse portion for relieving wirings constituting respective bank rows between the first bank row and the first peripheral region and between the second bank row and the second peripheral region. The method according to claim 7 or 8, And a fuse unit for relieving the wirings forming the banks in at least one portion of a space between the respective banks constituting the first bank row and the second bank row. The method of claim 10, wherein in the second peripheral region of the DQ peripheral region, The bonding pads are data input / output pads and power pads. And the probing pad is positioned to correspond to the power pad.

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