KR20120052440A

KR20120052440A - Semiconductor integrated circuit apparatus having fuses

Info

Publication number: KR20120052440A
Application number: KR1020100113282A
Authority: KR
Inventors: 유정택
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2010-11-15
Filing date: 2010-11-15
Publication date: 2012-05-24

Abstract

PURPOSE: A semiconductor integrated circuit device is provided to improve integration of the semiconductor integrated circuit device by decreasing an area of a fuse block. CONSTITUTION: A plurality of redundancy fuses(FA) are formed in a guard ring. A fuse block includes a plurality of logic fuses for providing a mode signal which are continuously arranged with the plurality of redundancy fuses in the guard ring. A fuse block is arranged in the outside of the banks. A peripheral area is located in a space between banks. A logic circuit unit(300) is electrically connected to the logic fuses in the peripheral area.

Description

Semiconductor Integrated Circuit Apparatus Including Fuses {Semiconductor Integrated Circuit Apparatus Having Fuses}

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device including a fuse.

In semiconductor integrated circuit devices, fuses are used to repair defective cells, store chip identification, and provide various mode signals. The fuse may be formed of a metal pattern in the form of a line, and the cutting may be performed by laser blowing.

1 is a plan view illustrating a general semiconductor integrated circuit device.

Referring to FIG. 1, the semiconductor integrated circuit device 10 includes a plurality of banks 20a-20d. The plurality of banks 20a-20d may be spaced apart from each other with the peripheral area 30 interposed therebetween, and arranged in a matrix form, for example. Each bank 20a-20d includes a plurality of word lines WL and a plurality of bit lines BL that are cross-arranged, and a row decoder 40 and a row fuse at one edge that crosses the word line WL. The block 45 is disposed to correspond to the adjacent banks 20a-20d, and the column decoder 50 and the column fuse block 55 are disposed at one edge crossing the bit line BL. Here, the low fuse block 45 may be referred to as a low redundancy fuse block because it includes a plurality of low redundancy fuses by group, and the column fuse block 55 includes a column including a plurality of column redundancy fuses by group. It may be referred to as a redundant fuse block.

A plurality of pads 60 and logic fuse blocks 70 are disposed in the peripheral region 30 between the banks 20a-20d arranged in the bit line BL direction. As described above, the logic fuse block 70 is a signal generation block for providing a predetermined mode signal to a circuit constituting a semiconductor integrated device circuit value, and as illustrated in FIG. 2, a plurality of fuses 70a are arranged in a line. It is configured. At this time, the fuse block 70 is surrounded by a guard ring 75, the guard ring 75 serves to protect the fuses 70a from external moisture.

However, as the integration density of a semiconductor integrated circuit device increases, the ratio of the peripheral area, particularly the fuse block area, to the total chip area is gradually increased. For this reason, although it is required to reduce the area of the fuse block, it is difficult to reduce the area any more with the current laser fuse using laser blowing.

Accordingly, the present invention is to provide a semiconductor integrated circuit device capable of reducing the ratio of fuse blocks to the total chip area.

The semiconductor integrated circuit device of the present invention for achieving the above object of the present invention is arranged in series with a guard ring, a plurality of redundancy fuses provided in the guard ring, and the plurality of redundancy fuses in the guard ring. And a fuse block having a plurality of logic fuses for providing a mode signal.

In addition, a semiconductor integrated circuit device according to another exemplary embodiment of the present invention may be divided at predetermined intervals by a peripheral area, and include a plurality of banks including a plurality of word lines and a plurality of bit lines that cross each other, and are perpendicular to the word lines. A low redundancy fuse block located at one end of the bank, a column redundancy fuse block located at one end of the bank perpendicular to the bit line, and at least one logic circuit part disposed in the peripheral region; At least one of the low redundancy fuse block and the column redundancy fuse block includes option fuses electrically connected to the logic circuit unit.

In accordance with the present invention, logic fuses are provided that provide options in the column or low redundancy fuse block. Accordingly, since the redundancy fuse and the logic fuses are surrounded by one guard ring, the area between the guard ring and the fuse is reduced for each individual logic fuse block.

In addition, by embedding the logic fuse block formed in the peripheral area in the column or the low redundancy fuse block, the routing of the wiring can be reduced, thereby reducing the wiring resistance and securing the wiring area.

As such, the area of the fuse block can be reduced, and thus the integration density of the semiconductor integrated circuit device can be greatly improved.

1 is a plan view of a general semiconductor integrated circuit device,
2 is a plan view schematically showing a typical fuse block;
3 is a plan view showing a fuse block according to an embodiment of the present invention, and
4 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Therefore, the shapes and the like of the elements in the drawings are exaggerated in order to emphasize a clearer description, and elements denoted by the same symbols in the drawings denote the same elements.

Referring to FIG. 3, the fuse block 100 includes both redundancy fuses FA and logic fuses FB. That is, the redundancy fuses FA are arranged in parallel in one direction with a constant equal interval, and the logic fuses FB are also continuously arranged in parallel in the one direction with a constant equal interval with the redundancy fuses FA. . In this case, the constant equal interval may be a laser tolerance. The logic fuses FB may be, as is known, a signal generation member for providing a mode signal, that is, an option.

Such redundancy fuses FA and logic fuses FB are surrounded by one guard ring 110 to define one fuse block 100.

The fuse block 100 of the present embodiment is installed with the redundancy fuses FA and logic fuses FB integrated in one guard ring 110, the following individual redundancy fuse block 45 or 55 of FIG. ) And the area of the individual logic fuse block 70 may be reduced by a predetermined value (for example, the distance x 2 between the guard ring and the fuse) per fuse block 100.

4 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention.

Referring to FIG. 4, the logic fuses FB of the fuse block 100 of the present exemplary embodiment may be formed by the logic circuit unit 300 and the wiring 350 installed in the peripheral area 200 between banks (not shown). Are interconnected. That is, since the logic fuses FB generate the mode signal through proper cutting, the logic fuses FB may be properly connected to the logic circuit unit 300 that requires the mode signal.

In this case, the fuse block 100 may be, for example, a column redundancy fuse block. However, the present invention is not limited thereto, and the fuse block of the present embodiment may be applied to the low redundancy fuse block.

As the logic fuses FB are integrally installed with the redundancy fuses FA, there is no need to install a separate logic fuse block in the peripheral area 200. Accordingly, in the formation of the wiring passing over the peripheral region 200, the logic fuse block need not be formed by routing the logic fuse block.

In addition, as described above with reference to FIG. 3, the logic fuses FB and the redundancy fuses FA are respectively integrated to be bundled by one guard ring 110, thereby reducing the area between the guard ring and the fuses. Therefore, the area of the fuse block 100 itself may also be reduced.

Therefore, it is possible to greatly reduce the area of the fuse block relative to the total chip area.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

100: fuse block FA: redundancy fuses
FB: logic fuses 110: guard ring
200: peripheral area 300: logic circuit
350: wiring

Claims

Guard ring;
A plurality of redundancy fuses provided in the guard ring; And
And a fuse block having a plurality of logic fuses for providing a mode signal arranged in series with said plurality of redundancy fuses in said guard ring.

The method of claim 1,
Further comprising a plurality of banks,
And the fuse blocks are disposed at one outer side of the banks, respectively.

The method of claim 2,
And a peripheral region located in the space between the banks.

The method of claim 3, wherein
And a logic circuit portion electrically connected to the logic fuses in the peripheral area.

The method of claim 4, wherein
And the logic fuses and the logic circuit portion are electrically connected by metal wires.

A plurality of banks separated by a predetermined area by a peripheral area and including a plurality of word lines and a plurality of bit lines crossing each other;
A low redundancy fuse block positioned at one end of the bank perpendicular to the word line;
A column redundancy fuse block positioned at one end of the bank perpendicular to the bit line;
At least one logic circuit portion disposed in the peripheral region,
And at least one of the low redundancy fuse block or the column redundancy fuse block includes option fuses electrically connected to the logic circuit portion.