KR100842923B1 - Method of manufacture enhancement mode semiconductor probe using anisotropic wet etching and side-wall, and an information storage device using thereof - Google Patents

Abstract

A method of manufacturing an enhancement semiconductor probe and an information storage device using the same are provided to reduce a process variable in device performance and to increase reliability of mass production by anisotropic-wet-etching a silicon substrate using side-walls. A method of manufacturing an enhancement semiconductor probe comprises the steps of: forming a first etching mask pattern(110a) on a silicon substrate(100c) to form a tip part of the probe in a first direction and forming side-wall areas at two sides of the first etching mask pattern; anisotropic-etching the silicon substrate to form two inclined surfaces of the probe; forming source and drain areas(160,170,180,190) on the silicon substrate by injecting dopants, using the side-wall area as masks, and removing the side-wall areas; removing the first etching mask pattern; forming a second etching mask pattern to form a tip part of the probe in a second direction; forming space layers at two sides of the second etching mask pattern; and etching the silicon substrate by photographing and etching processes and removing the space layers.

Description

METHOD OF MANUFACTURE ENHANCEMENT MODE SEMICONDUCTOR PROBE USING ANISOTROPIC WET ETCHING AND SIDE-WALL, AND AN INFORMATION STORAGE DEVICE USING THEREOF}

1A to 1J are process cross-sectional views illustrating a method of manufacturing a semiconductor probe with a resistive tip according to the prior art.

2 is a circuit diagram modeling a semiconductor probe with a conventional resistive tip

3A to 3V are cross-sectional views illustrating a method of manufacturing an increased semiconductor probe using sidewall regions and anisotropic wet etching according to the present invention.

Figure 4 is a comparison of the simulation results of the conventional and the present invention

[Description of Major Symbols in Drawings]

DESCRIPTION OF SYMBOLS 100 Silicon (Si) substrate 110 First etching mask layer

120: second etching mask layer 130: photosensitive agent

140: space film 150: side wall area

160, 170: deep source, drain region

180, 190: shallow source, drain region

210: third etching mask layer 220: fourth etching mask layer

230: photosensitive agent 240: space film

250: space membrane or HSQ

300 probe

The present invention relates to a method for manufacturing an increased semiconductor probe using sidewall regions and anisotropic wet etching, and an information storage device using the same. In particular, the reliability of the device in mass production can be improved by reducing the influence of process variables on the device performance. The present invention relates to a method for manufacturing an increased semiconductor probe using sidewall regions and anisotropic wet etching, and to an information storage device using the same, which can improve device performance by resolving factors that previously impaired measurement sensitivity.

Ferroelectric materials have received a lot of attention in recent years. Various devices have been studied and developed so far to read information stored in such ferroelectric materials. One of them, the resistive probe, shows high sensitivity and resolution compared to the previous observer, and has many possibilities as a next-generation probe because it is much easier to use.

However, the process method used up to now in the device fabrication is very likely to significantly change the device performance according to the process variable, there is a problem that the performance of the probe is lowered than expected due to various problems to be presented later. Therefore, further development of probes considering commercialization requires a process method having higher sensitivity and resolution and less influence of process variables.

Hereinafter, a conventional method for manufacturing a semiconductor probe and its problems will be described with reference to the accompanying drawings.

1A to 1J are process cross-sectional views illustrating a method of manufacturing a semiconductor probe with a resistive tip according to the prior art.

First, as shown in FIG. 1A, a mask film 13, such as a silicon oxide film or a silicon nitride film, is formed on a surface of a silicon substrate 11 or a silicon on insulator (SOI) substrate doped with a first impurity. 15) is applied to the upper surface thereof, and then the stripe mask 18 is placed thereon.

The patterning is then performed by exposure, shape and etching processes. As shown in FIG. 5B, a stripe-type mask film 13a is formed on the substrate 11 through a photolithography and an etching process, and then a region except for the mask film 13a is heavily doped with second impurities. Doped to form first and second semiconductor electrode regions 12 and 14.

Then, an annealing process is performed to reduce the width between the first and second semiconductor electrode regions 12 and 14 to the width of the mask film 13a. As shown in FIG. 1C, when the high concentration regions 12 and 14 of the second impurity are enlarged, the second impurity is diffused in the region adjacent to the high concentration region to form the low concentration region of the second impurity. That is, the resistance region 16 is formed. The resistive regions 336 under the mask layer 13a are in contact with each other to form a peak forming portion of the resistive tip described later.

Next, a photosensitive agent 19 is applied to the upper surface of the substrate 11 to cover the mask film 13a, and then the stripe type is orthogonal to the mask film 13a, as shown in FIG. 5D. When the photomask 20 is disposed and subjected to exposure, development, and etching processes, a photoresist layer 19a having the same shape as that of the photomask 20 is formed (see FIG. 1E).

Next, the mask film 13a not covered with the stripe-type photosensitive agent 19a is dry etched to form a rectangular mask film 13b (see FIG. 1F).

Next, as illustrated in FIG. 1G, after the photosensitive agent 19a is removed, the substrate 11 is wet or dry etched using the rectangular mask layer 13b as a mask to be applied to the inclined surface of the tip 10. The first and second semiconductor electrode regions 12 and 14 are positioned, and the resistance region 16 is aligned with the tip of the tip 20 (see FIG. 1H).

Then, after removing the mask film 13b and heating the substrate 11 in an oxygen atmosphere, a silicon oxide film (not shown) having a predetermined thickness is formed on the upper surface of the substrate 11, and the oxide film is removed. The end of the resistive region 16 becomes sharp. This thermal oxidation process may overlap the isolated resistive region 16 with sharpening of the tip.

Next, as shown in FIG. 1I, a dielectric layer 30 covering the resistive tip 10 is deposited on the substrate 11. In addition, the dielectric layer 30 on the end of the tip 10 is planarized by a chemical-mechanical polishing (CMP) process. Subsequently, metal is deposited on the dielectric layer 30 to form a metal shield 32. Thereafter, the metal of the region facing the resistance region 16 is removed by a patterning process to form an opening 33 having a predetermined size in the metal shield 32.

Next, as shown in FIG. 1J, the cantilever 40 is formed by etching the bottom surface of the substrate 11 so that the resistive tip 10 is positioned at the distal end portion, and the first and second semiconductor electrode regions ( 12) 14 is connected to the electrode pad 54 insulated by the insulating layer 52 on the substrate 11 to complete the semiconductor probe. In addition, an electrode pad 64 for ground voltage is formed on the metal shield 32.

As described above, in the conventional method of manufacturing a semiconductor probe with a resistive tip, a pyramidal probe is formed by using a mask having a thickness of several micrometers and isotropic wet etching. In this method, the performance of the device is changed greatly according to the position and size of the mask. In other words, large process variables are placed in attempts to create the probe's vertices in the correct position using a huge mask. This traditional method, which relies heavily on process variables, poses a major obstacle to the manufacture and use of probes in commercial terms. Therefore, mask fabrication and etching methods, which are relatively free from process variables, are indispensable conditions for reliable device production. In addition, to fabricate the device, a small mask should be used to reduce the error factor from the beginning.

Mask width 4㎛ 4.02㎛ 4.1㎛ Sensitivity 0.031% 0.02% 0.017%

Table 1 shows the sensitivity of the probe according to the mask width as a simulation result. Even if the size of the mask shows an error of about 0.5% of the intended size, the sensitivity decreases by about 30%. The presence of these process variables affecting device performance is a major obstacle to the commercialization of devices in the future and must be addressed.

In addition to the problems mentioned above, smaller than the intended sensitivity of the device has many problems, including performance degradation in the application of the device. The cause of such degradation is the high concentration of doped source and drain regions in the wet etching process, which are present as low concentration doping regions. This is because there is almost no increase.

The above device can be modeled as shown in FIG. In the figure, when the source and drain regions, Rs and Rd, are so large that a voltage source is applied across them, even if the resistance Rm at the tip of the probe changes, there is little change in the total current. In addition, Rm, the storage of the area that can be called the actual charge sensing area, is much larger than R1, the lower part, so that most of the current flows into the R1 area, and the effect of Rm on the overall current is very small. Therefore, for higher device sensitivity, it is necessary to make R1 very large than Rm and reduce the resistance of the source and drain regions.

Accordingly, the present invention has been made to solve the above problems, and the first object of the present invention is to reduce the influence of process variables on the performance of the device, thereby increasing the reliability of the device in mass production, and also to improve the previous measurement sensitivity. The present invention provides a method for manufacturing an increased semiconductor probe using sidewall regions and anisotropic wet etching that can improve device performance by resolving factors that have hindered the problem.

In addition, a second object of the present invention is to provide an information storage device using a method of manufacturing an increased semiconductor probe using the sidewall region of the first object and anisotropic wet etching.

According to an aspect of the present invention, there is provided a method of manufacturing an increased semiconductor probe using sidewall regions and anisotropic wet etching, comprising: (a) forming a tip portion in a first direction on a silicon substrate; Forming an etch mask pattern and forming sidewall regions on both sides thereof; (b) anisotropically etching the silicon substrate using the sidewall regions to form both inclined surfaces of the probe; (c) implanting impurities into the sidewall regions as a mask to form source and drain regions on the silicon substrate and then removing the sidewall regions; (d) forming source and drain regions on both inclined surfaces of the probe by using the first etch mask pattern as a mask, and then removing the first etch mask pattern; (e) forming a second etching mask pattern on the tip of the probe to form a tip of the probe in a second direction; (f) forming space layers on both sides of the second etching mask pattern; And (g) removing the space film after etching the silicon substrate to a predetermined depth by a photo and etching process using the space film.

The method of forming the first etching mask pattern in the step (a) may include: (a1) sequentially stacking a first etching mask layer, a second etching mask layer, and a photoresist on the silicon substrate; (a2) etching the second etching mask layer through the photolithography and etching process after patterning the photoresist; (a3) forming a space film on sidewalls of the second etch mask layer after removing the photoresist; (a4) etching the first etch mask layer using the space layer after removing the second etch mask layer; And (a5) removing the space layer to form the first etch mask pattern.

The first etching mask layer and the second etching mask layer may be formed of a material having different etching selectivity from each other.

The first etching mask layer may be formed of silicon oxide (SiO ₂ ), and the second etching mask layer may be formed of nitride (SiNx).

The method of forming the second etching mask pattern in the step (e) comprises the steps of: (e1) sequentially depositing a third etching mask layer, a fourth etching mask layer, a photoresist on the silicon substrate; (e2) etching the fourth etch mask layer through a photolithography and an etching process after patterning the photoresist; (e3) forming a space film on sidewalls of the fourth etch mask layer after removing the photoresist; (e4) etching the third etch mask layer using the space layer after removing the fourth etch mask layer; And (e5) removing the space layer to form the second etching mask pattern.

The third etching mask layer and the fourth etching mask layer may be formed of a material having different etching selectivity from each other.

The third etching mask layer may be formed of silicon oxide (SiO ₂ ), and the fourth etching mask layer may be formed of nitride (SiNx).

The side wall region in the step (a) is characterized in that formed using the nitride (SiNx).

The space film in step (f) is characterized in that it is formed using hydrogen silsequioxane (HSQ).

Further, an information storage device having an increased semiconductor probe according to the present invention for achieving the above object is produced by the method according to any one of claims 1 to 9.

Therefore, by reducing the influence of process variables on the performance of the device, it is possible to increase the reliability of the device in mass production, and to improve the device performance by solving the factors that previously hindered the measurement sensitivity.

Hereinafter, with reference to the accompanying drawings will be described in detail the increased semiconductor probe using a side wall region and anisotropic wet etching, an information storage device having the same and a manufacturing method thereof according to the present invention.

Example

First, there is a problem in that device performance is largely influenced by process variables in the process of forming a fine probe tip using a huge mask. In order to solve this problem, the size of the mask for forming the tip was produced in a very small size (see FIG. 3G). In addition, a method using a sidewall region was used to form a commercially available mask having a small size.

Next, in order to reduce the resistance by securing a highly doped source and drain regions, the etching method was selected after the first etching rather than the etching method after the previous doping. To this end, as shown in FIG. 3H, an etching process using a sidewall region is first performed, and then, as shown in FIG. 3I, a method of forming a shallowly doped source and drain region using a mask made before is introduced. In addition, a transfer method using anisotropic etching (see FIG. 3H) and HSQ (hydrogen silsequioxane) using a difference in etching speed according to the crystal plane without using an isotropic wet etching process having problems in terms of reliability (FIG. 3Q) Was used.

As noted earlier, in order to increase sensitivity, the current at the tip of the probe is much smaller than the resistance at the bottom. For this purpose, instead of using the depletion type probe like the conventional device, a probe using an incremental type was manufactured. It also reduces the resistance of the source and drain regions, eliminates the possibility of punch-through current, and maintains a pyramid shape for better sensing of charge as well as writing to ferroelectric materials.

3A to 3Q, a method of manufacturing an increased semiconductor probe using sidewall regions and anisotropic wet etching according to the present invention will be described in detail.

First, as shown in FIG. 3A, the first etching mask layer 110, the second etching mask layer 120, and the photoresist 130 are sequentially formed on the silicon substrate 100. In this case, the first etching mask layer 110 and the second etching mask layer 120 may be formed of a material having different etching selectivity from each other. For example, the first etching mask layer 110 may be formed of silicon oxide (SiO ₂ ), and the second etching mask layer 120 may be formed of silicon nitride (SiNx). The reason why the mask is formed of silicon oxide (SiO ₂ ) and nitride (SiNx) is because the etch ratio with silicon is very good with respect to the KOH and TMAH solutions commonly used in the anisotropic etching to be performed by the two materials. to be.

3B, the photoresist 130 is patterned by performing exposure, development, and etching processes using a mask (not shown).

Next, as shown in FIG. 3C, the second etch mask layer 120 is etched through the photolithography and the dry etching process using the patterned photoresist 130a as an etch mask.

Next, as shown in FIG. 3D, after removing the photoresist 130a, nitride is stacked on the sidewall of the second etching mask layer 120a to form a space layer 140.

Next, as shown in FIG. 3E, after removing the second etching mask layer 120a, the first etching mask layer 110 is etched using the space layer 140 as an etching mask.

Subsequently, when the space layer 140 is removed, a first etching mask pattern layer 110a is formed on the silicon (Si) substrate 100 as shown in FIG. 3F.

Next, after the nitride is deposited on the first etching mask pattern layer 110a formed on the silicon substrate 100, a sidewall region (on both sides of the first etching mask pattern layer 110a) may be subjected to an etching process. 150) (see FIG. 3G).

Next, as shown in FIG. 3H, the silicon substrate 100 is anisotropically etched by a dry or wet process using the sidewall regions 150 formed on both sides of the first etch mask pattern layer 110a. Form both slopes of the probe.

Next, as shown in FIG. 3I, impurities of an appropriate concentration are implanted into the exposed silicon substrate 100b by using the sidewall region 150 as a mask to expose a deep source and drain region 160 ( 170).

Next, as shown in FIG. 3J, the sidewall region 150 formed of the nitride is removed and then exposed to the exposed silicon substrate 100b using the first etching mask pattern layer 110a as a mask. Impurities of appropriate concentration are implanted to form shallow source and drain regions 180 and 190 on both slopes of the semiconductor probe.

On the other hand, Figures 3k to 3v shows a cross section of the process for forming a pyramid-shaped probe tip in the width direction. At this time, since anisotropic etching is already performed, it is difficult to apply the pyramid shape by applying it in another direction again, thereby forming a pyramid-shaped probe tip shape by the following HSQ transcription method.

First, as shown in FIG. 3K, after removing the first etching mask pattern layer 110a, the third etching mask layer 210 and the fourth etching mask layer on the silicon substrate 100c as shown in FIG. 3L. 220 and the photosensitive agent 230 are sequentially formed.

In this case, the third etching mask layer 210 and the fourth etching mask layer 220 is preferably formed of a material having a different etching selectivity from each other as before. For example, the third etching mask layer 210 may be formed of silicon oxide (SiO ₂ ), and the fourth etching mask layer 220 may be formed of silicon nitride (SiNx). The reason why the mask is formed of silicon oxide (SiO ₂ ) and nitride (SiNx) is because the etch ratio with silicon is very good with respect to the KOH and TMAH solutions commonly used in the anisotropic etching to be performed by the two materials. to be.

Next, FIG. 3M shows a cross-sectional view of the semiconductor probe viewed from the direction A shown in FIG. 3L.

Next, as shown in FIG. 3N, the photoresist 230 is patterned by performing an exposure, development, and etching process using a mask (not shown), and then the patterned photoresist ( The fourth etching mask layer 220 is etched through the photolithography and the dry etching process using 230a) as an etching mask.

Next, as shown in FIG. 3P, after the photoresist 230a is removed, nitride is deposited on the sidewall of the fourth etching mask layer 220a to form a space layer 240.

Next, as shown in FIG. 3Q, after removing the fourth etching mask layer 220a, the third etching mask layer 210 is etched using the space layer 240 as an etching mask. Subsequently, when the space layer 240 is removed, as illustrated in FIG. 3R, a third etching mask pattern layer 210a is formed on the silicon (Si) substrate 100c.

Using this method, the patterned line width can be determined from the dimension of the film thickness, so that an approximately 10 nm line pattern can be easily formed. In this case, the SiO2 ₂ pattern is formed from the thickness of the spacer film, and a line pattern generally corresponding to 20 to 30 nm can be easily formed.

Next, as shown in FIG. 3S, a hydrogen silsequioxane (HSQ) solution is deposited to sufficiently fill the third etching mask pattern layer 210a. Subsequently, the space layer (or HSQ) 250 is formed on both sides of the third etching mask pattern layer 210a and the remaining portions are removed using a mask (not shown).

Meanwhile, the space layer 250 may be used as long as the material has a good planarization characteristic and easily controls the etching selectivity with silicon (Si). The HSQ will be described by way of example because it is easy to adjust the etch selectivity with the silicon substrate even in a non-flat substrate.

Next, as shown in FIG. 3T, when the silicon (Si) substrate 100c is etched by the HSQ transfer method, the HSQ 250 having a poor etch ratio is cut like the silicon substrate 100c, and FIGS. 3U and FIG. It will take the form of a slope like 3v.

Here, the reason for using the HSQ transcription method is that it is difficult to make a pyramid shape by applying it again in another direction while anisotropic etching is already performed. To form.

4 is a view comparing the simulation results of the conventional and the present invention. As can be seen from the experimental results of FIG. 4, the sensitivity of the device was about 100 times higher than in the previous case.

S = {I (V _g = 1V)-I (V _g = 0V)} / I (V _g = 0V)

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims something to do.

As described above, according to the present invention, a method of manufacturing an increased semiconductor probe using sidewall regions and anisotropic wet etching, and an information storage device using the same, reduce the influence of process variables on the performance of devices, and The reliability of the device can be increased, and the device performance can be improved by solving the factors that previously hindered the measurement sensitivity.

In addition, the present invention can produce a probe having a sufficient ON / OFF (current) ratio, thereby having an effect that can make a significant contribution to improving the sensitivity of the device.

Claims (10)

In the manufacturing method of the incremental semiconductor probe, (a) forming a first etch mask pattern for forming a tip portion in a first direction on the silicon substrate and forming sidewall regions on both sides thereof; (b) anisotropically etching the silicon substrate using the sidewall regions to form both inclined surfaces of the probe; (c) implanting impurities into the sidewall regions as a mask to form source and drain regions on the silicon substrate and then removing the sidewall regions; (d) forming source and drain regions on both inclined surfaces of the probe by using the first etch mask pattern as a mask, and then removing the first etch mask pattern; (e) forming a second etching mask pattern on the tip of the probe to form a tip of the probe in a second direction; (f) forming space layers on both sides of the second etching mask pattern; And (g) etching the silicon substrate to a predetermined depth by a photo and etching process using the space film and then removing the space film. The method of claim 1, The method of forming the first etching mask pattern in the step (a): (a1) sequentially depositing a first etching mask layer, a second etching mask layer, and a photosensitive agent on the silicon substrate; (a2) etching the second etching mask layer through the photolithography and etching process after patterning the photoresist; (a3) forming a space film on sidewalls of the second etch mask layer after removing the photoresist; (a4) etching the first etch mask layer using the space layer after removing the second etch mask layer; And (a5) removing the space layer to form the first etch mask pattern. The method of claim 2, The method of claim 1, wherein the first etching mask layer and the second etching mask layer are formed of materials having different etching selectivity. The method of claim 3, wherein The first etching mask layer is formed of silicon oxide (SiO ₂ ), And the second etching mask layer is formed of nitride (SiNx). The method of claim 1, The method of forming the second etching mask pattern in the step (e) is: (e1) sequentially depositing a third etching mask layer, a fourth etching mask layer, and a photosensitive agent on the silicon substrate; (e2) etching the fourth etch mask layer through a photolithography and an etching process after patterning the photoresist; (e3) forming a space film on sidewalls of the fourth etch mask layer after removing the photoresist; (e4) etching the third etch mask layer using the space layer after removing the fourth etch mask layer; And (e5) removing the space film to form the second etching mask pattern. The method of claim 5, wherein And the third etching mask layer and the fourth etching mask layer are formed of a material having different etching selectivity from each other. The method of claim 6, The third etching mask layer is formed of silicon oxide (SiO ₂ ), And the fourth etching mask layer is formed of nitride (SiNx). The sidewall area of claim 1, wherein the sidewall area in (a) is: Method for producing an increased semiconductor probe, characterized in that formed using a nitride (SiNx). The method of claim 1, wherein the space film in step (f) is: Method for producing an increased semiconductor probe characterized in that it is formed using a hydrogen silsequioxane (HSQ). An information storage device having an incremental semiconductor probe, An information storage device having an increased semiconductor probe, which is manufactured by the method according to any one of claims 1 to 9.

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