KR100842751B1 - Method of optical proximity correction on dual polysilicon gates - Google Patents

Abstract

An optical proximity correction method for a dual polysilicon gate is provided to enhance performance of a semiconductor device by controlling line widths of gates of transistors accurately irrespective of the type of MOS transistors. A layout of first gates(310) for PMOS transistor and a layout of second gates(330) for NMOS transistor are designed. First etch biases are measured according to line widths of the first gates in an etch process for the first gates. Second etch biases are measured according to line widths of the second gates in an etch process for the second gates. Etch biases for first and second gates are extracted from the line widths and the first and second etch biases. Line control widths(313,333) are extracted to compensate the extracted etch biases. The line widths are re-adjusted by adding the line widths to the layouts of the first and second gates. An optical proximity correction process for the layouts of the re-adjusted first and second gates is performed.

Description

Method of optical proximity correction on dual polysilicon gates}

1 is a cross-sectional view schematically illustrating a conventional method for forming dual polysilicon gates.

FIG. 2 is a flowchart schematically showing an optical proximity effect correction (OPC) method for a dual polysilicon gate according to an exemplary embodiment of the present invention.

3 is a schematic diagram for explaining an original layout of a dual polysilicon gate according to an embodiment of the present invention.

4 and 5 are graphs of the results of measuring the etch bias for the dual polysilicon gate according to the embodiment of the present invention.

FIG. 6 is a view showing a result layout in which an etching bias is reflected in an original layout of a dual polysilicon gate according to an exemplary embodiment of the present invention.

7 is a cross-sectional view for explaining the effect of the optical proximity effect correction method for a dual polysilicon gate according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device fabrication, and in particular, to an optical proximity correction (OPC) method for dual polysilicon gates.

As the degree of integration of semiconductor devices increases, the reduction of design rules is rapidly occurring. Accordingly, the distortion phenomenon during the transfer of the pattern is severed due to the limitation of the resolution in the lithography process for forming the pattern. Accordingly, resolution enhancement techniques (RET) have been proposed to increase resolution, such as a technique for correcting optical proximity effects (OPC) as a method of overcoming the limitations of the lithography process.

This OPC method includes performing a process of OPC modification of a designed pattern layout, and using a simulation model to identify and recalibrate how a design pattern layout modified by OPC will be implemented on an actual wafer. It is becoming. Simulation models are modeled, including formulas describing how the designed pattern layout is transferred onto a wafer and implemented.

Meanwhile, in order to improve performance of a semiconductor device, a dual polysilicon gate is adopted in which a gate of a transistor constituting a DRAM memory device is applied differently according to MOS characteristics of the transistor. That is, an N-type polysilicon gate doped with an N-type dopant is applied to an NMOS transistor, and a P-type polysilicon gate doped with a P-type dopant is applied to a PMOS transistor.

However, in the process of forming the dual polysilicon gate, different line width differences may occur between gates to which the same critical dimension (CD) size and design duty are applied. The line width difference between the gates may be generated as a difference in etching bias is caused between the N-type polysilicon gate and the P-type polysilicon gate for NMOS. However, even if the OPC process is applied to the gate layout designed in the process of forming the dual polysilicon gate, the distinction is not clear for the different types of MOS transistors, and thus the distinction is made for the different types of MOS transistors. This makes model simulation difficult.

1 is a cross-sectional view schematically illustrating a conventional method for forming dual polysilicon gates.

Referring to FIG. 1, a gate dielectric layer 20 is formed on a semiconductor substrate 10, and a first gate 31 for a PMOS and a second gate 33 for an NMOS are formed on the gate dielectric layer 20. do. In this case, after designing and OPC gate layouts for the first and second gates 31 and 33, pattern transfer is performed on a layer of photoresist applied on the layer for the gate to perform photo transfer. The resist patterns 41 and 43 are formed.

In this case, when the line widths of the first and second gates 31 and 33 are designed to have substantially the same line widths and rules on the gate layout, the first and second gates for the PMOS formed by the pattern transfer process including exposure and development processes, etc. The first photoresist pattern 41 formed for one gate 31 and the second photoresist pattern 43 for the second gate 33 for NMOS have substantially the same line width d1. do. Since the OPC for the designed gate layout is difficult to perform by dividing the type of transistor, it is adjusted to induce the same line width d1 for the gate without substantially distinguishing the MOS type. Therefore, the first and second photoresist patterns 41 and 43 formed may be adjusted to have an equivalent line width d1.

However, the first and second gates 31, which are patterned by an etching process using the first and second photoresist patterns 41 and 43 as an etch mask, despite having an equivalent line width d1. , 33 may have different line widths d2 and d3. This is because the etch bias involved in the etching process is different in the polysilicon doped with the N-type dopant and the polysilicon doped with the P-type dopant. The etching bias is substantially a pattern line width after development, that is, a line width d1 of the photoresist patterns 41 and 43 and a pattern line width after etching, that is, a line width d2 of the first gate 31 or the second gate 33. It can be obtained by the difference of the line width (d3) of.

As described above, since the etching bias in the dual polysilicon gate varies depending on the MOS type, the gate widths 31 and 33 of the actual gate patterns 31 and 33 may be changed even though the line widths of the photoresist patterns 41 and 43 are uniformly adjusted or controlled through the OPC. The line width may be different for the line width of the original layout designed. Therefore, in view of the difference in gate line widths according to different MOS transistors, there is a demand for development of a method capable of suppressing such a difference and simultaneously improving the accuracy of pattern transfer by performing OPC.

The technical problem to be achieved by the present invention is to provide a method of correcting the optical proximity effect for a dual polysilicon gate that suppresses the difference in gate line width according to different types of MOS transistors.

One aspect of the present invention for the above technical problem is the step of designing the layout of the first gate for the PMOS transistor and the second gate for the NMOS transistor, each of the first and second gate Different readjustment of the linewidth (CD) size of each of the first and second gates to compensate for the otherwise accompanying etch bias, and the layout of the first and second gates of which the linewidths have been resized An optical proximity effect correction method for a dual polysilicon gate is provided.

The resizing of the line width may include adjusting the line widths so that the line widths of the second gate are larger than the line widths of the first gate.

Resizing the line width may include measuring etch biases involved in etching the test first gates for the PMOS transistor according to the line width size of the test first gates. Measuring etch biases involved in etching the test second gates for the transistor according to the line width of the test first gates, the first gate and the NMOS for the PMOS transistor Extracting respective etch biases corresponding to the linewidth sizes of the second gate for the transistor from the measurements, extracting linewidth adjustment widths to compensate for the extracted etch biases, and extracting the extracted linewidth adjustment widths from the measurements; And expanding the line width in addition to the layout of the first and second gates.

According to the present invention, it is possible to suppress the difference in the gate line widths according to different types of MOS transistors and to perform optical proximity effect correction (OPC) on the original gate layout, thereby providing dual polysilicon gates. This paper proposes a method for correcting optical proximity effects, which can achieve more effective linewidth control.

In an embodiment of the present invention, after designing a target original layout of a first gate for a PMOS transistor and a second gate for an NMOS transistor, an etch bias of an etching process performed on an actual wafer. In consideration of this, the size of the line width of the layout is resized. Subsequently, an automatic OPC is performed using an OPC model to present a technique for precisely controlling line widths of gates applied to different types of MOSs. In consideration of the etching bias, the size of the line width of the layout of the gates is readjusted, that is, enlarged in advance, so that the post-development (CD) target of the photoresist pattern performed on the wafer is set larger, and then the OPC is suited to this line width target. By performing, the size of the line width (CD) after the actual etching can be derived to match the target line width targeted in the design.

FIG. 2 is a flowchart schematically showing an optical proximity effect correction (OPC) method for a dual polysilicon gate according to an exemplary embodiment of the present invention. 3 to 7 are schematic views illustrating an optical proximity effect correction (OPC) method for a dual polysilicon gate according to an exemplary embodiment of the present invention.

Referring to FIG. 2, an optical proximity effect correction (OPC) method according to an embodiment of the present invention, as in the original layout of the dual polysilicon gates 310 and 330 shown in FIG. 3, is used for PMOS transistors. The layout of the second gate 330 for the first gate 310 and the NMOS transistor is designed (201 of FIG. 2). In this case, the first gate 310 may be set to have a first target line width 301, and the second gate 330 may be set to have a second target line width 303. The first and second target line widths 301 and 303 may be set to the same size, but may be set to different sizes in some cases.

A Design Rule Check (DRC) is performed on the designed layout to determine whether the layout matches the design rule (OK) or not good (NG). If the design rule matches the layout, OPC is performed on the layout. Before the OPC is performed, a process of resizing the line width CD of the first and second gates 310 and 330 is performed to compensate for the etching bias in the layout (204 of FIG. 1).

In order to readjust this line width, an etching bias is first checked (203 of FIG. 2). Specifically, the layout of the test first gates of various line widths for the PMOS transistor is transferred onto the test wafer to expose and develop the first test photoresist pattern, and the photoresist pattern is etched. The first test gates are formed by etching using a mask). The line width of the first test gate formed by the line width and the etching of the first test photoresist pattern is measured, and the difference in the line width of the first test gate formed by the etching with respect to the line width of the first test photoresist pattern from the measured result. Is measured by the first etching bias. The measured results can be presented as a distribution of trends as shown in the graph shown in FIG. 4.

In addition, the layout of the test second gates of various line widths for the NMOS transistor is transferred onto the test wafer to expose and develop the second test photoresist pattern, and the photoresist pattern is etch mask. Etching to form second test gates. The line width of the second test gate formed by the line width and the etching of the second test photoresist pattern is measured, and from the measured results, the difference in the line width of the second test gate formed by the etching with respect to the line width of the second test photoresist pattern is determined. Measured by the second etching bias. The measured results can be presented as a distribution of trends as shown in the graph shown in FIG. 5.

4 and 5, since the line widths of the etched gates are reduced compared to the line widths of the photoresist patterns, the etching biases may be extracted as negative values. At this time, the second etching bias value for the NMOS tends to be further reduced to a larger size than the first etching bias value for the PMOS. For example, the second etching bias tends to have a negative value about 7 nm more on average than the first etching bias. Due to the difference in the etching bias, the OPC result without considering the etching bias may be different from the actual line width of the gate formed by etching on the actual wafer.

In order to compensate for the deviation of the OPC result due to the etching bias, in the embodiment of the present invention, the process of re-adjusting the line width (CD) size of the first and second gates (310, 330 of FIG. 3) (Fig. 1, 204). The line width readjustment process may identify and extract the etch biases corresponding to the line widths CD of the first and second gates 310 and 330 from the measurement results of the measured etching biases shown in FIGS. 4 and 5 ( 204 of FIG. 2). Thereafter, after extracting the linewidth adjustment widths to compensate for the extracted etching biases, as shown in FIG. 6, the extracted linewidth adjustment widths 313 and 333 are added to the layout of the first and second gates 310 and 330. The linewidth is resized to expand the linewidth (204 in FIG. 1).

For example, on average, the etch bias for the gate is approximately -17.9 nm from the measurements presented in FIG. 5 for NMOS, and the etch bias is approximately -10.7 nm from the measurements shown in FIG. 4 for PMOS. It is measured by. Accordingly, the first line width adjusting width 313 to be added to the first gate 310 may be set to a value that is about 7 nm smaller than the second line width adjusting width 333. For example, if the first gate 310 is designed to be approximately 170 nm line width CD, the first line width adjustment width 313 may be given at approximately 5 nm in each direction to compensate for the corresponding etching bias of approximately -10 nm. If the second gate 330 is designed to be approximately 170 nm line width, the second line width adjusting width 333 may be given at 9 nm in each direction in order to compensate for the corresponding etching bias of approximately −18 nm.

As shown in FIG. 6, the first and second line width adjusting widths 313 and 333 are applied to the first and second gates 310 and 330 for the PMOS and the NMOS, respectively, in consideration of the etching bias, thereby increasing the line width. The readjusted layouts of the first gate 311 and the second gate 331 are obtained. The first and second gates of which the line width readjusted first and second gates 311 and 331 are converted into data that can be computed by a computing device such as a computer, for example, GDS data, are converted into the first and second gates. OPC is performed using the layout data of (311, 331) (206 in FIG. 2).

The OPC process may be performed using a model that simulates a pattern transfer process, for example, a photoresist exposure and development process. To this end, first, the simulation model is identified and calibrated so that the simulation model is matched to the conditions for the exposure and development process to be used in practice (205 of FIG. 2). Subsequently, layout data of the first and second gates 311 and 331 are input to the model identified through calibration, and simulation is performed. The OPC is performed on the layout using the simulation result.

With respect to the resultant layout in which such OPC is performed, a check on the design rule, that is, a post-OPC rule check (ORC) is performed to confirm whether the OPC layout matches the design rule (207 of FIG. 2). ). Thereafter, a photomask is fabricated using the OPC layout, and the photoresist layer is exposed and developed using the fabricated photomask. Accordingly, as shown in FIG. 7, the first photoresist pattern 741 for the PMOS transistor and the second photoresist pattern 743 for the NMOS transistor are formed on the semiconductor substrate 710. Since the first and second photoresist patterns 741 and 743 are formed according to the OPC result of the layout of the first and second gates 311 and 331 whose line widths are readjusted as shown in FIG. It may be formed to have a different line width (d4) and line width (d5).

Thereafter, the first and second photoresist patterns 741 and 743 of FIG. 7 are selectively etched using an etching mask to form a layer for a gate formed on the lower gate dielectric layer 710. Accordingly, the first gate 731 for the PMOS and the second gate 733 for the NMOS are patterned. In this etching process, the etching biases accompanying the etching of the first gate 731 and the second gate 733 may be different from each other as shown in the measurement results of FIGS. 4 and 5. That is, the extent to which the line width d6 of the first gate 731 decreases with respect to the line width d4 of the first photoresist pattern 741 is the second gate with respect to the line width d5 of the second photoresist pattern 743. The extent to which line width d7 of 733 is reduced may be smaller. Nevertheless, the difference in the etching biases is reflected through the line width readjustment as shown in FIG. 6 before the OPC process, and thus the line widths d6 and d7 of the first gate 731 and the second gate 733 actually formed. ) Can each match the target line width (CD). For example, when the first and second gates 310 and 330 of FIG. 3 are set to the same line widths 301 and 303 in the target layout design, the line widths d6 of the second gates 731 and 733 that are actually formed. , d7) will have an equivalent size.

As described above, in the exemplary embodiment of the present invention, when the gates for the NMOS and the PMOS are formed as a dual polysilicon gate structure in which different dopants are doped with a polysilicon layer, the gate is formed on the actual wafer according to the difference in the etching bias. The difference in line width can be suppressed. Thus, more accurate gate line width control is possible.

According to the present invention described above, when the dual polysilicon gate structure is adopted, the line width of the gates of transistors having the same size or duty can be accurately controlled through the OPC regardless of the MOS type. Accordingly, performance improvement of the semiconductor device can be realized.

In the above, the present invention has been described in detail through specific examples, but the present invention is not to be construed as being limited thereto, but is interpreted as being provided to those skilled in the art to more fully describe the present invention. It is desirable to be. It is to be understood that the present invention may be modified or improved by those skilled in the art within the technical spirit of the present invention.

Claims (3)

Designing a layout of a first gate for a PMOS transistor and a second gate for an NMOS transistor; Measuring first etch biases involved in etching the test first gates of the PMOS transistor by the line width of the test first gates; Measuring second etch biases involved in etching the test second gates for the NMOS transistor by the line width of the test second gates; Extracting etch biases to be involved in the first gate for the PMOS transistor and the second gate for the NMOS transistor from the measured linewidth sizes and first and second etch biases ; Extracting linewidth adjustment widths to compensate for the extracted etch biases; Re-adjusting the line width (CD) size of each of the first and second gates by adding the extracted line width adjustment widths to the layout of the first and second gates; And Optical proximity effect correction (OPC) for the layout of the first and second gates whose linewidths have been resized. The method of claim 1, Resizing the line width And re-adjusting the line width so that the line width of the second gate is larger than the line width of the first gate. delete

Images