KR100841118B1 - Plasma processing apparatus and plasma processing method - Google Patents

Abstract

The spatial distribution of the density of plasma generated by the capacitively coupled high frequency discharge is uniformized or arbitrarily controlled to improve in-plane uniformity of the process. The substrate W to be processed is mounted on the susceptor 16 of the lower electrode, and a high frequency for plasma generation is applied from the high frequency power supply 30. The upper electrode 34 disposed to face the susceptor 16 in parallel with the upper side of the susceptor 16 is attached to the chamber 10 in an electrically floating state via a ring-shaped insulator 35. In addition, a gap having a predetermined gap size is provided between the upper surface of the upper electrode 34 and the ceiling of the chamber 10, and a vacuum space 50 is formed in part or all of the gap. All or part of the inner wall of the vacuum space 510 is covered with a sheet-shaped insulator 52.

Description

Plasma processing apparatus and plasma processing method {PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD}

1 is a longitudinal cross-sectional view showing the configuration of a plasma etching apparatus according to an embodiment of the present invention.

2 is a longitudinal sectional view showing a configuration of a plasma etching apparatus according to a modification of the embodiment.

It is a figure which shows typically the structure of the capacitively coupled high frequency discharge in the plasma etching apparatus of a comparative example.

It is a figure which shows typically the structure of the capacitively coupled high frequency discharge in the plasma etching apparatus of an Example.

FIG. 5 is a diagram showing a comparison of the spatial distribution characteristics of electron density when the ground capacitance of the upper electrode is selected into two types of high capacitance and low capacitance in the plasma etching apparatus of the embodiment.

FIG. 6 is a diagram showing a comparison of in-plane distribution characteristics of an etching rate of an oxide film in the case where the ground capacitance of the upper electrode is selected from the high capacitance and the low capacitance in the plasma etching apparatus of the embodiment.

FIG. 7 is a diagram showing comparisons of in-plane distribution characteristics of the etching rate of a photoresist when the ground capacitance of the upper electrode is selected from two types of high capacitance and low capacitance in the plasma etching apparatus of the embodiment.

8 is a longitudinal sectional view showing a configuration of a plasma etching apparatus according to a modification of the embodiment.

FIG. 9 is a diagram schematically showing a structure of a capacitively coupled high frequency discharge in the plasma etching apparatus of FIG. 8.

10 is a longitudinal sectional view showing a configuration of a plasma etching apparatus according to a modification of the embodiment.

FIG. 11 is a diagram schematically showing a structure of a capacitively coupled high frequency discharge in the plasma etching apparatus of FIG. 10.

12 is a partial cross-sectional view showing one embodiment of the capacitance varying portion in the plasma etching apparatus of the embodiment.

13 is a partial cross-sectional view showing another embodiment of the capacitance varying portion in the plasma etching apparatus of the embodiment.

14 is a partial cross-sectional view showing another embodiment of the capacitance varying portion in the plasma etching apparatus of the embodiment.

It is a longitudinal cross-sectional view which shows the structure of the plasma etching apparatus by a modification of the Example.

16 is a longitudinal cross-sectional view showing a configuration of a plasma etching apparatus according to a modification of the embodiment.

Explanation of symbols for the main parts of the drawings

10: chamber (processing vessel)

16: susceptor (lower electrode)

30: high frequency power supply

34 upper electrode

34A: inner upper electrode

34B: outer top electrode

35: ring-shaped insulator

36: electrode plate

36a: gas jet hole

38: electrode support

40: gas buffer chamber

42: gas supply pipe

44: process gas source

50: vacuum space

52: insulator

64: high frequency power supply

70, 72: capacitance

73: insulator

74, 76: ring shaped insulator

80, 82, 84: capacitance

86, 92: variable capacitance

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for performing plasma processing on a substrate to be processed, and more particularly, to a capacitively coupled plasma processing apparatus and a plasma processing method.

In processes such as etching, deposition, oxidation, sputtering, etc. in the manufacturing process of a semiconductor device or a flat panel display (FPD), plasma is frequently used to perform a good reaction at a relatively low temperature to a processing gas. Background Art Conventionally, among single-piece plasma processing apparatuses, particularly plasma etching apparatuses, capacitively coupled plasma processing apparatuses have become mainstream.

In general, a capacitively coupled plasma processing apparatus arranges an upper electrode and a lower electrode in parallel in a processing container configured as a vacuum chamber, and mounts a substrate to be processed (semiconductor wafer, glass substrate, etc.) on the lower electrode. A high frequency voltage is applied to either of the electrodes. Due to this high frequency voltage, electrons are accelerated by the electric field formed between the two electrodes, and plasma is generated by collision ionization of the electrons and the processing gas, and desired processing (for example, etching process) is performed on the substrate surface by radicals or ions in the plasma. ) Is carried out. Here, since the electrode on the side to which high frequency is applied is connected to a high frequency power supply via a blocking capacitor in the matching unit, it acts as a cathode (cathode). The cathode coupling method, in which a high frequency is applied to a lower electrode supporting a substrate to form a cathode, is anisotropically excellent in directionality by introducing ions in a plasma almost perpendicularly to a substrate using a magnetic bias voltage generated at the lower electrode. Etching is enabled (for example, refer patent document 1).

(Patent Document 1) Japanese Patent Application Laid-Open No. 6-283474

In the conventional capacitively coupled plasma processing apparatus, the electrode on the anode side to which the high frequency is not applied is generally grounded. Usually, since the processing container is made of metal such as aluminum or stainless steel and is securely grounded, the electrode of the anode can be brought to ground potential through the processing container. For this reason, in the cathode coupling method, the structure which makes the upper electrode which is an anode electrode directly attach to the ceiling of a process container, and makes it integral, or takes the structure which uses the ceiling of a process container as an upper electrode as it is.

However, with the recent refinement of design rules in semiconductor manufacturing processes, high-density plasma is required under low pressure, and in the capacitively coupled plasma processing apparatus as described above, the frequency of the high frequency is increasing. High frequency of 40 MHz or more is used. However, when the frequency of the high frequency is high, the high frequency current is collected at the center of the electrode, so that the density of the plasma generated in the processing space between both electrodes is also higher than that of the electrode edge, and the in-plane uniformity of the process is lowered. The problem to say becomes remarkable.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in the capacitively coupled type, the in-plane uniformity of the process is improved by uniformizing or arbitrarily controlling the spatial distribution of the plasma density generated by applying a high frequency between two opposite electrodes. It is an object of the present invention to provide a plasma processing apparatus and a plasma processing method.

In order to achieve the above object, the plasma processing apparatus of the present invention includes a processing container capable of vacuum evacuation, a first electrode attached to the processing container in an electrically floating state through an insulator or a space, and the processing A second electrode disposed parallel to the first electrode at a predetermined interval in the container, the second electrode facing the first electrode and supporting the substrate to be processed; the first electrode, the second electrode, and a sidewall of the processing container; And a processing gas supply unit for supplying a desired processing gas in the processing space between and a first high frequency feeding unit for applying a first high frequency to the second electrode to generate plasma of the processing gas in the processing space, The first electrode and the processing vessel to obtain desired plasma density distribution characteristics for the plasma generated in the processing space. And it sets the capacitance between.

In the plasma processing method of the present invention, the first electrode and the second electrode are disposed in parallel in the processing container capable of vacuum evacuation at predetermined intervals, and are opposed to the first electrode so that the substrate to be treated is replaced with the second electrode. And evacuating the inside of the processing container at a predetermined pressure, supplying a desired processing gas to the processing space between the first electrode, the second electrode, and the sidewall of the processing container, and providing the second electrode to the second electrode. 1. A plasma processing method for generating a plasma of the processing gas in the processing space by applying high frequency, and performing a desired plasma processing on the substrate under the plasma, wherein the first electrode is electrically connected to the processing container via an insulator. By floating the desired plasma density distribution characteristics with respect to the plasma generated in the processing space. So that the sets of the capacitance between the first electrode and the process vessel.

In the capacitive coupling type which this invention takes, when the high frequency from a high frequency power supply is applied to a 2nd electrode, the high frequency discharge between a 2nd electrode and a 1st electrode, and between the 2nd electrode and the side wall (inner wall) of a processing container Plasma of the processing gas is generated in the processing space by the high frequency discharge, and the generated plasma diffuses in all directions, especially upward and radial directions outward, and the electron current in the plasma passes to the ground through the first electrode, the processing vessel sidewall, or the like. Flow. Here, since the first electrode is attached to the processing vessel in an electrically floating state through the insulator or the space according to the present invention, the impedance of the capacitance is added between the first electrode and the ground potential when viewed from the second electrode. Becomes By setting the capacitance around the first electrode to an appropriate value, it is possible to uniformize or arbitrarily control the spatial distribution characteristic of the density of plasma generated in the processing space in the radial direction.

The value which is preferable as an electrostatic capacitance between a 1st electrode and a processing container in this invention is 5000 pF or less, More preferably, it is 2000 pF or less, You may make it low to about 250 pF. According to a preferable embodiment of the present invention, a vacuum space independent of the processing space is provided between the rear surface of the first electrode and the processing container as viewed from the second electrode. This vacuum space not only has a heat insulation action and a discharge prevention function with respect to a 1st electrode, but also provides the lowest electrostatic capacitance of relative permittivity. The structure which covers all or part of the inner wall of a vacuum space with an insulator can also be taken suitably.

In order to keep the capacitance around the first electrode as low as possible, as another preferable embodiment, it is also preferable to configure all or part of the portion of the processing container facing the rear surface of the first electrode as an insulator as viewed from the second electrode. Do.

According to a preferred embodiment of the present invention, in order to supply the processing gas to the processing space, a gas chamber is provided above or above the first electrode, and at the same time, a gas for discharging the processing gas from the gas chamber to the processing space is provided on the lower surface of the first electrode. Multiple gas ejection holes are formed. Thus, the function of a shower head can be made to the 1st electrode electrically floating in a processing container.

Moreover, as a preferable aspect of this invention, the ring-shaped insulator is provided so that the space | interval may be bridged between the outer peripheral surface of a 1st electrode, and the side wall of a processing container. This ring-shaped insulator physically holds the first electrode and forms a part of the capacitance between the first electrode and the processing container.

In one suitable form, a space is formed between the outer circumferential surface of the first electrode (upper electrode) and the side wall of the processing container. In addition, the first electrode is divided into two, a disk-shaped inner electrode and a ring-shaped outer electrode in the radial direction. In addition, a ring-shaped fourth insulator is inserted between the inner electrode and the outer electrode, or a space is formed. Alternatively, a ring-shaped fifth insulator is inserted between the outer electrode and the sidewall of the processing container, or a space is formed. It is preferable to make the capacitance between the outer electrode and the processing container larger than that between the inner electrode and the processing container.

In another preferred embodiment, the first electrode is divided into a disk-shaped inner electrode and a ring-shaped outer electrode in the radial direction so that a ring-shaped fourth insulator is inserted between the inner electrode and the outer electrode. A ring-shaped fifth insulator is inserted between the outer electrode and the side wall of the processing container. According to this structure, the ground capacitance of the inner electrode can be significantly reduced, and the effect of relatively decreasing the plasma density of the electrode center portion and relatively increasing the plasma density of the electrode edge portion can be enhanced.

(Example)

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 shows a configuration of a plasma processing apparatus in an embodiment of the present invention. This plasma processing apparatus is constituted as a capacitively coupled (parallel flat type) plasma etching apparatus of a cathode couple, and has a cylindrical vacuum chamber (processing container) 10 formed of, for example, aluminum having anodized (anodic oxidation) surface. Has) Chamber 10 is securely grounded.

At the bottom of the chamber 10, a circumferential susceptor support 14 is arranged via an insulating plate 12 such as ceramic, and a susceptor 16 made of aluminum, for example, is provided on the susceptor support 14. It is prepared. The susceptor 16 constitutes a lower electrode, on which a semiconductor wafer W is mounted, for example, as a substrate to be processed.

An upper surface of the susceptor 16 is provided with an electrostatic chuck 18 for holding the semiconductor wafer W with an electrostatic attraction force. The electrostatic chuck 18 sandwiches an electrode 20 made of a conductive film between a pair of insulating layers or insulating sheets, and a DC power supply 22 is electrically connected to the electrode 20. By the DC voltage from the DC power supply 22, the semiconductor wafer W can be adsorbed and held by the electrostatic chuck 18 by the coulomb force. On the upper surface of the susceptor 16 around the electrostatic chuck 18, a focus ring 24 made of, for example, silicon for improving the uniformity of etching is disposed. On the side surfaces of the susceptor 16 and the susceptor support 14, a cylindrical inner wall member 25 made of, for example, quartz is attached.

Inside the susceptor support 14, a coolant chamber 26 extending in the circumferential direction, for example, is provided. The refrigerant chamber 26 is circulated and supplied with a coolant, for example, a predetermined temperature, from a tiller unit (not shown) attached to the outside via pipes 27a and 27b. The processing temperature of the semiconductor wafer W on the susceptor 16 can be controlled by the temperature of the refrigerant. In addition, a heat conduction gas such as He gas from a heat conduction gas supply mechanism (not shown) is supplied between the upper surface of the electrostatic chuck 18 and the rear surface of the semiconductor wafer W via the gas supply line 28.

The susceptor 16 is electrically connected to the high frequency power supply 30 for plasma generation through the matching unit 32 and the power feeding rod 33. The high frequency power supply 30 applies a predetermined high frequency, for example, a high frequency of 40 MHz, to the susceptor 16 when performing plasma processing in the chamber 10.

The upper electrode 34 is provided above the susceptor 16 in parallel with the susceptor. The upper electrode 34 supports the electrode plate 36 made of a semiconductor material such as Si or SiC having a plurality of gas ejection holes 36a and the electrode plate 36 so as to be mountable and detachable. The conductive material, for example, is composed of an electrode support 38 made of anodized aluminum, and is attached to the chamber 10 in an electrically floating state via a ring-shaped insulator 35. Plasma generating spaces or processing spaces PS are formed on the sidewalls of the upper electrode 34, the susceptor 16, and the chamber 10. The ring-shaped insulator 35 is made of, for example, alumina (Al ₂ O ₃ ), and is attached to fill the gap between the outer circumferential surface of the upper electrode 34 and the side wall of the chamber 10 in an airtight manner, and the upper electrode 34 ) Is physically supported and forms a part of the capacitance between the upper electrode 34 and the chamber 10.

The electrode support 38 has a gas buffer chamber 40 therein, and a plurality of gas reservoirs communicating from the gas buffer chamber 40 to the gas ejection hole 36a of the electrode plate 36 on the lower surface thereof. Has (38a) The processing gas supply source 44 is connected to the gas buffer chamber 40 via the gas supply pipe 42, and the mass flow controller (MFC) 46 and the opening / closing valve 48 are provided in the gas supply pipe 42. When a predetermined processing gas is introduced into the gas buffer chamber 42 from the processing gas supply source 44, the processing space is directed from the gas blowing hole 36a of the electrode plate 36 toward the semiconductor wafer W on the susceptor 16. The processing gas is blown into the shower in the PS. like this. The upper electrode 34 also serves as a shower head for supplying a processing gas to the processing space PS.

In addition, a passage (not shown) through which a coolant, for example, coolant, flows is provided inside the electrode support 38, and the entire upper electrode 34, in particular, the electrode plate 36, is opened by the external tiller unit through the coolant. The temperature is adjusted to a predetermined temperature. In addition, in order to further stabilize the temperature control of the upper electrode 34, a configuration (for example, a heater not shown) made of, for example, a resistance heating element may be attached to the inside or the upper surface of the electrode support 38.

A gap having a predetermined gap size is provided between the upper surface of the upper electrode 34 and the ceiling of the chamber 10, and a vacuum space 50 is formed in part or all of the gap. This vacuum space 50 not only thermally cuts off the upper electrode 34 from the chamber 10 to the ambient temperature, but also discharges between the upper electrode 34 and the chamber 10 by excluding gas. Also, since the relative dielectric constant of vacuum is 1, it also has a function of making the capacitance between the upper electrode 34 and the chamber 10 as small as possible. In addition, the vacuum space 50 is evacuated separately from the processing space PS, and maintains a vacuum state by the airtight structure. In this embodiment, in order to further improve the discharge prevention function, all or part of the inner wall of the vacuum space 50 (only the upper surface in the example shown) is covered with the sheet-shaped insulator 52. Although the polyimide resin excellent in heat resistance can be used suitably for this insulator 52, Teflon (registered trademark), quartz, etc. may be sufficient.

The ring-shaped space formed between the susceptor 16 and the susceptor support 14 and the side wall of the chamber 10 is an exhaust space, and the exhaust port 54 of the chamber 10 is located at the bottom of the exhaust space. Is provided. An exhaust device 58 is connected to the exhaust port 54 via an exhaust pipe 56. The exhaust device 58 has a vacuum pump such as a turbomolecular pump, and is capable of depressurizing the interior of the chamber 10, in particular the processing space PS, to a desired degree of vacuum. In addition, a gate valve 62 is attached to the sidewall of the chamber 10 to open and close the carrying in and out of the semiconductor wafer W. As shown in FIG.

In this plasma etching apparatus, in order to perform etching, first, the semiconductor wafer W to be processed is brought into the chamber 10 with the gate valve 62 open, and mounted on the electrostatic chuck 18. . Then, a processing gas, that is, an etching gas (generally a mixed gas), is introduced into the chamber 10 from the processing gas supply source 44 at a predetermined flow rate and flow rate ratio, and the vacuum exhaust path of the chamber 10 by the exhaust device 58 is introduced. Set the pressure to the set value. In addition, a high frequency (40 MHz) is applied to the susceptor 16 with a predetermined power from the high frequency power supply 30. In addition, a DC voltage is applied from the DC power supply 22 to the electrode 20 of the electrostatic chuck 18 to fix the semiconductor wafer W on the electrostatic chuck 18. The etching gas discharged from the shower head of the upper electrode 34 is plasma-formed by high frequency discharge in the processing space PS, and the main surface of the semiconductor wafer W is formed by radicals or ions generated by this plasma. Is etched.

In this capacitively coupled plasma etching apparatus, a high frequency of 40 MHz or more is applied to the susceptor (lower electrode) 16 to densify the plasma to a desired dissociation state, thereby forming a high density plasma even under a lower pressure condition. can do. Further, in the cathode coupling method, the anisotropic etching can be performed by drawing ions in the plasma almost perpendicularly to the wafer W using the self bias voltage generated in the susceptor 16.

In addition, a lower two frequency superimposition application method in which a relatively high frequency (e.g., 40 MHz) suitable for plasma generation and a relatively low frequency (e.g. 2 MHz) suitable for ion implantation are applied to the lower electrode in a superimposed manner. It is possible. As an apparatus structure in this case, as shown in FIG. 2, what is necessary is just to add the high frequency power supply 64, the matching device 66, and the power supply rod 68 for supplying the 2nd high frequency to the susceptor 16. FIG. In such a lower two-frequency superposition method, the density of the plasma generated in the processing space PS is optimized by the first high frequency (40 MHz), and a self bias voltage or ion sheath generated in the susceptor 16 is generated. The sheath can be optimized by the second high frequency (2 MHz), so that anisotropic etching with higher selectivity is possible.

Next, the characteristic of this invention in this plasma etching apparatus is demonstrated in detail. As described above, the plasma etching apparatus attaches the upper electrode 34 to the chamber 10 electrically in a cathode coupled manner via the ring-shaped insulator 35 and the upper vacuum space 50. Doing.

First, as a comparative example, the operation in the case where the upper electrode 34 is directly attached to the chamber 10 and set to the ground potential is described. In this case, when the high frequency from the high frequency power supply 30 is applied to the susceptor 16 as shown in FIG. 3, the high frequency discharge and the susceptor 16 between the susceptor 16 and the upper electrode 34 are performed. ) And plasma of the processing gas is generated in the processing space PS by the high frequency discharge between the side walls of the chamber 10. The generated plasma diffuses in all directions, particularly upward and radially outward, and the electron current in the plasma flows through the upper electrode 34 or the side wall of the chamber 10 to the ground. Here, in the susceptor 16, as the frequency of the high frequency increases, high frequency current tends to collect in the center of the susceptor due to the skin effect. In addition, in the side wall of the upper electrode 34 and the chamber 10 at the same potential (ground potential) as seen from the susceptor 16, since the former is closer to the distance than the latter, more high frequency in the center of the electrode is obtained. Power is emitted towards the processing space PS. For this reason, the ratio which flows to the side wall of the chamber 10 among the electron currents in a plasma is very low, and most flows to the upper electrode 34 especially the center part. As a result, the spatial distribution characteristic of the plasma density is not only the highest in the electrode center but also markedly shows the difference in the electrode edge portion.

In contrast, when the upper electrode 34 is attached to the chamber 10 in a floating state as in this embodiment, as shown in FIG. 4, the plasma distribution in the processing space PS extends outward in the radial direction. In FIG. 4, the upper electrode 34 is electrically connected to the chamber 10 via capacitances 70 and 72. Here, the capacitance 70 is an electrostatic capacitance between the upper electrode 34 and the side wall of the chamber 10, and is mainly formed by the ring-shaped insulator 35. On the other hand, the capacitance 72 is the capacitance between the upper electrode 34 and the ceiling of the chamber 10, and is mainly formed by the vacuum space 50 and the insulator 52.

Also in this case, when a high frequency is applied from the high frequency power supply 30 to the susceptor 16, the high frequency discharge between the susceptor 16 and the upper electrode 34 and the sidewalls of the susceptor 16 and the chamber 10. The plasma of the etching gas is generated in the processing space PS by the high frequency discharge in between. The generated plasma diffuses upward and radially outward, and the electron current in the plasma flows through the upper electrode 34 or the side wall of the chamber 10 to the ground. In the susceptor 16, a high frequency current tends to collect in the center of the susceptor, and the upper electrode 34 is located closer to the upper electrode 34 than the side wall of the chamber 10 when viewed from the susceptor 16. same. However, the impedance of the capacitances 70 and 72 is added between the upper electrode 34 and the ground potential, so that even if a high frequency current is collected in the center of the susceptor 12, the upper electrode 34 directly thereon. It becomes difficult to flow. For this reason, the ratio which flows to the side wall of the chamber 10 among the electron current in plasma PS is never low. In theory, depending on the value of the capacitance (capacitance) of the capacitances 70 and 72, somehow between the susceptor 16 and the upper electrode 34 and between the susceptor 16 and the side wall of the chamber 10. The ratio of the flowing electron currents can be controlled. Therefore, the uniformity of the spatial distribution characteristics of the plasma density in the radial direction can also be controlled arbitrarily.

5 to 7, for the etching of the SiO ₂ via hole by the plasma etching apparatus (FIG. 2) of this embodiment, the ground capacitance of the upper electrode 34, that is, capacitances 70 and 72 around the upper electrode 34 Spatial distribution characteristics of electron density Ne, and in-plane distribution of oxide film (SiO ₂ ) etching rate and photoresist (PR) etching rate when two synthesis capacities were selected: 20000 pF (high capacity) and 250 pF (low capacity). The characteristics are compared and shown. Main etching conditions are as follows.

Wafer caliber: 300 mm

Process gas: C ₄ F ₆ / C ₄ F ₈ / Ar / O ₂ = flow rate 40/20/500/60 sccm

Pressure in chamber: 30 mTorr

High Frequency Power: 40 MHz / 2 MHz = 2500/3200 W

5 to 7, when the ground capacitance of the upper electrode 34 is a high capacitance (20000 pF), the electron density Ne remains high and relatively uniform at the center of the wafer, but near the wafer edge ( Abruptly decreases in the vicinity of R = ± 120 mm). Since the etching rate of the oxide film and the etching rate of the photoresist both depend on the electron density distribution, their in-plane uniformity is not so good at ± 4.1% and ± 19.1%, respectively. On the other hand, when the ground capacitance of the upper electrode 34 is a low capacitance 250 pF, the electron density Ne decreases at the center of the wafer, while the outside of the wafer region (-150 mm to 150 mm), that is, the exhaust region, is reduced. Increasing, the difference between the wafer center and the wafer edge decreases. In this regard, the etching rate of the oxide film and the etching rate of the photoresist also decrease between the wafer center portion and the wafer edge portion. In particular, the etching rate of the oxide film is lowered only at the center portion, and the edge portion hardly decreases, and the in-plane uniformity is improved to ± 2.4%. In addition, although the etching rate of the photoresist generally increases, in-plane uniformity is greatly improved to ± 4.4%.

In this way, the electric current flowing between the susceptor 12 and the upper electrode 34 is converted by switching the capacitance or the ground capacitance around the upper electrode 34 from the high capacitance (20000 pF) to the low capacitance (250 pF). Can be reduced relatively. At the same time, the electron current flowing between the susceptor 12 and the sidewalls of the chamber 10 is relatively increased, thereby relatively decreasing the plasma density at the electrode center, thereby relatively increasing the plasma density at the electrode edge portion. Can be. As a result, the in-plane uniformity of the etching rate of an oxide film or a photoresist can be improved. In particular, the dramatic improvement in in-plane uniformity (19.1% to 4.4%) according to the etching rate of the photoresist was not possible in the prior art.

As a result of the present inventors continuing the experiment as described above, when the ground capacitance of the upper electrode 34 is 5000 pF or less, the effect of in-plane uniformity of the etching rate as described above was obtained. Moreover, when the ground capacitance of the upper electrode 34 was lowered to 2000 pF or less, it was confirmed that the practical effect in in-plane uniformity of the said etching rate can be acquired reliably.

8 and 10 show a preferred device configuration for lowering the ground capacitance of the upper electrode. In the structural example shown in FIG. 8, the insulator 73 constitutes a portion of the chamber 10 ′ opposite to the rear surface, that is, the upper surface of the upper electrode 34, or the ceiling portion. According to such a configuration, it is possible to reduce or eliminate the capacitive coupling between the back surface of the upper electrode 34 and the ceiling portion of the chamber 10 'as much as possible, and the upper electrode 34 is electrically shown in FIG. It can be set as the ground capacitance which removed substantially the capacitance 72 (FIG. 4) of (). As a result, the effect of relatively decreasing the plasma density of the electrode center portion and relatively increasing the plasma density of the electrode edge portion can be further enhanced. In addition, in the illustrated example, the ceiling portion of the chamber 10 'is all composed of the insulator 73 to minimize the capacity of the distribution or the upper capacitance 72, but the outer periphery of the ceiling portion is constituted by the conductor to form an insulator in the center ( By appropriately adjusting the area ratio of 73, the capacity of the allocation capacitance 72 may be adjusted to a desired value.

In the structural example shown in FIG. 10, the upper electrode is divided into two discs of a disk-shaped inner upper electrode 34A and a ring-shaped outer upper electrode 34B in the radial direction, and a ring is formed between the positive electrodes 34A and 34B. The inner insulator 74 having a shape is hermetically inserted, and the ring-shaped outer insulator 76 is hermetically inserted between the outer upper electrode 34B and the side wall of the chamber 10. The material of the two ring insulators 74 and 76 is preferably quartz having a small dielectric constant, but may be ceramic, alumina (Al ₂ O ₃ ), or the like. In addition, a space may be formed instead of the two ring insulators 74 and 76. A space 78 communicating with the atmosphere is provided between the upper electrodes 34A and 34B and the ceiling of the chamber 10.

In this apparatus configuration, both upper electrodes 34A and 34B are electrically floating. As shown in FIG. 11, a capacitance 80 exists between the inner upper electrode 34A and the chamber 10, and a capacitance 82 exists between the outer upper electrode 34B and the chamber 10. The capacitance 84 exists between the inner upper electrode 34A and the outer upper electrode 34B. Here, the capacitance 80 is mainly formed by the space 78, the capacitance 82 is mainly formed by the outer ring insulator 76, and the capacitance 84 is mainly formed by the inner ring insulator 74. Is formed.

When a high frequency is applied from the high frequency power supply 30 to the susceptor 16, the high frequency discharge between the susceptor 16 and the inner upper electrode 34A, the high frequency discharge between the susceptor 16 and the outer upper electrode 34B The plasma of the etching gas is generated in the processing space PS by the high frequency discharge between the acceptor 10 and the side wall of the chamber 10. Some of the electron current in the plasma flows into the ground through the first path of the inner upper electrode 34A capacitance 80 10chamber 10, and the other part is the outer upper electrode 34B capacitance 82 chamber. Flows to ground through path 2 of 10). The other part flows to the ground through the third upper path of the chamber 10, the inner upper electrode 34A → capacitance 84 → the outer upper electrode 34B → the capacitance 82 → the side wall of the chamber 10 directly. To reach the ground. Among these, since the third path has the highest impedance, the current flowing is small, and the total amount of current flowing from the inner upper electrode 34A to ground decreases. As such, the proportion of the current flowing through the second path or the side wall of the chamber 10 increases. Thereby, the effect of relatively decreasing the plasma density of an electrode center part and increasing the plasma density of an electrode edge part relatively can be strengthened further. In addition, it is possible to provide a gas chamber and a gas blowing hole in the outer upper electrode 34B to have the function of a shower head.

In addition, the capacitance between the outer upper electrode 34B and the chamber 10 may be made larger than that between the inner upper electrode 34A and the chamber 10. Thereby, the ratio of the electric current which flows to the 2nd path | route or the chamber 10 can be increased reliably compared with a 1st path | route or a 3rd path | pass.

In the plasma etching apparatus of this embodiment, it is also possible to vary the capacitance or the ground capacitance around the upper electrode 34, and examples of the configuration of the capacitance varying portion are shown in Figs.

The capacitance variable portion 86 or 86 'shown in FIGS. 12 and 13 is disposed between a first position contacting or approaching an upper surface of the upper electrode 34 and a second position away from the upper electrode 34. A movable conductor plate 88 or 88 ', an operation mechanism 90 or 90' for moving or displacing the conductor plate 88 or 88 'up and down, and an upper portion through the operation mechanism 90 or 90'. It has a capacitance control unit 85 for controlling the ground capacitance of the electrode 34 to a desired value. The operating mechanism 90 in FIG. 2 is made of a conductive material, a material having a conductive property with respect to a high frequency, or a low impedance material with respect to a high frequency, and is grounded directly or via the chamber 10. The operating mechanism 90 'of FIG. 13 may be an insulating material. This capacitance variable system can vary the ground capacitance of the upper electrode 34 according to the height position of the conductor plate 88 or 88 '. As the conductor plate 88 or 88 'approaches the ceiling surface of the chamber 10, the ground capacitance of the upper electrode 34 can be reduced. Conversely, as the conductor plate 88 or 88 'approaches the upper surface of the upper electrode 34, the ground capacitance of the upper electrode 34 can be increased. Extremely, the upper electrode 34 can be grounded by bringing the conductive plate 88 or 88 'into contact with the upper electrode 34, so that the ground capacitance can be infinite.

The capacitance variable portion 92 illustrated in FIG. 14 forms a ring-shaped liquid storage chamber 94 in a ring-shaped insulator 35 provided between the upper electrode 34 and the sidewall of the chamber 10. The liquid (eg, organic solvent such as galdene) Q having an appropriate dielectric constant is introduced and removed from the outside of the chamber 10 via the pipe 96. By changing the kind (dielectric constant) or the liquid amount of the liquid Q, the capacitance of the entire ring-shaped insulator 35 and the ground capacitance of the upper electrode 34 can be varied.

As another configuration example, a configuration in which a variable capacitor (not shown) is connected between the upper electrode 34 and the chamber 10 is also possible.

In addition, as shown in FIG. 15, the DC power supply 98 is electrically connected to the upper electrode 34, and the structure which applies arbitrary DC voltage to the upper electrode 34 is also possible. Also in this case, the upper electrode 34 achieves a direct current operation in an electrically floating state at the potential of the chamber 10, that is, the ground potential. By applying an appropriate direct current voltage to the upper electrode 34, (1) the absolute value of the self bias voltage of the upper electrode 34 is increased so that sputtering of the upper electrode 34 (deposition removal) is performed. (2) the plasma sheath in the upper electrode 34 is enlarged to reduce the plasma formed, and (3) the electrons generated in the vicinity of the upper electrode 34 are treated. Effect of irradiating onto the substrate (semiconductor wafer W), (4) controlling the plasma potential, (5) increasing the electron density (plasma density), (6) increasing the plasma density of the center portion At least one of the effects can be achieved.

In addition, it is also possible to take the structure as shown in FIG. Specifically, as shown in FIG. 2, the susceptor 16 is fed from the high frequency power supply 30 through the matching unit 32 and the feeding bar 33 to feed the first high frequency wave, and from the high frequency power supply 64. 66) and the second high frequency power supply (lower two-frequency superposition method) via the feed rod 68, and further, as shown in FIG. 10, the upper electrode 34 is in the radial direction with a disk-shaped inner upper electrode 34A. It is a structure divided into two by the ring-shaped outer upper electrode 34B.

In addition, in the above-mentioned embodiment, although the electrical floating state with respect to the ground potential of the upper electrode 34 was demonstrated from a capacitance point of view, it can also be demonstrated from a impedance point of view.

For example, in the above description of FIGS. 5 to 7, when the ground capacitance of the upper electrode 34 is 5000 pF or less, the effect of in-plane uniformity of the etching rate can be obtained, and when it is 2000 pF or less, the in-plane etching rate is obtained. It is said that the effect of uniformity can be obtained certainly. When this is replaced by an impedance, the impedance of the upper electrode 34 seen from the processing space PS side may be 10 Ω or more and 5 Ω or more, respectively.

In addition, in the above embodiment, the ground capacitance of the upper electrode 34 composed of the electrode plate 36 and the electrode support 38 has been described. However, a vacuum space or dielectric is provided between the electrode plate 36 and the electrode support 38, so that only the electrode plate 36 is the upper electrode 34, that is, only the electrode plate 36 is in a floating state. It is good also as a structure. In addition, a separate conductive member which is directly coupled to the electrode plate 36 or the electrode support 38 as a member constituting the upper electrode 34 together with the electrode plate 36 and the electrode support 38. Also good.

The frequency of the high frequency used in the said embodiment is an example, It is possible to use arbitrary frequencies according to a process. In addition, the structure of each part in a device can also be variously modified. Although the above embodiment relates to a plasma etching apparatus and a plasma etching method, the present invention is also applicable to other plasma processing apparatuses and processing methods such as plasma CVD, plasma oxidation, plasma nitriding, sputtering, and the like. In addition, the to-be-processed board | substrate in this invention is not limited to a semiconductor wafer, Various board | substrates for flat panel displays, a photomask, a CD board | substrate, a printed board, etc. are also possible.

According to the plasma processing apparatus or the plasma processing method of the present invention, in-plane uniformity of the process is achieved by uniformizing or arbitrarily controlling the spatial distribution of plasma density generated by the capacitively coupled high frequency discharge by the above-described configuration and action. Can be improved.

Claims (23)

A processing vessel capable of vacuum evacuation, A first electrode attached in the processing vessel in an electrically floating state through an insulator or a space; A second electrode disposed parallel to the first electrode at a predetermined interval in the processing container, the second electrode facing the first electrode and supporting the substrate to be processed; A processing gas supply unit supplying a desired processing gas to a processing space between the first electrode, the second electrode, and a side wall of the processing container; A first high frequency feeder configured to apply a first high frequency to the second electrode to generate a plasma of the processing gas in the processing space, Setting a capacitance between the first electrode and the processing vessel so as to obtain a desired plasma density distribution characteristic for the plasma generated in the processing space; Plasma processing apparatus. The method of claim 1, And a capacitance varying portion for varying the capacitance between the first electrode and the processing vessel. Plasma processing apparatus. The method of claim 1, Constituting the periphery of the first electrode such that the capacitance between the first electrode and the processing vessel is greater than zero and equal to or less than 5000 pF. Plasma processing apparatus. The method of claim 3, wherein Constituting the periphery of the first electrode such that the capacitance between the first electrode and the processing vessel is greater than zero and equal to or less than 2000 pF. Plasma processing apparatus. The method of claim 1, The processing vessel is made of a conductor and grounded Plasma processing apparatus. The method of claim 1, A vacuum space independent from the processing space is provided between the back surface of the first electrode and the processing container as viewed from the second electrode. Plasma processing apparatus. The method of claim 6, A first insulator covering all or part of an inner wall of the vacuum space Plasma processing apparatus. The method of claim 1, When all or part of the portion of the processing container which faces the rear surface of the first electrode when viewed from the second electrode is composed of a second insulator Plasma processing apparatus. The method of claim 1, The first electrode is an upper electrode, and the second electrode is a lower electrode. Plasma processing apparatus. The method of claim 9, A gas chamber for introducing the process gas from the process gas supply unit is provided above or above the first electrode, and a plurality of gas ejection holes for ejecting the process gas from the gas chamber to the process space in the first electrode. Is formed Plasma processing apparatus. The method of claim 10, A ring-shaped third insulator is provided between the outer circumferential surface of the first electrode and the side wall of the processing container. Plasma processing apparatus. The method of claim 11, The third insulator is provided to fill the gap between the outer circumferential surface of the first electrode and the side wall of the processing container. Plasma processing apparatus. The method of claim 10, A space is formed between the outer circumferential surface of the first electrode and the side wall of the processing container. Plasma processing apparatus. The method of claim 1, The first electrode is divided into two disc-shaped inner electrodes and a ring-shaped outer electrode in the radial direction. Plasma processing apparatus. The method of claim 14, A ring-shaped fourth insulator is inserted or a space is formed between the inner electrode and the outer electrode. Plasma processing apparatus. The method of claim 14, A ring-shaped fifth insulator is inserted or a space is formed between the outer electrode and the sidewall of the processing container. Plasma processing apparatus. The method of claim 14, The capacitance between the outer electrode and the processing container is greater than the capacitance between the inner electrode and the processing container. Plasma processing apparatus. The method of claim 1, A second high frequency feeder configured to apply a second high frequency having a frequency lower than that of the first high frequency to the second electrode; Plasma processing apparatus. The method according to any one of claims 1 to 18, Further comprising a direct current power source for applying a desired direct current voltage to the first electrode Plasma processing apparatus. The first electrode and the second electrode are arranged in parallel in the vacuum processing chamber at predetermined intervals, and are opposed to the first electrode to support the substrate to be processed by the second electrode, and the inside of the processing container has a predetermined pressure. Evacuating, supplying a desired processing gas to the processing space between the first electrode, the second electrode and the sidewall of the processing container, and applying a first high frequency to the second electrode to perform the processing in the processing space. In the plasma processing method of generating a plasma of a gas, and performing a desired plasma treatment on the substrate under the plasma, The first electrode is electrically floated with respect to the processing vessel via an insulator or space, and the desired plasma density distribution characteristics of the plasma generated in the processing space can be obtained. To set the capacitance between Plasma treatment method. The method of claim 20, The capacitance between the first electrode and the processing container is made variable. Plasma treatment method. The method of claim 20 or 21, The capacitance between the first electrode and the processing container is selected to a value that is greater than 0 and less than or equal to 2000 pF. Plasma treatment method. The method of claim 22, The capacitance between the first electrode and the processing vessel is selected to a value greater than 0 and less than or equal to 250 pF. Plasma treatment method.

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