KR100839318B1 - Slicing apparatus for receiver - Google Patents

Abstract

The present invention relates to a QAM slicing apparatus in a receiver.

The present invention detects the sign and magnitude of a channel compensated signal received in a multipath, respectively, and determines the first bit value through comparison and subtraction of the detected signal magnitude value and the minimum resolution value, Determining the second bit value by subtracting the selected first bit value from an intermediate value, thereby defining the determination level of the channel data in the QAM slicer and allowing the channel data distribution to have a minimum resolution at regular intervals. To determine the bit.

QAM, Slicer, Decoder, Bit Selection

Description

Slicing apparatus for receiver

1 is a block diagram showing a receiver according to an embodiment of the present invention.

Figure 2 is a detailed block diagram showing a slicer according to the first embodiment of the present invention.

Figure 3 is a detailed block diagram showing a slicer according to a second embodiment of the present invention.

Figure 4 is a detailed block diagram showing a slicer according to a third embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10a to 10n ... Multipath symbol estimator 101 ... Descrambler

102 ... channel estimator 103,106,113,115,125,143 ... multiplier

111,112,133,134 ... Adder 104 ... Channel estimator

105 Complex number 114 Long term average

120 ... channel power calculator 130 ... slicer

131,231 ... Real part extractor 132,232 ... Imaginary part extractor

135,136,234,235,334,335 ... shift register

137,138,238a, 238b, 338a, 338b ... bit selector

139,239249,339,349 ...

140,240,250,340,350 ... absolute value extractor

141a ~ 141n, 241a ~ 241n, 251a ~ 251n, 341a ~ 341n, 351a ~ 351n ...

142a ~ 142m, 242a ~ 242n, 252a ~ 252n, 342a ~ 342n, 352a ~ 352n ... Subtractor

144 ... Bit Median 145,236,336 ... Subtractor

The present invention relates to a slicing device in a receiver for selecting an input bit of channel decoding, in particular in a mobile communication system.

In a wideband code division multiple access (W-CDMA) modem, the slicing operation is located in front of the channel decoder, and its role is to saturate and truncate the bits of the despread symbol to the number of channel decoder input bits (hereinafter referred to as bit selection). ).

Quadrature Amplitude Modulation (QAM) requires more decision boundary values for determining a signal region than quadrature phase shift keying (QPSK). For example, two 16QAM decision systems are required. When the I / Q channel signal positions are -3, -1, 1, and 3, respectively, the first decision boundary is positive with respect to 0 (3,1). ) And a negative boundary (-1, -3), and the second boundary determines a positive boundary (1,3) or a negative boundary (-1, -3), respectively. The actual 16QAM slicer produces four values for one constellation and sends it to the channel decoder.

Here, if the constellation is r, four outputs may be expressed as x1, x2, y1, and y2, respectively.

x1 = real (r)

x2 = dec-abs (x1)

y1 = imag (r)

y2 = dec-abs (y1)

Here, dec (1, 2, 3, ...) is a boundary value for determining 1 and 3. These four values should be matched to the number of input bits of the channel decoder when implemented in real hardware (hereinafter referred to as bit selection). At this time, a method of matching the number of bits includes a method of selecting fixed bits and a method of changing bit selection positions according to signal strength.

After pre-predicting the signal distribution of the actual operating region for the 16QAM signal, the method of saturating and truncating the bits at a fixed position saturates to the case where the signal intensity is the largest, so that the actual quantization resolution This is inefficient.

That is, if the input bit of the channel decoder is a constant bit, the resolution that can be represented by one bit is fixed once, so that the resolution is equally applied to a signal having a signal strength, thereby causing an error in resolution. This resolution error is equally applied to x1, x2, y1, y2. And unlike QPSK, there is an error on the boundary value for the second decision, which is in addition to the x2 and y2 resolution errors.

The first object of the present invention is to allow the input bit of the decoder to be selected using a 16QAM slicer in the receiver.

A second object of the present invention is to allow a slicer in a receiver to adjust bit selection by dividing a channel gain value into short or long term according to the signal speed.

A third object of the present invention is to select a bit quantized by n 16 bits by a 16QAM slicer in a receiver and output it to a decoder.

A fourth object of the present invention is to obtain a quantization value by applying a comparator and a subtractor when selecting bits in a slicer, so that a separate divider is not used.

Slicing device in the receiver according to the present invention for achieving the above object,

In a 16QAM and above slicing device of a receiver,

Code and magnitude detection means for detecting the magnitude and the magnitude of the channel compensated signal received in the multipath, respectively;

First bit selection means for determining a first bit value by comparing and subtracting the signal magnitude value and the minimum resolution value detected by the magnitude detection means;

and second bit selecting means for subtracting the first bit value selected by the first bit selecting means from the intermediate value of the n bit output to determine the second bit value.

Preferably, the minimum resolution value is a short-term channel gain value.

Preferably, the minimum resolution value is a long term channel gain value.

Preferably, the short-term channel gain value is a value obtained by adding a plurality of channel estimated values input through a multipath.

Preferably, the short-term channel gain value may be obtained by using a value obtained by adding a plurality of channel estimation values input through a multipath and a power ratio of a data channel and a pilot channel.

Preferably, the long-term channel gain value is obtained by summing a plurality of channel estimated values inputted through a multi-path for M symbols, and calculating the average using the average value and the power ratio of the data channel and the pilot channel. .

Preferably, the short-term channel gain value or the long-term channel gain value selected according to the channel speed is shifted by 2 ^n-1 bits (n = number of bits) and added to the channel compensated signal.

Preferably, the minimum resolution value is a value in which the short term channel gain value or the long term channel gain value selected according to the channel speed is shifted by 2 ^n-2 (n = number of bits) bits and added.

Preferably, the first bit selection means slices at a predetermined interval for a positive integer value when the magnitude value of the signal is large by comparing the signal magnitude value detected by the magnitude detection means with the minimum resolution value, respectively. And a plurality of comparators outputted between the comparators and a plurality of subtractors connected between the comparators and subtracted to a minimum resolution value when the magnitude value of the signal is input from the comparator at the front end and output to the comparator at the rear end. .

Preferably, the first bit selecting means comprises 2 ^n-1 -1 (n = number of bits) comparators and 2 ⁿ -2 -2 (n = number of bits) subtractors.

Preferably, the first bit selecting means further comprises multiplication means for compensating and outputting the detected code to the code detecting means with respect to the determined first bit value.

Preferably, the second bit selecting means is composed of a subtractor.

A slicing device in a receiver according to another embodiment of the present invention,

A 16QAM and higher slicing apparatus of a receiver, comprising: first code and magnitude detecting means for detecting the sign and magnitude of a channel compensated signal received in a multipath, respectively; A first bit selection for determining a first bit value by compensating the sign of the second code detecting means to a value obtained by comparing and subtracting a signal magnitude value detected by the first size detecting means with a minimum resolution value Means;

Second sign and magnitude detecting means for detecting a sign and magnitude respectively by subtracting a signal magnitude value of the first magnitude detecting means from a channel gain value; Second bit selecting means for compensating the sign of the second code detecting means to a value obtained by comparing and subtracting a signal magnitude value detected by the second size detecting means with a minimum resolution value and determining a second bit value; Characterized in that it comprises a.

Specifically, the channel gain value is shifted 2 ^n-1 (n = number of bits) bits by the first shift register and added to define decision levels of the first bit value and the second bit value, and the second shift register. 2 ^n-2 (n = number of bits) bit shifted to output the vegetable resolution value.

Preferably, the channel gain value is a short term channel gain value or a long term channel gain value.

Preferably, the channel gain value is a short term channel gain value, and the minimum resolution value is a long term channel gain value.

Specifically, the short-term channel gain value is shifted 2 ^n-1 (n = number of bits) bits by the first shift register and added to define decision levels of the first bit value and the second bit value.

The long-term channel gain value is shifted by 2 ^n-1 (n = number of bits) bits by the second shift register, and is output to the first and second bit selection means with vegetable resolution values.

Specifically, the long-term channel gain value is obtained by summing a plurality of channel estimated values input through multipaths for M symbols, and calculating the average, and calculating the average by using the average value and the power ratio of the data channel and the pilot channel. .

Hereinafter, with reference to the accompanying drawings as follows.

1 is a block diagram showing a slicing device in a receiver according to the present invention.

Referring to FIG. 1, a descrambler 101 for descrambling channel data Rx data of N paths, a despreader 102 for despreading descrambled data, and N pieces of data. A channel estimator 104 for estimating a channel value of a path, a complex conjugate 105 that takes a channel estimated value as a complex number, and multiplies the despread symbol value with an output value of the complex number A multipath symbol estimator (10a to 10n) including a first multiplier (103) for compensating channel data, and a second multiplier (106) for multiplying the channel values of the respective paths and the complex part values;

A first adder 111 for combining the total N channel compensated values, a second adder 112 for adding the output values of the N second multipliers 106, and an output of the second adder 112 A third multiplier 113 for multiplying the short-term channel gain value C by the value and outputting the short-term channel gain value a, and a long term for accumulating averaging the output values of the second adder 112. long term) an averager 114, a fourth multiplier 115 that multiplies the output of the long term averager 114 by a channel gain value C, and outputs a long term channel gain value b, and the first multiplier; A slicer 130 that receives an output i of the adder 111 and an output a or b of the third or fourth multipliers 113 and 115 and selects and outputs n bits, and the slicer 130 ), And the decoder 160 decodes the output n bits (eg, 4 bits = x1, x2, y1, y2).

The channel gain value is obtained by the channel power calculator 120, and the channel power calculator 120 calculates the data power estimated by the data power estimator 121 and the channel power estimator CPCP power estimator. Square root calculating unit 123 for square root processing of the estimated channel power by 122, and the output, modulation, and multicode of the square root calculating unit 123 It is obtained by the fifth multiplier 125 that multiplies the factor F and outputs the channel gain value C.

2 is a detailed configuration diagram of the slicer according to the present invention.

Referring to FIG. 2, the slicer 130 is a QAM slicer (eg, 16QAM), and a real part extractor 131 and an imaginary part extracting a real part when an input complex signal i is transmitted. An imaginary part extractor 132 for extracting the first and second first and second shift registers 135 and 136 for shifting the short term channel gain value (a) or the long term channel gain value (b) by a predetermined bit, and the first and second shift registers 135 and 136. Third and fourth adders 133 and 134 for adding the output values of the one shift register 135 to the real and imaginary parts, respectively, and shifted with the output values of the third and fourth adders 133 and 134, respectively. I / Q channel bit selectors 137 and 138 for selecting bits of the I / Q signal using one channel gain value.

The I / Q channel bit selectors 137 and 138 include a code extractor 139, an absolute value extractor 140, 2 ^n-1 -1 comparators 141a to 141n, and 2 ^n-1 -2 A subtractor 142-142m, a sixth multiplier 143 that multiplies the output of the comparators 141a-141n and a sign value, and a bit multiplied value of the output of the comparators 141a-141n and a sign And a subtractor 145 subtracted by an intermediate constant (eg, 4) 144. Here, the selected n bits of the I / Q channel bit selectors 137 and 138, for example, 4 bits, are output as x1, x2, y1, y2.

Referring to the accompanying drawings, the slicing apparatus in the receiver according to the embodiment of the present invention configured as described above is as follows.

Referring to FIG. 1, the reception data signals Rx Data for each path 1 to N paths receive output signals of reception filters of N paths aligned in time. The signal of each path is input to the multipath symbol estimators 10a to 10n to generate a symbol through the descrambler 101 and the despreader 102, and the channel value estimated by the symbol and the channel estimator 104. By multiplying the output value of the complex number 105 of the to make a channel compensated symbol.

That is, the multipath symbol estimators 10a to 10n respectively estimate and compensate channel data values of N paths. To this end, the multipath symbol estimator 10a to 10n includes a descrambler 101, a despreader 102, first and second multipliers 103 and 106, a channel estimator 104, and a complex unit 105.

The descrambler 101 descrambles the channel data received for each path, and the descrambled data signal is obtained as a data symbol value despread by the despreader 102, and the first multiplier 103 Channel is compensated for.

The channel estimator 104 estimates the channel values of the N paths by using the common pilot channel (CPICH) channel, respectively, and the channel estimated values are complex values by the complex number 105 and the first multiplier 103 and the first value. It is output to the multiplier 106. That is, the first multiplier 103 performs channel compensation by multiplying the despread data symbol value by the output value of the complex unit 105, and the second multiplier 106 outputs the channel estimate value by the complex multiplier 105. The result is squared with the value.

The channel compensated values of the respective paths output to the first multipliers 103 of the N multipath symbol estimators 10a to 10n are combined by the first adder 111 and input to the slicer 130, and the second The N channel estimated values output to multiplier 106 are added by second adder 112.

At this time, the output of the second adder 112 is input to the long term averager 114 and the third multiplier 113. The long term averager 114 is summed for M symbols after the channel estimation value of each path is added. To obtain the average and pass it to the fourth multiplier (115). Where M is the number of symbols required to obtain the long term average value in the fading channel.

The third multiplier 113 multiplies and outputs the channel estimate of each path by a value c obtained by the power ratio between the data channel and the CPICH, and the fourth multiplier 115 outputs the output value of the long term averager 114. And multiply the value obtained by the power ratio between the data channel and the CPICH to output the result.

Here, the channel power calculator 120 includes a data power estimator 121, a CPICH power estimator 122, a square root unit 123, and a fifth multiplier 125, wherein the square root unit 123 is a data power unit. The data power estimated by the estimator 121 and the CPICH power estimation value estimated by the CPICH power estimator 122 are routed and then output.

로 구하게 되는데, 상기 A는 데이터 파워 추정 값이며, 상기 B는 파일럿 채널(CPICH) 파워 추정 값이다.Here, the square root portion 123 is a channel power

Where A is a data power estimate and B is a pilot channel (CPICH) power estimate.

The fifth multiplier 125 multiplies the output value of the square root unit 123 by a modulation method and a multiplication factor (F) 124 and multiplies the channel power ratio value by the third and fourth values. Output to multipliers 113 and 115.

The third multiplier 113 multiplies the channel power ratio output from the fifth multiplier 125 by the channel estimate value c and outputs the shortened channel gain value a to the slicer 130 as a fourth multiplier ( The multiplier 115 multiplies the output value of the fifth multiplier 125 by the average channel estimate value and outputs the long term channel gain value b to the slicer 130. Here, the fifth multiplier 125 is adjusted to a factor value of a multiple code and modulation scheme so that the fifth multiplier 125 may exist at an intermediate position of a positive portion of the slicer input data signal distribution.

The slicer 130 is a demodulator consisting of quadrature amplitude modulation (QAM) 16QAM or 64QAM, but the present invention will be described in the case of applying the 16QAM slicer. Bit selection is performed according to the number of input bits (n bits, n = 4) input to the decoder 160 (x1, x2, y1, y2). That is, since the decoder 160, for example, the number of input bits of the turbo decoder is fixed, it makes stable and effective bit selection in a radio channel in which fading exists.

The slicer 130 selectively receives the output signals of the third or fourth multipliers 113 and 115 and slices the input data signal r, thereby performing bit selection. Since the n bits selected by the slicer 130 are input to the decoder 160, the n bits are decoded and output.

To this end, the slicer 130 may use only the channel estimate value to define the interval of bits (4 sections if 16QAM), or the short-term channel gain in which the power ratio is compensated for the channel estimate value when the channel reception rate is below or above a threshold. A value or long term channel gain value may be taken selectively.

Therefore, it is used to select the actual hardware bit by using the short-term or long-term channel gain average value, and especially, by selecting the long-term channel gain average (b) value, stable bit selection is possible even at high fading channels (x1, x2, y1, y2). Will be able to. The bit selection here is to trim the slicer input to the number of input bits of the decoder (saturation & truncation).

In other words, in the case of 16QAM, the receiver should determine this value assuming that the I channel and the Q channel are (-3, -1, 1, 3), respectively. The signal passing through the fading channel will be distorted, and assuming that channel compensation is complete, the receiver will define two decision levels and use it to determine the signal.

In the case of 16QAM, the decision level is 0 and 2, where 0 distinguishes (-3, -1) and (1,3) to distinguish between negative or positive numbers, and 2 denotes two signal parts located in positive numbers (( 1,3). Here, negative numbers (-3, -1) can be distinguished using 2 by substituting positive numbers, and (-3, -1) (3,1) is less than 2 based on 2-and greater than 2 + Becomes

For example, if the received signal is a signal distortion and (x, y) = (-0.3, 2.5), and it is determined without considering the decoder (channel decoder) (I channel only described), x1 = -0.3, x2 = 2-abs (-0.3) = 0.7 is found. Where abs is an absolute value.

(x1 <0) & (x2 <0): -3

(x1> 0) & (x2> 0): -1

(x1> 0) & (x2 <0): 3

(x1> 0) & (x2> 0): 1

In this way, the x signal is obtained by obtaining a bit value x1, and x2 is obtained through an absolute value (x1) subtracted from a constant (dec), and four signal position values are determined using these two bit values (x1, x2). Can be.

However, since the actual receiver uses the decoder and the Viterbi algorithm, the (x1, x2) value obtained above is input to the decoder. Of course, the value of (y1, y2) is input to the decoder as well for the Q channel.

y1 = 2.5

y2 = 2-abs (2.5) = -0.5

In the actual channel, only the second of the decision level values is used, and decision level 2 in the example is replaced by 2 * h (t) * h (t). Of course, the received signals (-3, -1,1,3) are (-3h (t), -h (t), h (t), 3h (t)). When channel compensation is made, it becomes (-3h (t) * h (t), -h (t) * h (t), h (t) * h (t), 3h (t) * h (t)). .

However, in actual hardware implementation, the number of input bits of the decoder is limited. If the number of input bits is 4 bits, the channel estimation value h (t) is a value that changes with time, so the decision level "2 * h (t) * h (t)" also changes with time. This value is the intermediate value of the channel compensated signal (x, y) = (h (t) * (h (t), 3h (t) * h (t)). do.

I channel is x1 = x, x2 = 2hh-abs (x)

2hh: 4 = x1: (Unknown) can determine x1 bit value. The x2 bit value is also determined by 2hh: 4 = x2: (unknown).

Q channel is y1 = y, y2 = 2hh-abs (y)

At this time, the y1 bit value can be determined through 2hh: 4 = y1: (unknown). Also, the y2 bit value is determined by 2hh: 4 = y2: (unknown).

This slicer 130 is as shown in FIG. 2. For convenience of explanation, the description will be made based on the real part signal processing of the input data, and the assumption is made that the number of input bits (n = 4, x1, x2, y1, y2) of the decoder 160 is 4 bits, respectively. Shall be.

2 is a block diagram illustrating a 16QAM slicer according to an embodiment of the present invention.

Referring to FIG. 2, the slicer 130 includes real and imaginary part extractors 131 and 132, third and fourth adders 133 and 134, bit detectors 137 and 138, and a plurality of shift registers 135 and 136.

The real part and imaginary part extractors 131 and 133 extract the real part and the imaginary part from the input data signal r, respectively, and the real part is input to the I channel bit selector 137. The imaginary parts are respectively input to the Q channel bit selector 138.

A channel gain value, such as a short term channel gain value or a long term channel gain value, is added to this signal.

To this end, the first shift register 135 is composed of, for example, a 3-bit shift right register when n = 4. That is, the first shift register 135 is obtained by 1 / (2 ^n-1 ). The second shift register 136 is composed of a 2-bit shift register register, for example, when n = 4 bits. That is, the second shift register 136 is obtained by 1 / (2 ^n-2 ). Where n is the number of input bits of the decoder.

The first shift register 135 is transferred to the third adder 133 and the fourth adder 134 to affect the input data, and the second shift register 136 is a comparator of the bit selector 137 and 138. 141a to 141n) and subtractors 142a to 142m.

If the channel speed is less than or equal to the threshold, the short-term channel gain value (a) is selected and transmitted as a value of a / 8 to the channel signal, and a / 4 is transmitted to the bit selectors 137 and 138. Accordingly, a / 8 is added to the channel data signal to determine a section of 0 (-a / 8 to a / 8) from the signal section, and is applied to the bit selector at a / 4 to divide the signal distribution at intervals of a / 4. give.

Alternatively, when the channel speed is fast or the channel distribution section changes slowly, the long-term average gain value (b) is used. When b is selected, b / 8 is transmitted to the channel data signal so that the 0 section of the I / Q channel is actually 0. (b / 8 to b / 8), and b / 4 is input to the bit selectors 137 and 138, so that the channel signal distribution is decomposed by b / 4 corresponding to a predetermined interval.

The third adder 133 and the fourth adder 134 add the values of the real part and the imaginary part and the 1/8 value of the channel gain average value a or b output by the first shift register 135, respectively. The output of the third adder 133 is input to the I channel bit selector 137, and the output of the fourth adder 134 is input to the Q channel bit selector 138, respectively.

The bit selectors 137 and 138 include a code detector 139 and an absolute value detector 140, a plurality of comparators 141a to 141n, a subtractor 142 to 142m, a multiplier 143, and a subtractor 145.

The code detector 139 detects the signs (+,-) of the received signals (real and imaginary), and the absolute value detector 140 detects the signal magnitude. At this time, the sign and magnitude of the real part and the imaginary part of the received signal are temporarily stored.

When the size of the real part is detected, it is compared by the comparators 141a to 141n, and subtracted by the subtractors 142a to 142m.

Here, the number of comparators 141a to 141n and the subtractor is related to the input bits of the decoder. The comparators 141a to 141n are 2 ^n-1 -1, and the subtractors 142a to 142m are found to be 2 ^n-1 -2. For example, if n = 4, there are 7 comparators and 6 subtractors.

First, the first comparator 141a compares the output real part size x of the absolute value detector 140 with the output y value of the second shift register 136. If x is greater than y, it is determined that x is greater than y, and 0 is output. If x is less than y, it is output to first subtractor 142a. The first subtractor 142a subtracts the y value from the magnitude value of the real part. That is, x = x-y is obtained, and the obtained x value is compared again to see if the value exceeds y by the second comparator 141b. If x is less than y, 1 is sent out. If x is greater than y, it is compared to the third comparator 141c via the second subtractor 142b. If x is less than y, 2 is outputted. In the fourth comparator 141c, if x is larger than y, 3 is outputted, and if it is small, the fourth comparator is subtracted again and compared in the fifth comparator. In this procedure, 6 or 7 is output through the remaining comparator, the subtractor, and the last comparator 141n.

That is, in the last seventh comparator 141n, if x is less than y, 6 is sent out and 7 is exported. Here, when the value of the comparator is exported from either comparator, the subsequent comparison operation is stopped. In other words, the calculation process is performed by the number of comparison operations determined by the number of input bits of the decoder.

In this manner, the positive integer value obtained by the comparators 141a to 141n is multiplied by the sign detector 139 to output a real part x1 value having a positive or negative value. Similarly, the imaginary part is obtained in the above manner. In addition, a positive integer value obtained by the comparators 141a to 141n and a sign (x1) having a positive or negative value by multiplying with a sign of the code detector 139 are obtained, and an n-bit intermediate value ( X2 is output by subtracting the positive integer value abs (x1) at 144. That is, the value obtained by subtracting x1 from the bit intermediate value 144 becomes x2. If the input bit of the decoder is 4 bits, the middle value of the bit is a constant 4 when the positive / negative integer is a reference. If the input bit of the decoder is 5 bits, the value is 8 (4 * 2).

In other words, it is assumed that the number of input bits n of the decoder is 4, and the minimum resolution value y is set by dividing the channel gain value by 4. First, the long term channel gain value is divided by 8 by the first shift register and added to the input value of the slicer 130. This assumes -0.5 to 0.5 (interval 1) as 0, 0.5 to 1.5 (interval 1) as 1, ..., and 5.5 to 6.5 as 6 (assuming the negative resolution is equal to 1). This can keep the same interval 1. On the other hand, if a section of 0 is not defined through a / 8 (or b / 8), -1 to 1 (interval 2) is determined to be 0, and 1 to 2 (interval 1) are determined to be 1 and the same interval This can cause errors in the quantization process.

Obtain the sign and absolute value of the values thus obtained. If the absolute value is greater than the minimum resolution y, then y is subtracted, and if not, 0 is sent to the multiplier 143. After subtracting y once, x compares with minimum resolution y and outputs the result according to the result, or subtracts y once more, repeats the comparison and subtraction, and selects and outputs a value of 1-7.

In addition, since the bit selector 137 assumes that the number of input bits is four, the result of the seven comparisons and six subtractions can achieve the same result as the division. In the seventh size comparison, all values greater than y are saturated to 7. Thus, since the slicer is made on a 4-bit basis, for example, the slicer is composed of seven comparators and six subtractors. In the final multiplier 143, a desired output value is obtained by multiplying a sign value by a positive integer value obtained from a specific comparator. Multiplying by the sign to determine the x1 bit value (abs (x1)), and the x2 bit value is obtained by subtracting abs (x1) from the n-bit intermediate value 144.

Meanwhile, the imaginary part is used to output the y1 and y2 of the Q channel in the same manner as the output method of the x1 and x2 of the I channel.

On the other hand, Figure 3 is a block diagram showing a second embodiment of the 16QAM slicer of the present invention.

As shown in FIG. 3, only x1 and x2 are obtained by using the real part, and the imaginary part is the same as the method of obtaining the real part, and thus will be omitted. In addition, since the part for obtaining the real part x1 is the same as that of FIG. 2, a detailed description thereof will be omitted.

The slicer 130 includes a real part and an imaginary part extractor 231 and 232, adders 233 and 237, first and second bit selectors 238a and 238b, a plurality of shift registers 234 and 235, and a subtractor 236. .

When the channel speed of the input signal r is less than or equal to the threshold value, the slicer 130 selects the short-term channel gain value and uses the long-term average gain value when the channel speed is fast or the channel distribution section is slowly changed.

When the long-term or short-term channel gain value is selected according to the channel speed, a specific channel gain value is inputted to the first shift register 234, shifted by 2 ^n-1 bits, and then output to the adders 233 and 237, respectively. The second shift register 235 is shifted by 2 ^n-2 bits, and then the bit selectors 238a and 238b for selecting the first bit value and the second bit value as the minimum resolution value. Is entered.

The real part and imaginary part extractors 231 and 232 extract the real part and the imaginary part respectively from the input channel data signal r, and the real part is the first bit selector 238a of the I channel. ), And the imaginary parts are respectively input to the first bit selector (not shown) of the Q channel.

In the second bit selector 238b of the I-channel (or Q-channel), the signal extracted by the real part extractor is not input, but the absolute value x of the first bit selector 238a and the channel gain value. (a or b), a value calculated by the channel gain value (a / 8 or b / 8) shifted by the first shift register 234 is input. That is, a- | r | or b- | r | are input.

That is, the selected channel gain value (a or b) is not only applied to the minimum resolution value of the bit selectors 238a and 238b through the second shift register 235, but also transferred to the subtractor 236 to be applied to the subtractor 236. The absolute value x of the 1-bit selector 238a is subtracted and then added to the adder 237 and input to the second bit selector 238b.

Accordingly, the output of the first shift register 234 is input to the adders 233 and 237 to affect the input data, and the output of the second shift register 235 is a bit selector to output the input data signal at the minimum resolution interval. The inputs are input to the comparators 241a to 241n and 251a to 251n and the subtractors 242a to 242m and 251a to 252m, respectively.

That is, in the second embodiment, the absolute value (size value) of the first bit selector 238a is received and subtracted from the first bit value x1 without subtracting the first bit value x1 into the bit intermediate value. It can be used to obtain.

The first and second bit selectors 238a and 238b include code detectors 239 and 249 and absolute value detectors 240 and 250, a plurality of comparators 241a to 241n, 251a to 251n, and a subtractor 242a. 242m) 242a to 242m, and multipliers 243 and 253.

Since the first and second bit selectors 238a and 238b operate in the same manner as the bit selector of the first embodiment to output x1 and x2, respectively, y1 and y2 can be obtained in the same manner as x1 and x2. have. This detailed description will be omitted.

That is, x2 (y2) uses the same method as x1 (y1), and x2 (y2) compares and subtracts a- | r | or b- | r | by using a comparator and a subtractor, and then The 2-bit value will be determined.

Figure 4 is a block diagram showing a third embodiment of the 16QAM slicer of the present invention.

As shown in FIG. 4, only x1 and x2 are obtained by using the real part, and the imaginary part is the same as that of the real part. In addition, since the part for obtaining the real part x1 is the same as that of FIG. 2, a detailed description thereof will be omitted.

Slicer 130 is composed of real and imaginary part extractors 331 and 332, adders 333 and 337, first and second bit selectors 338a and 338b, a plurality of shift registers 234 and 235 and subtractor 236. .

The real part and imaginary part extractors 231 and 232 extract the real part and the imaginary part from the input data signal r, respectively, and the real part is provided to the first bit selector 338a of the I channel. The imaginary parts are respectively input to the first bit selector (not shown) of the Q channel.

The adder 333 adds the output value of the real part extractor 331 and the short-term channel gain value shifted by the first shift register 334 so that the first bit selector 338a of the I (or Q) channel is added. Is entered.

In addition, the second bit selector 338b of the I (or Q) channel subtracts the short-term channel gain value a from the absolute value x of the signal input to the first bit selector 338a, and The value calculated by the one shift register 334 is added and input.

That is, the adder 337 adds the output of the subtractor 336 and the output of the first shift register 334. The subtractor 336 adds the short-term channel gain value to the signal absolute value of the first bit selector 338a. The value is subtracted and output to the adder 337, and the first shift register 334 shifts the short-term channel gain value by 2 ^{n −1} to output to the adder 337.

The adder 337 adds two input signals and outputs the minimum resolution value of the second bit selector 338b.

As described above, the first bit x1 and the second bit x2 are obtained using the signals input to the first bit selector 338a and the second bit selector 338b.

The second shift register 335 shifts the long term channel gain value b and outputs the minimum resolution value 7 to the first bit selector 338a and the second bit selector 338b. The intervals for the input signals from the comparators 341a to 341n and 351a to 351n and the subtractors 342a to 342n and 352a to 352n are constantly output, and finally, the second bit (x2) is obtained.

The first and second bit selectors 338a and 338b operate in the same manner as the bit selector of the first embodiment to output x1 and x2, respectively, and an input for obtaining x2 (a-abs (r)). The short-term channel gain value a is used, and the long-term channel gain value is used for the comparator and the subtractor for the comparison and subtraction operations. In addition, y1 and y2 can be obtained in the same manner as x1 and x2. This detailed description will be omitted.

Using this embodiment, the slicer may effectively slice the channel signal using one or two channel gain values of the long term and short term channel gain values. In addition, the minimum resolution value is input as a variable of the comparator and the subtractor of the bit selector by the channel gain value, so that the input bit of the decoder can be obtained more accurately.

In this way, the 16QAM slicer can make its own stable and effective bit selection without the help of software, thereby reducing fast processing time and unnecessary memory usage. In other words, software help means that the software determines the strength of the signal and adjusts the bit selection. When software is involved, the overall processing time becomes longer. Accordingly, conventionally, if the processing time usually takes one slot, memory is wasted because one slot of data must be stored.

Although 16QAM has been described in the present invention, a slicer such as 16QAM or more, that is, 64QAM or the like can be implemented, and eight signal positions of an I / Q channel can be accurately determined by four decision levels.

So far, the present invention has been described with reference to the preferred embodiments, and those skilled in the art to which the present invention pertains to the detailed description of the present invention and other forms of embodiments within the essential technical scope of the present invention. Could be implemented. Here, the essential technical scope of the present invention is shown in the claims, and all differences within the equivalent range will be construed as being included in the present invention.

As described above, according to the slicing apparatus and method in the receiver according to the present invention, the QAM modulation scheme is adopted, and the slicing apparatus of the present invention is effective in a radio channel in which fading exists.

First, it can reduce its fast processing time and unnecessary memory usage by making its own stable and effective bit selection without the help of software. In other words, software help means that the software determines the signal strength and adjusts the bit selection. Accordingly, when software is involved in the related art, the overall processing time becomes long. If the processing time usually takes one slot, it will waste memory because it must store one slot of data.

Second, by implementing a subtractor without using a divider in the slicer, hardware implementation can be facilitated and the minimum resolution interval can be equal.

Claims (18)

In a 16QAM and above slicing device of a receiver, Code and magnitude detection means for detecting the magnitude and the magnitude of the channel compensated signal received in the multipath, respectively; First bit selection means for determining a first bit value by comparing and subtracting the signal magnitude value and the minimum resolution value detected by the magnitude detection means; and second bit selecting means for determining a second bit value by subtracting a first bit value selected by said first bit selecting means from an intermediate value of an n bit output. The method of claim 1, And the minimum resolution value is a short term channel gain value. The method of claim 1, And the minimum resolution value is a long term channel gain value. The method of claim 2, And the short-term channel gain value is a value obtained by adding a plurality of channel estimated values inputted through a multipath. The method of claim 2, The short-term channel gain value is obtained by using a value obtained by adding a plurality of channel estimation values input through a multipath and a power ratio of a data channel and a pilot channel. The method of claim 3, wherein The long-term channel gain value corresponds to a plurality of channel estimated values input through a multipath. A slicing device in a receiver characterized in that the average is obtained by summing for the number of symbols required to obtain the long term average value in the fading channel, and using the average value and the power ratio of the data channel and the pilot channel. The method of claim 1, And the short-term channel gain value or the long-term channel gain value selected according to the channel speed is shifted by 2 ^n-1 bits (n = number of bits) and added to the channel compensated signal. The method of claim 1, And the minimum resolution value is a value obtained by shifting the short term channel gain value or the long term channel gain value selected according to the channel speed by 2 ^n-2 (n = number of bits) bits. The method of claim 1, The first bit selection means may be configured to slice and output a positive integer value at a predetermined interval when the magnitude value of the signal is large by comparing the signal magnitude value detected by the magnitude detection means with the minimum resolution value. Slicing in the receiver, comprising a plurality of comparators and a plurality of subtractors connected between the comparators and subtracted to a minimum resolution value when the magnitude value of the signal is input from the comparator at the front end and output to the comparator at the next stage. Device. The method of claim 1, And said first bit selecting means comprises 2 ^n-1 -1 (n = number of bits) comparators and 2 ⁿ -2 -2 (n = number of bits) subtractors. The method of claim 1, And said first bit selecting means further comprises multiplication means for compensating and outputting the detected sign to said code detecting means with respect to said determined first bit value. The method of claim 1, And said second bit selecting means comprises a subtractor. In a 16QAM and above slicing device of a receiver, First code and magnitude detecting means for detecting the sign and magnitude of the channel compensated signal received in the multipath, respectively; Second sign and magnitude detecting means for detecting a sign and magnitude respectively by subtracting a signal magnitude value of the first magnitude detecting means from a channel gain value; First bit selection means for determining a first bit value by compensating the sign of the second code detection means to a value obtained by comparing and subtracting a signal magnitude value and the minimum resolution value detected by the first size detection means; and; Second bit selecting means for compensating the sign of the second code detecting means to a value obtained by comparing and subtracting a signal magnitude value detected by the second size detecting means with a minimum resolution value and determining a second bit value; Slicing device in the receiver comprising a. The method of claim 13, The channel gain value is shifted 2 ^n-1 (n = number of bits) bits by the first shift register and added to define the decision level of the first bit value and the second bit value, and 2 by the second shift register. Slicing device in the receiver, characterized in that ^n-2 (n = number of bits) bit shifted output as a vegetable resolution value. The method of claim 13, And the channel gain value is a short term channel gain value or a long term channel gain value. The method of claim 13, Wherein the channel gain value is a short term channel gain value and the minimum resolution value is a long term channel gain value. The method of claim 16, The short-term channel gain value is shifted 2 ^n-1 (n = number of bits) bits by the first shift register and added to define decision levels of the first bit value and the second bit value, And the long-term channel gain value is shifted 2 ^n-1 (n = number of bits) bits by the second shift register and outputted to the first and second bit selection means at a vegetable resolution value. The method of claim 16, The long-term channel gain value is obtained by averaging a plurality of channel estimated values input through a multipath for the number of symbols required to obtain a long-term average value in a fading channel, and using the average value and the power ratio of the data channel and the pilot channel. Slicing device in the receiver, characterized in that obtained.

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