KR100683328B1 - Slicing apparatus and method in receiver - Google Patents

Abstract

The present invention relates to a slicing device and method in a receiver, in particular in a mobile communication system.

The present invention obtains channel gain values for the short term section or the long term section from channel estimation values input through the multipath, respectively, and then selectively converts the channel in the slicer by the short term channel gain value or the long term channel gain value according to the speed of the channel data. By defining the decision level of the data and making the channel data distribution have the minimum resolution, it is possible to determine the input bit of the decoder.

Slicer, Decoder, Bit Selection

Description

Slicing apparatus and method in receiver

1 is a block diagram showing a slicing device in a receiver according to the present invention.

Figure 2 is a detailed block diagram of a slicer according to the present invention.

3 is a flow chart illustrating a slicing method in a receiver according to the present invention.

<Description of the symbols for the main parts of the drawings>

10a to 10n ... Multipath symbol estimator 101 ... Descrambler

102 ... channel estimator 103,106,113,115,125,143 ... multiplier

111,112,133,134 ... Adder 104 ... Channel estimator

105 Complex number 114 Long term average

120 ... channel power calculator 130 ... slicer

131 ... Imperial Extraction Unit 132 ... Imaginary Extraction Unit

135,136 ... Shift Register 137,138 ... Bit Selection

139 ... Sign Extraction 140 ... Absolute Value Extractor

141a ~ 141n ... comparator 142a ~ 142m ... subtractor

144 ... real part output 145 ... imaginary part output

The present invention relates to a slicing device and method in a receiver, in particular in a mobile communication system.

In a code division multiple access (CDMA) modem, the slicing operation is located in front of the channel decoder, and its role is to saturate and truncate the bits of the despread symbol to the number of channel decoder input bits (hereinafter referred to as bit selection).

In general, QPSK (Quadrature (Quaternary) Phase Shift Keying) slicing method is a method that selects a fixed bit by measuring the distribution of all signals in the operating area in advance, or selects a bit according to the signal size by measuring the signal strength. have.

After pre-predicting the signal distribution of the actual operating region for the QPSK signal, the method of saturating and truncating the bits at a fixed position saturates to the case where the signal intensity is the largest, so that the actual quantization resolution This is inefficient.

The first object of the present invention is to divide the channel gain value into short or long term according to the speed of the signal to adjust bit selection in the slicer.

The second object of the present invention is to selectively apply either the long-term channel gain value or the short-term channel gain value obtained by multiplying the channel estimated value or the channel estimated value by the channel power in the slicer as a predetermined cumulative average value, The interval is determined for the channel data, and the bit interval by the minimum resolution value can be equalized.

 A third object of the present invention is to obtain a quantization value by applying a comparator and a subtractor when selecting bits in a slicer, so that a separate divider is not used.

Slicing device in the receiver according to the present invention for achieving the above object,

Code and magnitude detection means for detecting the magnitude and the magnitude of the channel compensated signal received in the multipath, respectively;

And bit selection means for selecting and outputting n bits through a comparison operation between the signal magnitude value detected by the magnitude detection means and the minimum resolution value.

Preferably, the minimum resolution value determined according to the channel rate is a short term channel gain value or a long term channel gain value.

Preferably, the bit selecting means is composed of 2 ^n-1 -1 (n = number of bits) comparators and 2 ^{n -1} -2 (n = number of bits) subtractors.

Preferably, the bit selecting means comprises a plurality of comparators for outputting a positive integer value when the magnitude value of the signal is large by comparing the signal magnitude value detected by the magnitude detecting means with the minimum resolution value, and And a plurality of subtractors connected between the comparators and receiving a magnitude value from the comparator at the front end and subtracting the magnitude value to the minimum resolution value and outputting the comparator at the rear end.

Preferably, the short-term channel gain value is a value obtained by adding a plurality of channel estimated values input through a multipath.

Preferably, the short-term channel gain value is obtained by using a value obtained by adding a plurality of channel estimation values input through a multipath and a power ratio of a data channel and a pilot channel.

Preferably, the long-term channel gain value is obtained by summing a plurality of channel estimated values inputted through a multi-path for M symbols, and calculating the average using the average value and the power ratio of the data channel and the pilot channel. .

In addition, the slicing apparatus in the receiver according to an embodiment of the present invention,

A channel compensator for generating a symbol through descrambling and despreading for the channel data signal input to each path and compensating the channel through a complex multiplication of the channel estimated value, and estimating a channel value for the multipath and estimating the estimated channel value. Multipath symbol estimation means including a channel estimate value output unit for multiplying a channel value and a complex number; A first adder for combining and outputting channel compensated values of each path, and a second adder for adding channel estimated values in each path; A long term averaging unit for calculating an average by summing outputs of the second adder for a predetermined symbol; A first multiplier configured to multiply the output ratio of the second adder by the power ratio of the data channel and the pilot channel and output the short term channel gain value; A second multiplier for multiplying the output of the long term averager by the power ratio of the data channel and the pilot channel and outputting the long term channel gain value; A slicer which receives the short-term channel gain value or the long-term channel gain value according to a channel speed, and selects and selects a bit for the I channel and Q channel distribution of the combined channel data; And a decoder which receives and decodes the bit selected by the slicer.

On the other hand, the slicing method in the receiver according to another embodiment of the present invention,

Detecting a sign and magnitude for a channel compensated signal received in a multipath; And selecting and outputting the number of input bits through a comparison operation using the minimum resolution value to the detected signal magnitude value.

Preferably, the minimum resolution value is a short-term channel gain value obtained by a channel estimate received in a multipath.

Preferably, the minimum resolution value is a long term channel gain value obtained by a channel estimate value received in a multipath.

Preferably, the minimum resolution value is shift written by 2 ^n-1 bits to be added to the channel compensated signal and shifted by 2 ^n-2 bits for comparison with the signal magnitude.

Hereinafter, with reference to the accompanying drawings as follows.

1 is a block diagram showing a slicing device in a receiver according to the present invention.

Referring to FIG. 1, a descrambler 101 for descrambling channel data Rx data of N paths, a despreader 102 for despreading descrambled data, and N pieces of data. A channel estimator 104 for estimating a channel value of a path, a complex conjugate 105 that takes a channel estimated value as a complex number, and multiplies the despread symbol value and the complex output value; A multipath symbol estimator (10a to 10n) including a first multiplier (103) for compensating channel data, and a second multiplier (106) for multiplying the channel values of the respective paths and the complex part values;

A first adder 111 for combining the total N channel compensated values, a second adder 112 for adding the output values of the N second multipliers 106, and an output of the second adder 112 A third adder 113 multiplying the channel gain value C by the channel gain value and outputting the short gain channel a, and a long term cumulative average of the output values of the second adder 112. term) an averager 114, a fourth multiplier 115 for multiplying the output of the long term averager 114 by the channel gain value C and outputting the channel gain value b as a long term channel gain value b; and the first adder. A slicer 130 that receives an output i value of 111 and an output a, b value of the third and fourth multipliers 113 and 115 and selects and outputs n bits, and the slicer 130 A decoder 160 that decodes an output n-bit value (o) of n).

The channel gain value is obtained by the channel power calculator 120, and the channel power calculator 120 calculates the data power estimated by the data power estimator 121 and the channel power estimator CPCP power estimator. Square root calculating unit 123 for square root processing of the estimated channel power by 122, and the output, modulation, and multicode of the square root calculating unit 123 It is obtained by the fifth multiplier 125 that multiplies the factor F and outputs the channel gain value C.

2 is a detailed configuration diagram of the slicer according to the present invention.

Referring to FIG. 2, the slicer 130 extracts a real part extractor 131 for extracting a real part and an imaginary part extractor 132 for extracting an imaginary part when an input complex signal i is transmitted. ), First and second shift registers 135 and 136 to write-shift by a predetermined bit by receiving the short-term channel gain value a or the long-term channel gain value b, and the first shift register 135. By using the third and fourth adders 133 and 134 for adding the output value of the &lt; RTI ID = 0.0 &gt; and &lt; / RTI &gt; real and imaginary parts, respectively, and the output value of the third and fourth adders 133 and 134 and the shifted one channel gain value, I / Q channel bit selectors 137 and 138 for selecting bits of the / Q signal, and real and imaginary part output units 144 and 145 for outputting the final determined bits by extracting the real and imaginary parts of the bit selectors 137 and 138, respectively. ) Is a configuration that includes.

The I / Q channel bit selectors 137 and 138 include a code extractor 139, an absolute value extractor 140, 2 ^n-1 -1 comparators 141a to 141n, and 2 ^n-1 -2 And a sixth multiplier 143 that multiplies the output of the comparators 141a to 141n by the sign value.

Referring to the accompanying drawings, the slicing apparatus of the WCDMA modem according to the embodiment of the present invention configured as described above is as follows.

Referring to FIG. 1, the reception data signals Rx Data for each path 1 to N paths receive output signals of reception filters of N paths aligned in time. The signal of each path is input to the multipath symbol estimators 10a to 10n to generate a symbol through the descrambler 101 and the despreader 102, and the channel value estimated by the symbol and the channel estimator 104. By multiplying the output value of the complex number 105 of the to make a channel compensated symbol.

That is, the multipath symbol estimators 10a to 10n respectively estimate and compensate channel data values of N paths. To this end, the multipath symbol estimator 10a to 10n includes a descrambler 101, a despreader 102, first and second multipliers 103 and 106, a channel estimator 104, and a complex unit 105.

The descrambler 101 descrambles the channel data received for each path, and the descrambled data signal is obtained as a data symbol value despread by the despreader 102, and the first multiplier 103 Channel is compensated for.

The channel estimator 104 estimates the channel values of the N paths by using the common pilot channel (CPICH) channel, respectively, and the channel estimated values are complex values by the complex number 105 and the first multiplier 103 and the first value. It is output to the multiplier 106. That is, the first multiplier 103, the multiplied output value of the despreading data symbol values and a complex unit 105, and performs a channel compensation, a second multiplier 106 may repeat small reservoir 105, a channel estimation value It is output by squared with the output value of.

The channel compensated values of the respective paths output to the first multipliers 103 of the N multipath symbol estimators 10a to 10n are combined by the first adder 111 and input to the slicer 130, and the second The N channel estimated values output to multiplier 106 are added by second adder 112.

At this time, the output of the second adder 112 is input to the long term averager 114 and the third multiplier 113. The long term averager 114 is summed for M symbols after the channel estimation value of each path is added. To obtain the average and pass it to the fourth multiplier (115). Where M is the number of symbols required to obtain the long term average value in the fading channel.

The third multiplier 113 multiplies the channel estimate obtained by summing over M symbols and the value obtained by the power ratio between the data channel and the CPICH, and the fourth multiplier 115 outputs the long term averager 114. A value obtained by multiplying the value by the power ratio between the data channel and the CPICH is output.

Here, the channel power calculator 120 includes a data power estimator 121, a CPICH power estimator 122, a square root unit 123, and a fifth multiplier 125, wherein the square root unit 123 is a data power unit. The data power estimated by the estimator 121 and the CPICH power estimation value estimated by the CPICH power estimator 122 are routed and then output.

Here, the square root unit 123 is obtained for the channel power, where A is a data power estimate and B is a CPICH power estimate.

The fifth multiplier 125 multiplies the output value of the square root unit 123 by the modulation scheme and the multiplication factor (F) 124 and outputs the channel power ratio value to the third and fourth multipliers 113 and 115. Done.

The third multiplier 113 multiplies the channel power ratio output from the fifth multiplier 125 by the channel estimation value and outputs the result to the slicer 130, and the fourth multiplier 115 outputs the fifth multiplier 125. The value is multiplied by the average channel estimate value and output to the slicer 130. Here, the fifth multiplier 125 is adjusted to a factor value of a multiple code and modulation scheme so that the fifth multiplier 125 may exist at an intermediate position of a positive portion of the slicer input data signal distribution.

The slicer 130 is a demodulator consisting of Quadrature (Quaternary) Phase Shift Keying (QPSK) or M-array Phase Shift Keying (MPSK), and selects bits according to the number of input bits (n bits) input to the decoder 160. Done. That is, since the decoder 160, for example, the number of input bits of the turbo decoder is fixed, it makes stable and effective bit selection in a radio channel in which fading exists.

The slicer 130 selectively receives the output signals of the third or fourth multipliers 113 and 115 and slices the input data signal i, thereby performing bit selection. Since the n bits selected by the slicer 130 are input to the decoder 160, the n bits are decoded and output.

To this end, the slicer 130 may use only the channel estimate value to define the interval of the bit, or, if the channel reception rate is lower than or equal to a certain value, the slicer 130 may use the short term channel gain value or the long term channel gain value whose power ratio is compensated for. Get drunk.

Accordingly, the average hardware bit is selected by using the short-term or long-term channel gain average value. In particular, the long-term channel gain average (b) value is used to enable stable bit selection even in a high fading channel. The bit selection here is to trim the slicer input to the number of input bits of the decoder (saturation & truncation).

In other words, in the case of QPSK, the receiver should determine this value assuming that the I channel and the Q channel are (-8 to 7), respectively. The signal passing through the fading channel will be distorted, and assuming that channel compensation is complete, the receiver will define one decision level and use it to determine the signal. In the case of QPSK, the decision level is 0 intervals. That is, 0 distinguishes (-8, 7).

In hardware implementations, the number of input bits of the decoder is limited. If the number of input bits is 4 bits, the channel estimation value h (t) is a value that changes with time, so the decision level also changes with time. If this value is channel compensated signal (x, y) = (-h (t) * (h (t), h (t) * h (t)) and the decision level is h (t) * h (t) The x bit value can be determined by hh: 4 = x: (), and the y bit value can be determined by hh: 4 = y: ().

This slicer 130 is as shown in FIG. 2. For convenience of explanation, the real part signal processing of the input data will be described as a reference, and it will be described on the assumption that the number of input bits (n = 4) of the decoder 160 is four.

Referring to FIG. 2, the slicer 130 includes a real part and an imaginary part extractor 131 and 132, third and fourth adders 133 and 134, a bit detector 137 and 138, a real output part 144, and an imaginary output part 145. ), And a plurality of shift registers 135 and 136.

The real part and imaginary part extractors 131 and 133 extract the real part and the imaginary part from the input data signal i, respectively, and the real part is input to the I channel bit selector 137. The imaginary parts are respectively input to the Q channel bit selector 138.

The first shift register 135 is composed of, for example, a 3-bit shift right register when n = 4. That is, the first shift register 135 is obtained by 1 / (2 ^n-1 ). The second shift register 136 is composed of, for example, a 2 bit shift register when n = 4 bits. That is, the second shift register 136 is obtained by 1 / (2 ^n-2 ). Where n is the number of input bits of the decoder.

The first shift register 135 is transferred to the third adder 133 and the fourth adder 134 to affect the input data, and the second shift register 136 is a comparator of the bit selector 137 and 138. 141a to 141n) and subtractors 142a to 142m.

If a is selected, the channel signal is transmitted with a value of a / 8, and the bit selector 137 receives a / 4, so that a / 8 is added to the channel data signal. a / 8 to a / 8) are determined and applied to the bit selector at a / 4 to divide the signal distribution at intervals of a / 4.

Alternatively, when the channel speed is fast or the channel distribution section is slowly changed, the long-term average gain value is used. When b is selected, b / 4 is transmitted to the channel signal so that an interval of 0 of the I / Q channel (-a / 4 ~ a / 4), and b / 4 is input, so the channel signal distribution is decomposed by b / 4 corresponding to a certain interval.

The third adder 133 and the fourth adder 134 add the values of the real part and the imaginary part and the 1/8 value of the channel gain average value a or b output by the first shift register 135, respectively. The output of the third adder 133 is input to the I channel bit selector 137, and the output of the fourth adder 134 is input to the Q channel bit selector 138, respectively.

The bit selectors 137 and 138 include a code detector 139 and an absolute value detector 140, a plurality of comparators 141a to 141n, a subtractor 142 to 142m, and a multiplier 143.

The code detector 139 detects the sign (+,-) of the real part, and the absolute value detector 140 detects the size of the real part. The real part sign and size at this time are temporarily stored.

When the size of the real part is detected, it is compared by the comparators 141a to 141n, and subtracted by the subtractors 142a to 142m.

Here, the number of comparators 141a to 141n and the subtractor is related to the input bits of the decoder. The comparators 141a to 141n are 2 ^n-1 -1, and the subtractors 142a to 142m are found to be 2 ^n-1 -2. For example, if n = 4, there are 7 comparators and 6 subtractors.

First, the first comparator 141a compares the output real part size x of the absolute value detector 140 with the output y value of the second shift register 136. If x is greater than y, it is determined that x is less than y, and 0 is output. If x is greater than y, it is output to first subtractor 142a. The first subtractor 142a subtracts the y value from the magnitude value of the real part. That is, x = x-y is obtained, and the obtained x value is compared again to see if the value exceeds y by the second comparator 141b. If x is less than y, 1 is sent out. If x is greater than y, it is compared to the third comparator through the next second subtractor 142b. If x is less than y, 1 is outputted. In the third comparator, if x is less than y, 2 is emitted; if it is larger, the third comparator is subtracted again and compared in the fourth comparator. In this order, the remaining comparators, subtractors, and comparators are compared.

Here, in the last seventh comparator 141n, if x value is less than y value, 6 is sent out, and if it is large, 7 is exported. Here, when the value of the comparator is exported from either comparator, the subsequent comparison operation is stopped. In other words, the calculation process is performed by the number of comparison operations determined by the number of input bits of the decoder.

In this way, the positive integer value obtained by the comparator is multiplied by the sign detector 139 to output a real part having a positive or negative value. Similarly, the imaginary part is obtained in the above manner.

In other words, it is assumed that the number of input bits n of the decoder is 4, and the minimum resolution value y is set by dividing the long term channel gain value by 4. First, the long term channel gain value is divided by 8 by the first shift register and added to the input value of the slicer 130. This assumes -0.5-0.5 (interval 1) as 0, 0.5-1.5 (interval 1) as 1, ㅇ, 5.5-6.5 as 6 (a negative part is also assumed) This can keep the same interval 1. On the other hand, if a section of 0 is not defined through a / 8 (or b / 8), -1 to 1 (interval 2) is determined to be 0, and 1 to 2 (interval 1) are determined to be 1 and the same interval This can cause errors in the quantization process.

Obtain the sign and absolute value of the values thus obtained. If the absolute value is greater than the minimum resolution y, then y is subtracted, and if not, 0 is sent to the multiplier 143. Then, if the output signal x is greater than the minimum resolution y, then y is subtracted, otherwise 1 is sent to the multiplier 143. The multiplier 143 multiplies the outputs of the comparators 141a to 141n by the sign. For example, since it is assumed that the number of bits is 4, a total of seven size comparisons and six subtractions yield the same result as the division. In the seventh size comparison, all values greater than y are saturated to 7.

Thus, since the slicer is made on a 4-bit basis, for example, the slicer is composed of seven comparators and six subtractors. In the final multiplier 143, a desired output is obtained by multiplying a sign value by a positive integer value obtained from a specific comparator. Make.

In this way, the QPSK slicer can make its own stable and effective bit selection without the help of software, thus reducing fast processing time and unnecessary memory usage. In other words, software help means that the software determines the strength of the signal and adjusts the bit selection. When software is involved, the overall processing time becomes longer. Accordingly, conventionally, if the processing time usually takes one slot, memory is wasted because one slot of data must be stored.

3 is a flowchart illustrating a slicing method of a CDMA modem according to the present invention.

Referring to FIG. 3, in order to determine the interval range according to the channel distribution, the input data signal compensated with the multipath is divided into a real part and an imaginary part (S111), and one of channel short-term or long-term channel gain average values according to channel speed. The channel gain is set to the minimum resolution value (S113), and the short or long term channel gain value is divided by 1/2 ^n-1 and added to the real part and the imaginary part (S115). That is, if the channel speed is less than or equal to a certain speed, the short-term channel gain value is shifted by the short-term channel gain value according to the channel distribution in the real part and the imaginary part to set a section of 0, which is the determination level of QPSK, and the channel speed is a constant speed. If this is the case, the long term channel gain value is added to the real part and the imaginary part to shift the channel distribution by the long term channel gain value, thereby setting the section of 0, which is the determination level of the minimum resolution.

Thereafter, the sign and size of the input data to which the short or long term channel gain value is added are detected (S117), and the input data size is compared with the minimum resolution value of the channel gain to perform a constant interval, that is, the minimum resolution for the channel distribution. The bit section is determined at an interval of (1/2 ^n-2 ) (S119). Thereafter, the comparison result is multiplied by a sign to select an input bit of the decoder (S121).

So far, the present invention has been described with reference to the preferred embodiments, and those skilled in the art to which the present invention pertains to the detailed description of the present invention and other forms of embodiments within the essential technical scope of the present invention. Could be implemented. Here, the essential technical scope of the present invention is shown in the claims, and all differences within the equivalent range will be construed as being included in the present invention.

 As described above, according to the slicing apparatus and method in the receiver according to the present invention, the QPSK modulation scheme is adopted, and the slicing apparatus of the present invention has the following effects in a radio channel in which fading exists.

First, it can reduce its fast processing time and unnecessary memory usage by making its own stable and effective bit selection without the help of software. In other words, software help means that the software determines the signal strength and adjusts the bit selection. Accordingly, when software is involved in the related art, the overall processing time becomes long. If the processing time usually takes one slot, it will waste memory because it must store one slot of data.

Second, by implementing a subtractor without using a divider in the slicer, hardware implementation can be facilitated and the minimum resolution interval can be equal.

Claims (23)

Code and magnitude detection means for detecting the magnitude and the magnitude of the channel compensated signal received in the multipath, respectively; And bit selection means for selecting and outputting n bits through a comparison operation of the signal magnitude value and the minimum resolution value detected by the magnitude detection means. The method of claim 1, And the minimum resolution value is a short term channel gain value. The method of claim 1, And the minimum resolution value is a long term channel gain value. The method of claim 1, And said bit selecting means comprises 2 ^n-1 -1 (n = number of bits) comparators and 2 ^{n -1} -2 (n = number of bits) subtractors. According to claim 1, The bit selecting means includes a plurality of comparators for outputting a positive integer value when the magnitude value of the signal is large by comparing the signal magnitude value detected by the magnitude detecting means with the minimum resolution value, and the comparator. And a plurality of subtractors connected between the plurality of subfields and receiving a magnitude value from a comparator at the front end and subtracting the magnitude value to a minimum resolution value and outputting the result to a comparator at a rear end. The method of claim 5, The bit selecting means outputs bit distributions for the input signal magnitude values at regular intervals through comparison with the minimum resolution value, And the detected code is applied to the code detecting means with respect to the bit output by the bit selecting means. The method of claim 2, And the short-term channel gain value is a value obtained by adding a plurality of channel estimated values inputted through a multipath. The method of claim 2, The short-term channel gain value is obtained by using a value obtained by adding a plurality of channel estimates input through a multipath and a power ratio of a data channel and a pilot channel. The method of claim 3, wherein The long-term channel gain value is obtained by summing a plurality of channel estimated values input through a multi-path for M symbols, and calculating the average using the average value and the power ratio of the data channel and the pilot channel. Device. A channel compensator for generating a symbol through descrambling and despreading for the channel data signal input to each path and compensating the channel through a complex multiplication of the channel estimated value, and estimating a channel value for the multipath and estimating the estimated channel value. Multipath symbol estimation means including a channel estimate value output unit for multiplying a channel value and a complex number; A first adder for combining and outputting channel compensated values of each path, and a second adder for adding channel estimated values in each path; A long term averaging unit for calculating an average by summing outputs of the second adder for a predetermined symbol; A first multiplier configured to multiply the output ratio of the second adder by the power ratio of the data channel and the pilot channel and output the short term channel gain value; A second multiplier for multiplying the output of the long term averager by the power ratio of the data channel and the pilot channel to output the long term channel gain value; A slicer which receives the short-term channel gain value or the long-term channel gain value according to a channel speed, and selects and selects a bit for the I channel and Q channel distribution of the combined channel data; And a decoder which receives and decodes the bit selected by the slicer. The method of claim 10, A square root calculator configured to perform a square root processing of the data power estimated by the data power estimator and the channel power estimated by the CPICH power estimator, and the square root calculator A third multiplier for outputting the power ratio of the data channel and the pilot channel to the first and second multipliers by a channel gain value C by multiplying the output and the modulation method F by a multicode. A slicing device in a receiver, characterized in that it further comprises a channel power calculation unit. The method of claim 10, The slicer includes a real part extractor for extracting a real part and an imaginary part extractor for extracting an imaginary part when the input complex signal i is transmitted, and a short-term channel gain value (a) or a long-term channel gain. First and second shift registers for receiving a value (b) and shifting predetermined bits, respectively; third and fourth adders for adding the output values of the first shift register to the real part and the imaginary part, respectively; I-channel and Q-channel bit selecting means for separating the sign and magnitude of the output values of the third and fourth adders and selecting the bits for the distribution of the I / Q signals using the shifted channel gain values; And a real part and an imaginary part output part for extracting the real and imaginary parts of the Q channel bit selection means and outputting the final determined bits to the decoder. The method of claim 12, And the slicer uses a short-term channel gain value if the channel speed is less than or equal to a predetermined rate, and uses a long-term channel gain value if the channel speed is greater than or equal to the predetermined rate. The method of claim 12, The first shift register is a shift write register of 2 ^n-1 bits if the number of input bits is signed n bits. And the second shift register is a shift write register of 2 ^n-2 bits if the number of input bits is signed n bits. The method of claim 12, The bit selecting means receives a real part and an imaginary part of the channel data, respectively, and extracts a sign, a absolute value extractor which takes an absolute value for the channel data, a channel data signal of the absolute value and the second value. A bit selector that obtains a positive integer value by comparing, subtracting, and comparing the output channel gain value of the shift register; and a fifth multiplier that multiplies the positive value output by the comparison operation part with the sign. And a slicing device in the receiver. The method of claim 12, A first comparator for comparing the absolute value of the channel data with the channel gain value and outputting a result value of 0 if the channel data is large, and outputting the channel data for comparison if the channel data is small; and output channel data of the first comparator Compares the output channel data of the first subtractor and the first subtractor with the channel gain value and the channel gain value again, and repeats the operation of the second comparator outputting 1, so that the last m subtractor and the n th comparator Slicing device in the receiver, characterized in that for outputting a positive value corresponding to the number of input bits through. The method according to claim 12 or 16, And the bit selector comprises 2 ^n-1 -1 comparators and 2 ^n-1 -2 subtractors if the number of input bits of the decoder is signed n bits. delete delete delete delete delete delete

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