KR100838396B1 - Internal voltage generator and generation method in semiconductor device - Google Patents

Abstract

An internal voltage generator of a semiconductor memory device and a method thereof are provided to control operation period of the internal voltage generator in a test mode by adding test mode operation in the internal voltage generator of the semiconductor memory device. A voltage detection unit(300) detects the level of a boosting voltage, and outputs a detection signal with an enable period determined in response to the detection result. An enable period changing unit(340) outputs a test detection signal by changing the enable period of the detection signal received in response to an enable period test signal. A multiplexing unit(350) outputs one of the detection signal and the test detection signal in response to a test mode signal. An oscillation unit(310) outputs an oscillation signal toggling with an expected cycle in the enable period of a signal outputted from the multiplexing unit. A pumping unit(320) outputs the boosting voltage by performing charge pumping operation in response to the oscillation signal.

Description

INTERNAL VOLTAGE GENERATOR AND GENERATION METHOD IN SEMICONDUCTOR DEVICE

1 is a block diagram illustrating a boost voltage generator of a semiconductor memory device according to the related art.

FIG. 2 is a detailed view of a voltage detector of components of a boosted voltage generator of a semiconductor memory device according to the related art shown in FIG. 1.

3 is a block diagram illustrating a boost voltage generator of a semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a detailed circuit diagram illustrating an ACTIVE activation section variation unit and an ACTIVE multiplexing unit among components of a boost voltage generator of a semiconductor memory device according to an embodiment of the present invention shown in FIG. 3.

FIG. 5 is a circuit diagram illustrating an output unit in detail of components of a boosted voltage generator of a semiconductor memory device according to an exemplary embodiment of the present invention illustrated in FIG. 3.

FIG. 6 is a timing diagram illustrating waveforms of signals output from a boosted voltage generator of a semiconductor memory device according to an exemplary embodiment of the present invention illustrated in FIG. 3.

* Explanation of symbols for the main parts of the drawings.

100, 300: voltage detector 110.310: oscillator

120, 320: pumping unit 330: output unit

340: activation section change unit 350: multiplexing unit

112, 312: ACTIVE oscillator 114, 314: STANDBY oscillator

342: ACTIVE activation section change section 344: STANDBY activation section change section

352: ACTIVE multiplexer 354: STANDBY multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to an internal voltage generator of a semiconductor memory device, and more particularly, to a circuit capable of adjusting an operating period of an internal voltage generator in a test mode.

Most semiconductor devices including DRAMs have internal voltage generators for generating internal voltages of various potentials using a power supply voltage (VDD) and a ground voltage (VSS) supplied from the outside. It supplies its own voltage. The main issue in designing such an internal voltage generator is to provide a stable supply of internal voltage at a desired level.

In addition to the high-speed operation of semiconductor devices, low power has been accelerated. Accordingly, a design technique for satisfying the performance required in a low voltage environment is required. Under such a low voltage environment, most semiconductor devices compensate for voltage loss occurring when operating using the power supply voltage VDD, and boost voltage VPP having a voltage level higher than the power supply voltage VDD to maintain normal data. )need.

In particular, a boost voltage VPP is widely used in DRAM to compensate for a loss caused by a threshold voltage of a MOS transistor in a word line driver circuit, a bit line isolation circuit, and a data output buffer circuit.

On the other hand, in the case of DRAM, the back bias voltage VBB having a voltage level lower than the ground voltage VSS is applied to the bulk of the NMOS transistor used as the cell transistor.

The boosted voltage VPP, the back bias voltage VBB, and the like are generated using a charge pumping method, and since the voltage generation mechanism is the same, the configuration is similar.

1 is a block diagram illustrating a boost voltage generator of a semiconductor memory device according to the related art.

Referring to FIG. 1, a boosted voltage generator of a semiconductor memory device according to the related art has the following configuration.

A voltage detector which detects the level of the boosted voltage VPP output terminal by comparing the feedback boosted voltage VPP and the reference voltage VREFP, and outputs detection signals PPEA and PPES in which an activation period is determined in response to the detection result. 100 and an oscillation unit 110 for outputting oscillation signals AOSC and SOSC which toggles with a predetermined period in the activation period of the detection signals PPEA and PPES, and oscillation signals AOSC and SOSC. In response, the pumping unit 120 is configured to output a boosted voltage VPP by performing a charge pumping operation.

Here, the detection signals PPEA and PPES output from the voltage detection unit 100 may include the ACTIVE detection signal PPEA for controlling generation of the boosted voltage VPP during the ACTIVE operation of the semiconductor memory device, and the stepped-up voltage transition during the STANDBY operation. It is divided into a STANDBY detection signal PPES for controlling generation of (VPP).

Similarly, the oscillator 110 also outputs the ACTIVE oscillator 112 that outputs the ACTIVE oscillation signal AOSC in response to the ACTIVE detection signal PPEA, and the STANDBY oscillation signal SOSC in response to the STANDBY detection signal PPES. Is divided into a STANDBY oscillator 114.

In addition, the pumping unit 120 also includes an ACTIVE pumping unit 122 performing a charge pumping operation in response to the ACTIVE oscillation signal AOSC, and an ACTIVE pumping unit performing a charge pumping operation in response to the STANDBY oscillation signal SOSC. Divided by 124.

As described above, the oscillation unit 110 and the pumping unit 120 in which the generation of the boost voltage VPP is generated according to the ACTIVE operation of the semiconductor memory device and the STANDBY operation of the semiconductor memory device are different from each other. This is because the amount of boosted voltage VPP used in the semiconductor memory device is different according to the operation and the STANDBY operation of the semiconductor memory device.

For example, in the STANDBY operation of the semiconductor memory device, since the amount of the boosted voltage VPP used is relatively small, only the STANDBY pumping unit 124 is operated to generate the boosted voltage VPP.

However, in the ACTIVE operation of the semiconductor memory device, since the amount of the boosted voltage VPP is relatively large, the boosted voltage VPP is generated by operating both the STANDBY pumping unit 124 and the ACTIVE pumping unit 122. Let's do it.

FIG. 2 is a diagram illustrating in detail a voltage detector among components of a boosted voltage generator of a semiconductor memory device according to the related art shown in FIG. 1.

Referring to FIG. 2, the voltage detector 100 of the components of the boosted voltage generator of the semiconductor memory device according to the related art has the following configuration.

A detector for comparing the level of the feedback boosted voltage VPP and the reference voltage VREFP to detect the level of the boosted voltage VPP output terminal, and outputting a detection result signal DET_AS in which an activation period is determined in response to the detection result. And the ACTIVE detection signal output unit 104 for outputting the ACTIVE detection signal PPEA for operating the ACTIVE pumping unit 122 in response to the detection result signal DET_AS, and the detection result signal DET_AS. In response, a STANDBY detection signal output unit 106 for outputting a STANDBY detection signal PPES for operating the STANDBY pumping unit 124 is provided.

Here, the ACTIVE detection signal output unit 104 and the STANDBY detection signal output unit 106 are turned on / off regardless of the level of the detection result signal DET_AS input in response to the operation control signal TVPP_OFF. Off) Controlled.

In addition, the ACTIVE detection signal PPEA and STANDBY detection signal PPES output in response to the initialization signal PWRUP_PRE are initialized to predetermined levels.

As described above, the ACTIVE detection signal output unit 104 and the STANDBY detection signal output unit 106 are used to detect the detection signals PPEA and PPES output according to the ACTIVE operation of the semiconductor memory device or the STANDBY operation of the semiconductor memory device. Additional functions such as adjusting the activation time point are also performed, but eventually, the signal is activated in response to the activation of the detection result signal DET_AS, and deactivated in response to the deactivation of the detection result signal DET_AS. I will not explain.

The operation of the boost voltage generator of the semiconductor memory device according to the prior art will be described with reference to FIGS. 1 through 2 as follows.

The voltage detector 100 compares the boosted voltage VPP fed back from the pumping unit 120 with the reference voltage VREFP to detect when the level of the boosted voltage VPP is lower than the level of the reference voltage VREFP. Output signals PPEA and PPES.

Here, the activation section of the detection signals PPEA and PPES is determined in response to the level difference between the boosted voltage VPP and the reference voltage VREFP.

That is, the detection signals PPEA and PPES have a long activation period when the level difference between the boost voltage VPP and the reference voltage VREFP is relatively large, and the level difference between the boost voltage VPP and the reference voltage VREFP is increased. Relatively small has a short activation interval.

The oscillator 110 oscillates the oscillation signals AOSC and SOSC having a predetermined period in response to the detection signals PPEA and PPES received from the voltage detector 100.

The pumping unit 120 outputs a boosted voltage VPP by performing a charge pumping operation according to toggling of the oscillation signals AOSC and SOSC.

That is, the pumping unit 120 performs a charge pumping operation in response to the oscillation signals AOSC and SOSC that toggle within the activation period of the detection signals PPEA and PPES.

Therefore, the charge pumping operation is not performed in the section in which the oscillation signals AOSC and SOSC are not toggled, that is, in the inactive section of the detection signals PPEA and PPES.

Although the boosted voltage generator of the semiconductor memory device is operated by the above-described method, the boosted voltage generator of the semiconductor memory device according to the related art operates the signal used in the boosted voltage generator, in particular, the boosted voltage generator according to the activation period. There was no test to increase or decrease the activation interval of detection signals (PPEA, PPES) with different intervals.

The present invention has been proposed to solve the above problems of the prior art, and provides a circuit that can adjust the operation period of the internal voltage generator in the test mode by adding a test mode operation to the internal voltage generator of the semiconductor memory device. There is a purpose.

According to an aspect of the present invention for achieving the above technical problem, the voltage detection means for detecting the level of the boosted voltage, and outputting a detection signal for determining the activation period in response to the detection result; Activation section changing means for varying an activation section of the detection signal received in response to an activation section test signal and outputting the test section as a test detection signal; Multiplexing means for selecting and outputting any one of the detection signal and the test detection signal in response to a test mode signal; Oscillating means for outputting an oscillating signal having a predetermined period in an activation section of a signal output from the multiplexing means; And pumping means for outputting the boosted voltage by performing a charge pumping operation in response to the oscillation signal.

In addition, according to another aspect of the present invention for achieving the above technical problem, detecting the level of the boost voltage, and determining the activation period of the detection signal output in response to the detection result; Changing an activation section of the detection signal received in response to an activation section test signal and outputting the test section as a test detection signal; Selecting one of the detection signal and the test detection signal in response to a test mode signal and outputting the selected signal to an outside of the semiconductor memory device; Outputting a periodic signal for toggling in response to a frequency of the oscillation signal within an activation period of the selected signal in the selecting and outputting to the outside of the semiconductor memory device; And outputting the boosted voltage by performing a charge pumping operation in response to the periodic signal.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

3 is a block diagram illustrating a boost voltage generator of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, a boosted voltage generator of a semiconductor memory device according to an embodiment of the present invention has the following configuration.

The voltage detector 300 detects the level of the boosted voltage VPP and outputs the detection signals PPEA and PPES in which the activation section is determined in response to the detection result, and in response to the activation section test signals TM1 and TM4. Activation section changing unit 340 for varying the activation section of input detection signals PPEA and PPES and outputting them as test detection signals TPEPA and TPPES, and detection signal PPEA in response to test mode signals TM2 and TM3. Oscillation toggling with a predetermined period in the activation section of the signal output from the multiplexing unit 350 and the multiplexing unit 350 to select and output any one of the signal, PPES) and the test detection signal (TPPEA, TPPES) An oscillator 310 for outputting signals AOSC and SOSC, and a pumping unit 320 for outputting a boosted voltage VPP by performing a charge pumping operation in response to the oscillation signals AOSC and SOSC, and testing Output signal of the multiplexer 350 in response to the mode signals TM2 and TM3 A further includes an output unit 330 for outputting to the outside of the semiconductor memory device.

Here, the detection signals PPEA and PPES output from the voltage detector 300 may include the ACTIVE detection signal PPEA for controlling generation of the boosted voltage VPP during the ACTIVE operation of the semiconductor memory device, and the step-up voltage input during the STANDBY operation. It is divided into a STANDBY detection signal PPES for controlling generation of (VPP).

Similarly, the activation section changing unit 340 also outputs the ACTIVE detection section PPEA as an ACTIVE test detection signal TPEPE in response to the ACTIVE activation section test signal TM1, and In response to the STANDBY activation section test signal TM4, the STANDBY detection section PPES is divided into a STANDBY activation section changing section 344 which outputs the STANDBY detection signal PPES as the STANDBY test detection signal TPEPES.

In addition, the multiplexer 350 also includes an ACTIVE multiplexer 452 for selecting and outputting any one of an ACTIVE detection signal PPEA and an ACTIVE test detection signal TPEPE in response to the ACTIVE test mode signal TM2. The STANDBY multiplexing unit 454 selects and outputs one of the STANDBY detection signal PPES and the STANDBY test detection signal TPEPE in response to the STANDBY test mode signal TM3.

In addition, the oscillator 310 also responds to a signal output from the ACTIVE oscillator 312 and the STANDBY multiplexer 454 that outputs the ACTIVE oscillation signal AOSC in response to the signal output from the ACTIVE multiplexer 452. It is divided into a STANDBY oscillator 314 which outputs a STANDBY oscillation signal SOSC.

In addition, the pumping unit 320 also includes an ACTIVE pumping unit 322 that performs a charge pumping operation in response to the ACTIVE oscillation signal AOSC, and an ACTIVE pumping unit which performs a charge pumping operation in response to the STANDBY oscillation signal SOSC. Divided by (324).

As described above, the reason why the oscillation part 310 and the pumping part 320 in which the generation of the boosted voltage VPP is generated according to the ACTIVE operation of the semiconductor memory device and the STANDBY operation of the semiconductor memory device is different is explained in the related art. I will not explain it here.

According to the above-described embodiment of the present invention, a circuit for testing a boost voltage generator of a semiconductor memory device includes an independent ACTIVE activation section change unit 342 and an ACTIVE multiplexer 352 according to the ACTIVE operation of the semiconductor memory device. In addition, the independent STANDBY activation section changing unit 344 and the STANDBY multiplexing unit 354 according to the STANDBY operation of the semiconductor memory device have a test according to the ACTIVE detection signal PPEA and a test according to the STANDBY detection signal PPES, respectively. It is possible to do it independently.

In the following description, the internal configuration and operation of the ACTIVE activation section changing unit 342 and the ACTIVE multiplexing unit 352 will be described.

However, the ACTIVE activation section changing unit 342, the STANDBY activation section changing unit 344, the ACTIVE multiplexing unit 352, and the STANDBY multiplexing unit 354 each have the same configuration and perform an operation, but the input signal and the output signal are the same. Since only the name and the operation time of, the STANDBY activation section changing section 344 and STANDBY multiplexing section 354 actually have the same configuration as the ACTIVE activation section changing section 342 and ACTIVE multiplexing section 352 described later. You can do the same thing with them.

FIG. 4 is a detailed circuit diagram illustrating an ACTIVE activation section variation unit and an ACTIVE multiplexing unit among components of a boost voltage generator of a semiconductor memory device according to an exemplary embodiment of the present invention shown in FIG. 3.

Referring to FIG. 4, the connection relationship between the ACTIVE activation section variation unit 342 and the ACTIVE multiplexer 352 among the components of the boost voltage generator of the semiconductor memory device according to the embodiment of the present invention may be understood.

First, the ACTIVE activation section changing unit 342 includes a rising edge detection unit 3424 and a rising edge of the ACTIVE activation test signal TM1 that detects and outputs a rising edge of the ACTIVE detection signal PPEA. In response to an output signal NO4 of the second rising edge detector 3342 and the first rising edge detector 3424, which detects and outputs an edge, a pull-up driving of the ACTIVE test detection signal TPEPE is performed. A test detection signal driver 3426 is configured to pull down the ACTIVE test detection signal TPEPE in response to the output signal NO3 of the rising edge detector 3342.

Here, the second rising edge detector 3342 may include a falling edge detector 3342a for detecting and outputting a falling edge of the ACTIVE detection signal PPEA, and an output signal NO1 of the falling edge detector 3342a. A latch unit 3422b and an output signal of the latch unit 3342b which receive an input signal as a set input and invert a phase of the ACTIVE activation test signal TM1 as a reset input and latch an SR. And a third rising edge detector 3342c that detects the rising edge of the inverted signal NO2 and outputs the output edge as the output signal NO3 of the second rising edge detector 3342.

In addition, the test detection signal driver 3426 pulls up the drive in response to the output signal NO4 of the first rising edge detector 3424, and outputs the output signal NO3 of the second rising edge detector 3342. A phase of a signal output from the driver 3426a for pull-down driving in response, a test detection signal initializer 3426b for initializing the ACTIVE test detection signal TPEPE in response to the initialization signal PWRUP_PRE, and a driver 3426a Is inverted and output as an ACTIVE test detection signal TPEPE, and further includes a latch portion 3426b for latching the level of the ACTIVE test detection signal TPEPE.

That is, the ACTIVE activation section changing unit 342 is pulled up in response to the rising edge of the detection signal PPEA, and is pulled down in response to the rising edge of the ACTIVE activation test signal TM1 (TPPEA). )

In addition, the ACTIVE multiplexer 352 performs a multiplexing operation of outputting any one of an ACTIVE detection signal PPEA and an ACTIVE test detection signal TPEPE in response to the ACTIVE test mode signal TM2.

Therefore, when the activation time of the ACTIVE activation test signal TM1 and the ACTIVE test mode signal TM2 is properly adjusted, the activation time is the same as the ACTIVE detection signal PPEA, but the inactivation time is arbitrarily adjustable. ) Can be printed.

However, the ACTIVE multiplexer 352 checks whether the activation section of the ACTIVE test detection signal TPEPE output in the test mode is arbitrarily adjusted as the user intended, or the activation section of the ACTIVE detection signal PPEA output in the normal mode. In order to determine the difference between the activation interval between the ACTIVE test detection signal TPEPE and the ACTIVE test detection signal TPPEA, the signal PPEA or TPPEA output from the ACTIVE multiplexer 352 must be monitored outside the semiconductor memory device.

Therefore, the boosted voltage generator according to the embodiment of the present invention further includes an output unit as follows, so that the signal PPEA or TPPEA output from the ACTIVE multiplexer 352 can be monitored outside the semiconductor memory device.

FIG. 5 is a circuit diagram illustrating an output unit in detail of components of a boosted voltage generator of a semiconductor memory device according to an embodiment of the present invention shown in FIG. 3.

Referring to FIG. 5, the output unit 330 of the components of the boosted voltage generator of the semiconductor memory device according to the embodiment of the present invention has the following configuration.

The control signal generator 332 generates the first control signal CON1 and the second control signal CON2 in response to the data DATA output from the semiconductor memory device, and in response to the ACTIVE test mode signal TM2. Responding to the first selection unit 334 for selecting and outputting any one of the first control signal CON1 and the output signal PPEA or TPPEA of the ACTIVE multiplexer 352, and the ACTIVE test mode signal TM2. Of the second selector 336 and the first selector 334 to select and output any one of the second control signal CON2 and the output signal PPEA or TPPEA of the ACTIVE multiplexer 352 Pull-up driving in response to an output signal, pull-down driving in response to an output signal of the second selector 336, and outputting pull-up or pull-down driven data to a predetermined data input / output pin DQ. An output driver 338 is provided.

That is, in the test mode, the pull-up or pull-down driven data is output to the predetermined data input / output pin DQ in response to the output signal PPEA or TPPEA of the ACTIVE multiplexer 352. In the normal mode, the first control is performed. In response to the signal CON1 and the second control signal CON2, pull-up or pull-down driven data is output to the predetermined data input / output pin DQ.

3 to 5, the operation of the boosted voltage generator of the semiconductor memory device according to the exemplary embodiment of the present invention will be described as follows.

The voltage detector 300 compares the boosted voltage VPP fed back from the pumping unit 320 with the reference voltage VREFP to detect when the level of the boosted voltage VPP is lower than that of the reference voltage VREFP. Output signals PPEA and PPES.

Here, the activation section of the detection signals PPEA and PPES is determined in response to the level difference between the boosted voltage VPP and the reference voltage VREFP.

That is, the detection signals PPEA and PPES have a long activation period when the level difference between the boost voltage VPP and the reference voltage VREFP is relatively large, and the level difference between the boost voltage VPP and the reference voltage VREFP is increased. Relatively small has a short activation interval.

The activation section changing unit 340 is activated at an activation point such as the detection signals PPEA and PPES, and outputs test detection signals TPEPE and TPPES that are deactivated at the activation point of the activation section test signals TM1 and TM4. .

That is, the test detection signals TPPEA and TPPES for adjusting the activation period are output according to the activation time points of the activation period test signals TM1 and TM4.

The multiplexer 350 receives the detection signals PPEA and PPES and the test detection signals TPEPE and TPPES and outputs the detection signals PPEA and PPES in the normal mode in response to the test mode signals TM2 and TM3. In test mode, test detection signals TPEPE and TPPES are output.

The oscillator 310 oscillates the oscillation signals AOSC and SOSC having a predetermined period in response to the output signals PPEA or TPPEA, PPES or TPPES of the multiplexer 350.

The pumping unit 320 outputs a boosted voltage VPP by performing a charge pumping operation according to toggling of the oscillation signals AOSC and SOSC.

That is, the pumping unit 320 performs a charge pumping operation in response to the oscillation signals AOSC and SOSC that toggle within the section in which the output signals PPEA or TPPEA, PPES or TPPES of the multiplexing unit 350 are activated. do.

Therefore, the charge pumping operation is not performed in a section in which the oscillation signals AOSC and SOSC are not toggled, that is, in a section in which the output signals PPEA or TPPEA, PPES or TPPES of the multiplexer 350 are deactivated.

The output unit 330 allows the output signal PPEA or TPPEA, PPES or TPPES of the multiplexer 350 to be output to the outside of the semiconductor memory device through the predetermined data input / output pin DQ.

That is, in the normal mode in response to the test mode signals TM2 and TM3, the data may be data of the semiconductor memory device-cell data inside the semiconductor memory device, or may be address data. Is output to the outside of the semiconductor memory device through the predetermined data input / output pin (DQ), but in the test mode, the output signal (PPEA or TPPEA, PPES or TPPES) of the multiplexer 350 is scheduled. Output to the outside of the semiconductor memory device through (DQ).

Therefore, the user can easily monitor the operation section test by the boosted voltage generator of the semiconductor memory device by analyzing a waveform of a signal output through the data input / output pin DQ, which is scheduled outside the semiconductor memory device.

FIG. 6 is a timing diagram illustrating a waveform of a signal output from a boosted voltage generator of a semiconductor memory device according to an embodiment of the present invention illustrated in FIG. 3.

 Referring to FIG. 6, a timing of a signal output from a boosted voltage generator of a semiconductor memory device according to an exemplary embodiment of the present invention illustrated in FIG. 3 may be known. It can be seen that the output signal of 350 is divided into two cases (<A> and <B>).

For reference, the waveform shown in FIG. 6 is based on the waveform output during the ACTIVE operation of the semiconductor memory device, and the waveform output during the STANDBY operation of the semiconductor memory device also has the same characteristics as the waveform output during the ACTIVE operation of the semiconductor memory device. Have

In each case (<A>, <B>), the detailed description is as follows.

In the case of <A>, the ACTIVE test mode signal TM2 is activated to operate the semiconductor memory device in the test mode.

First, the initialization signal PWRUP_PRE is activated to initialize all signals output from the boosted voltage generator of the semiconductor memory device.

When the ACTIVE detection signal PPEA is activated, the rising edge of the ACTIVE detection signal PPEA is detected (NO4), and both the ACTIVE test detection signal TPEPE and the output signal of the multiplexer 350 are activated.

If the ACTIVE detection signal PPEA is deactivated after a certain period of time, the falling edge of the ACTIVE detection signal PPEA is detected (NO1), but it is operated in the test mode, and thus the output of the ACTIVE test detection signal TPEPE and the multiplexer 350 is output. It has no effect on the signal. (②)

When the ACTIVE activation test signal TM1 is activated after a certain time, the rising edge of the ACTIVE activation test signal TM1 is detected (NO2, NO3) to output the ACTIVE test detection signal TPEPE and the output signal of the multiplexer 350. Deactivate all (③)

When the ACTIVE detection signal PPEA is activated again, the rising edge of the ACTIVE detection signal PPEA is detected (NO4), so that both the ACTIVE test detection signal TPEPE and the output signal of the multiplexer 350 are activated. ④)

When the ACTIVE detection signal PPEA is deactivated after a certain time, the falling edge of the ACTIVE detection signal PPEA is detected (NO1), but still operates in the test mode, so that the ACTIVE test detection signal (TPPEA) and the multiplexing unit 350 It has no effect on the output signal. (⑤)

When the ACTIVE activation test signal TM1 is activated after a certain time, the rising edge of the ACTIVE activation test signal TM1 is detected (NO2, NO3) to output the ACTIVE test detection signal TPEPE and the output signal of the multiplexer 350. Deactivate all (⑥)

After a certain period of time, the ACTIVE test mode signal TM2 is deactivated to terminate the test mode operation.

In the above test mode operation, the ①, ②, ③ operation and the ④, ⑤, ⑥ operation are the same operation.

However, the ACTIVE activation test signal TM1 is adjusted by adjusting the time at which the ACTIVE activation test signal TM1 is activated from the activation time of the ACTIVE detection signal PPEA so that the operations ①, ②, ③ and ④, ⑤, ⑥ differ from each other. If the time of activation of) is different, even in the same test mode operation, the activation period of the output signal of the ACTIVE test detection signal (TPPEA) and the multiplexer 350 is different.

In the case of <B>, the ACTIVE test mode signal TM2 is inactivated and the semiconductor memory device operates in the normal mode.

When the ACTIVE detection signal PPEA is activated, the rising edge of the ACTIVE detection signal PPEA is detected (NO4), and both the ACTIVE test detection signal TPEPE and the output signal of the multiplexer 350 are activated.

When the ACTIVE detection signal PPEA is deactivated after a certain time, the falling edge of the ACTIVE detection signal PPEA is detected (NO1) to deactivate the output signal of the multiplexer 350. (8)

At this time, since the ACTIVE activation test signal TM1 is not a test mode operation, it is not input at all.

Therefore, the ACTIVE test detection signal TPEPE remains activated until it is initialized.

As described above, according to the exemplary embodiment of the present invention, an activation period of a signal used in a booster voltage generator of a semiconductor memory device, particularly, a detection signal PPEA or PPES in which an operation period of the booster voltage generator varies according to an activation period. Test mode operation allows you to perform tests such as randomly increasing or decreasing.

In addition, the waveform of the signal under test can be externally monitored through the data input / output pins during test mode operation.

Therefore, the test mode operation may shorten the defect analysis time of the semiconductor memory device, thereby contributing to shortening the product development schedule.

In addition, the above-described embodiment of the present invention may be applied to an internal voltage generation circuit of a semiconductor device generated through a pumping operation, such as a boost voltage VPP.

For example, the present invention is also applicable to a back bias voltage VBB generation circuit.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently in position and type depending on the polarity of the input signal.

According to the present invention, an activation period of a signal used in a booster voltage generator of a semiconductor memory device, in particular, a detection signal PPEA or PPES in which an operation period of the booster voltage generator varies according to an activation period, is arbitrarily increased or decreased through a test mode operation. Tests can be performed.

In addition, the waveform of the signal under test can be externally monitored through the data input / output pins during test mode operation.

Therefore, the test mode operation may shorten the defect analysis time of the semiconductor memory device, thereby contributing to shortening the product development schedule.

In addition, the above-described embodiment of the present invention may be applied to an internal voltage generation circuit of a semiconductor device generated through a pumping operation, such as a boost voltage VPP.

For example, the present invention is also applicable to a back bias voltage VBB generation circuit.

Claims (9)

Voltage detection means for detecting a level of the boosted voltage and outputting a detection signal in which an activation section is determined in response to the detection result; Activation section changing means for varying an activation section of the detection signal received in response to an activation section test signal and outputting the test section as a test detection signal; Multiplexing means for selecting and outputting any one of the detection signal and the test detection signal in response to a test mode signal; Oscillating means for outputting an oscillating signal having a predetermined period in an activation section of a signal output from the multiplexing means; And Pumping means for outputting the boosted voltage by performing a charge pumping operation in response to the oscillation signal An internal voltage generator of a semiconductor device having a. The method of claim 1, And an output means for outputting the output signal of the multiplexing means to the outside of the semiconductor memory device in response to the test mode signal. The method of claim 1, The activation section changing means, And activating the test detection signal in response to the activation of the detection signal, and deactivating the test detection signal in response to the activation of the activation test signal. The method of claim 3, The activation section changing means, A first rising edge detector configured to detect and output a rising edge of the detection signal; A second rising edge detector configured to detect and output a rising edge of the activation test signal; And And a test detection signal driver configured to pull-up the test detection signal in response to an output signal of the first rising edge detector and pull down the test detection signal in response to an output signal of the second rising edge detector. An internal voltage generator of a semiconductor memory device. The method of claim 4, wherein The second rising edge detector, A falling edge detector configured to detect and output a falling edge of the detection signal; A latch unit configured to receive an output signal of the falling edge detector as a set input, and to receive an SR signal of an inverted phase of the activation test signal as a reset input; And And a third rising edge detector configured to sense and output a rising edge of the signal inverting the output signal of the latch unit. The method of claim 4, wherein The test detection signal driver, A driving unit configured to pull up driving in response to an output signal of the first rising edge detector and to pull down driving in response to an output signal of the second rising edge detector; A test detection signal initialization unit for initializing the test detection signal in response to the initialization signal; And And a latch unit for inverting a phase of a signal driven by the driver and outputting the test detection signal as a test detection signal, and latching a level of the test detection signal. The method of claim 2, The output means, A control signal generator configured to generate a first control signal and a second control signal in response to data output from the semiconductor memory device; A first selector which selects and outputs one of the first control signal and the output signal of the multiplexing means in response to the test mode signal; A second selector which selects and outputs one of the second control signal and the output signal of the multiplexing means in response to the test mode signal; A pull-up drive in response to an output signal of the first selector, a pull-down drive in response to an output signal of the second selector, and a data output for outputting pull-up or pull-down data to a predetermined data input / output pin An internal voltage generator of a semiconductor memory device, characterized in that it comprises a drive unit. Detecting a level of the boosted voltage and outputting a detection signal for determining an activation period in response to the detection result; Changing an activation section of the detection signal in response to an activation section test signal and outputting the test section as a test detection signal; Selecting one of the detection signal and the test detection signal in response to a test mode signal and outputting the selected signal to an outside of the semiconductor memory device; Outputting an oscillation signal toggling with a predetermined period in an activation period of a signal selected in the step of outputting to the outside of the semiconductor memory device; And Outputting the boosted voltage by performing a charge pumping operation in response to the oscillation signal Internal voltage generation method of a semiconductor memory device comprising a. The method of claim 8, Outputting to the outside of the semiconductor memory device, Selecting one of the detection signal and the test detection signal in response to the test mode signal; And And outputting the signal selected in the selecting step to the outside of the semiconductor memory device in response to the test mode signal.

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