KR100834391B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to refresh control of a semiconductor memory device. According to an aspect of the present invention, a command decoder for outputting an auto-refresh signal according to a ras signal, a cas signal, a write enable signal and a clock; An address buffer buffering the input address and providing the buffer to the following address controller; When the first test signal is activated while the auto-refresh signal is activated, the ROH addresses of the first group and the second group for performing the refresh of the redundancy cell are activated and output, and the normal when the second test signal is activated. The row address control unit for activating and outputting a row address of the first group for performing a cell refresh; A row address decoder configured to decode the row address applied from the row address control unit to activate word lines of the normal cell and the redundancy cell, wherein the row address control unit comprises: the auto-refresh signal and the first test; There is provided a semiconductor memory device including an internal address generator for generating the row address according to a signal and the second test signal, and a multiplexer for selecting and outputting an output address of the internal address generator or an output address of the address buffer. .

Refresh, redundancy, test, row address, counter

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram of a conventional semiconductor memory device.

FIG. 2 is a detailed configuration diagram illustrating an internal address generator of FIG. 1. FIG.

3 is a detailed circuit diagram of the flip-flop of FIG.

4 is a block diagram of a semiconductor memory device according to the present invention.

FIG. 5 is a detailed configuration diagram illustrating the internal address generator of FIG. 4. FIG.

6 and 7 are detailed circuit diagrams of the flip-flop of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory device design techniques, and in particular, to refresh control.

Generally, semiconductor memory devices are classified into dynamic memory devices (DRAM) and static memory devices (SRAM). Among them, SRAM implements a basic cell with four transistors forming a latch, so stored data is preserved without damage unless power is removed. Thus, no refresh operation to recharge the data is required.

However, DRAM constitutes a basic cell with one transistor and one capacitor, and stores data in the capacitor. However, due to the characteristics of the capacitor element, the charge of the capacitor representing the stored data decreases with time. Accordingly, the DRAM device requires a refresh operation of recharging data in a memory cell at regular intervals in order to maintain data stored in the DRAM.

This refresh operation is performed through a series of processes as follows. The word line of the memory cell is selected while sequentially changing the row address at predetermined time intervals. The charge stored in the capacitor corresponding to this word line is amplified by the sense amplifying means and stored in the capacitor again. Through this series of refresh processes, the stored data is preserved without damage.

In the past, the refresh was performed by inputting an instruction and an address necessary for the refresh to the outside. However, in recent years, the refresh is generated by generating an instruction and an address necessary for refreshing internally due to the ease of control and the speed of the chip. have.

There are two methods for generating a refresh address internally and performing refresh, such as auto refresh and self refresh.

First of all, DRAM uses self-refresh mode to realize low power consumption. The self-refresh operation generates even the Lars / RAS signal used as the refresh synchronization signal from the internal device, and the Cas / CAS signal occurs before the Lars / RAS signal, and then refreshes itself under certain conditions.

When the self refresh mode is entered, the self counter of the self refresh mode is used to perform refresh cycle by one cycle. At this time, the order of performing the refresh by enabling the word line is performed by the entire refresh cycle by generating a row address by receiving the information of the address generated from the counter as in the normal refresh mode.

On the other hand, in the auto refresh apparatus, instead of receiving a refresh address from the outside, a refresh address counter built in the memory device chip generates a row address to perform a refresh, so-called CAS-Before-Ras Refresh; CBR). This is a method of refreshing using an internally generated address while ignoring an externally input address when the casing / CAS signal occurs before the Lars / RAS signal. After a certain time after entering the CBR, it enters the self refresh mode.

1 is a block diagram of such a conventional semiconductor memory device.

The conventional semiconductor memory device includes an instruction decoder 10, an address buffer 20, a row address control unit 30, and a row address decoder 40. Here, the row address control unit 30 includes an internal address generation unit 31 and a multiplexer 32. Then, the test mode signal TM is input to the row address control unit 30.

First, the command decoder 10 decodes the ras signal / RAS, the cas signal / CAS, the write enable signal / WE, and the clock CKE to output the auto-refresh signal AREF. The address buffer 20 buffers and outputs the input addresses A <0:12>.

The internal address generator 31 then counts the addresses according to the auto-refresh signal AREF and sequentially outputs the row addresses RA <0:12>. The multiplexer 32 selects one of the output of the internal address generator 31 or the buffered addresses A <0:12> applied from the address buffer 20 and outputs the row addresses RA <0:12>. The row address decoder 40 decodes the row addresses RA <0:12> to address Lax01 <0: 3>, Lax2 <0: 1>, Lax34 <0: 3>, Lax56 <0: 3>, Lax78 <0 Outputs: 3>, Lax9a <0: 3>, Laxbc <0: 3>, and Laxd <0: 1>.

FIG. 2 is a detailed configuration diagram of the internal address generator 31 of FIG. 1.

The internal address generator 31 includes a plurality of T-flip flops FF1 to FF5. Here, the T-flip-flop FF1 counters the auto-refresh signal AREF and the reset signal RST and outputs the row address RA <0>. The remaining T-flip flops FF2 to FF5 counter the row addresses RA <0> to RA <12> and the reset signal RST of the preceding flip-flop, respectively, and sequentially output the row addresses RA <1> to RA <12>. .

FIG. 3 is a detailed circuit diagram of a plurality of T-flip flops FF1 to FF5 of FIG. 2. Here, since the detailed circuit diagrams of the plurality of T-flip flops FF1 to FF5 are all the same and only the input signal is different, the first T-flip flop FF1 will be described as an example.

The T-flip flop FF1 includes inverters IV1 to IV6, a NOA gate NOR1, a NAND gate ND1, and a transfer gate T1.

Inverter IV1 inverts the auto-refresh signal AREF, and inverter IV2 inverts the output of NAND gate ND1. A latch consisting of inverter IV3 and NOR gate NOR1 latches the output of inverter IV2 and is reset in accordance with the reset signal RST. The transfer gate T1 selectively outputs the output of the NOR gate NOR1 in accordance with the auto-refresh signal AREF and the output state of the inverter IV1.

The latch composed of the inverter IV4 and the NAND gate ND1 latches the output of the transfer gate T1 and is reset in accordance with the reset signal RST inverted by the inverter IV5. Inverter IV6 inverts the output of NAND gate ND1 and outputs row address RA <0>.

The operation of the conventional refresh apparatus having such a configuration will be described below.

First, the address output from the address buffer 20 is output to the row address decoder 40 via the multiplexer 32. At this time, when the auto-refresh signal AREF is activated in the command decoder 10, the T-flip-flop FF shown in FIG. 2 operates as a row address counter to sequentially generate all row addresses RA <0:12>. That is, whenever one auto-refresh signal AREF is activated, the value of the T-flip-flop FF, which is the row address counter, is sequentially increased from the row address RA <0>.

The T-flip-flop FF resets its output to a low level when the reset signal RST generated due to the termination of the power-up operation or the refresh operation of the normal or redundant cells is activated. On the other hand, when the auto-refresh signal AREF toggles from low to high, the output of the NOR gate NOR1 maintained at the high level by the reset signal RST becomes the high level. Then, when the auto-refresh signal AREF transitions from high to low, the output becomes high level.

Therefore, the reverse level of the previous state is output from each T-flip-flop FF every cycle in which auto-refresh is performed, so that the row address can be counted.

However, in the conventional semiconductor memory device, when the test mode signal TM is applied in the parallel test mode to perform auto-refresh, all the cells of the main word line are refreshed and the redundancy word line is performed. This will refresh the cell.

In a memory device having a word line of 8K, 13 T-flip-flops FF operate to refresh all normal word line cells. In the case of having 128 redundancy cells, the lower seven T-flip flops FF are operated to refresh the redundancy cells.

Therefore, when observing the timing of the transition from normal to redundancy in the failure analysis, it is possible to observe after performing the 8K refresh. Conversely, after refreshing the 128 redundancy cells, the timing of transition to normal refresh can be observed.

This results in more test cycles, which increases test time and makes it difficult to monitor when 8K refresh operations have been performed. That is, in case of failure analysis, when the refresh of the normal and the redundancy is performed at the same time, there is a problem in that the timing of the redundancy cell refresh cannot be observed only when the 8K normal refresh is performed.

The present invention has been proposed to solve the above problems, and has the following object.

First, when the test mode signal is entered during the failure analysis, the 8K th row address is forcibly set in the internal address counter of the row address control unit so that the redundancy cell can be refreshed as soon as one refresh signal is input. The purpose is to shorten the time.

Second, when the test mode signal is entered during the failure analysis, the test mode is set to the 128th row address to shorten the test time by performing normal refresh.

According to an aspect of the present invention for achieving the above object, the command decoder for outputting the auto-refresh signal in accordance with the ras signal, the cas signal, the write enable signal and the clock; An address buffer buffering the input address and providing the buffer to the following address controller; When the first test signal is activated while the auto-refresh signal is activated, the ROH addresses of the first group and the second group for performing the refresh of the redundancy cell are activated and output, and the normal when the second test signal is activated. The row address control unit for activating and outputting a row address of the first group for performing a cell refresh; A row address decoder configured to decode the row address applied from the row address control unit to activate word lines of the normal cell and the redundancy cell, wherein the row address control unit comprises: the auto-refresh signal and the first test; And an internal address generator for generating the row address according to a signal and the second test signal, and a multiplexer for selecting and outputting an output address of the internal address generator or an output address of the address buffer. An apparatus is provided.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a configuration diagram illustrating a semiconductor memory device according to the present invention.

The present invention includes a command decoder (100), an address buffer (200), a row address control unit (300), and a row address decoder (400). Here, the row address controller 300 includes an internal address generator 310 and a multiplexer 320. The test mode signal TM, the test signal Tnor_red, and the test signal Tred_nor are input to the row address control unit 300.

First, the command decoder 100 decodes the ras signal / RAS, the cas signal / CAS, the write enable signal / WE, and the clock CKE to output the auto-refresh signal AREF. The address buffer 200 buffers and outputs the input addresses A <0:12>.

The internal address generator 310 counts addresses according to the auto-refresh signal AREF, the test signal Tnor_red, and the test signal Tred_nor, and sequentially outputs the row addresses RA <0:12>. The multiplexer 320 selects one of the output of the internal address generator 310 or the buffered addresses A <0:12> applied from the address buffer 200 to output the row addresses RA <0:12>. The row address decoder 400 decodes the row addresses RA <0:12> and activates a plurality of addresses Lax01 <0: 3>, Lax2 <0: 1>, Lax34 <for activating the word lines of the normal cell and the redundancy cell. 0: 3>, Lax56 <0: 3>, Lax78 <0: 3>, Lax9a <0: 3>, Laxbc <0: 3>, and Laxd <0: 1>.

FIG. 5 is a detailed configuration diagram illustrating the internal address generator 310 of FIG. 4.

The internal address generator 310 includes a first counter part 311 including a plurality of T-flip flops FF6 to FF8 of the first group, and a first counter part including a plurality of T-flip flops FF9 to FF11 of the second group. Two counter parts 312 are provided.

Here, the first T-flip flop FF6 of the first counter unit 311 counts the auto-refresh signal AREF, the reset signal RST, the test signal Tnor_red and the test signal Tred_nor to output a row address RA <0>. The remaining T-flip flops FF7 to FF8 of the first group counter the row addresses RA <0> to RA <5>, the reset signal RST, the test signal Tnor_red, and the test signal Tred_nor of the front flip-flop, respectively. Outputs RA <1> ~ RA <6> sequentially.

Further, the first T-flip-flop FF9 of the second counter part 312 counts the row address RA <6>, which is the final output of the first counter part 311, the reset signal RST, and the test signal Tnor_red to count the row address RA. Outputs <7>. The remaining T-flip flops FF10 to FF11 of the second group counter the row addresses RA <7> to RA <12>, the reset signal RST and the test signal Tnor_red of the front flip-flop, respectively. RA <12> is output sequentially.

FIG. 6 is a detailed circuit diagram of the first counter 311 of FIG. 5. Here, since the detailed circuit diagrams of the plurality of T-flip flops FF6 to FF8 of the first group are all the same and only the input signal is different, the first T-flip flop FF6 will be described as an embodiment of the present invention. The first counter 311 receives a test signal Tnor_red and a test signal Tred_nor as its inputs.

T-flip-flop FF6 includes inverters IV7 to IV12, NOA gates NOR1 and NOR2, NAND gates ND2, ND3 and transfer gate T2.

Here, inverter IV7 inverts the auto-refresh signal AREF. Then, the NOR gate NOR2 performs a NO operation on the test signal Tnor_red and the test signal Tred_nor. The NAND gate ND1 performs a NAND operation on the output of the NOR gate NOR2 and the output of the NAND gate ND3.

Inverter IV8 inverts the output of NAND gate ND2. A latch consisting of inverter IV9 and NOR gate NOR3 latches the output of inverter IV8 and is reset in accordance with the reset signal RST. The transfer gate T2 selectively outputs the output of the NOR gate NOR3 according to the auto-refresh signal AREF and the output state of the inverter IV7.

The latch composed of the inverter IV10 and the NAND gate ND3 latches the output of the transfer gate T2 and is reset in accordance with the reset signal RST inverted by the inverter IV11. Inverter IV12 inverts the output of NAND gate ND3 and outputs row address RA <0>.

FIG. 7 is a detailed circuit diagram of the second counter 312 of FIG. 5. Here, since the detailed circuit diagrams of the plurality of T-flip flops FF9 to FF11 of the second group are all the same and only the input signal is different, the first T-flip flop FF9 will be described as an embodiment of the present invention. The second counter 312 receives only the test signal Tnor_red as its input.

The T-flip flop FF9 includes inverters IV13 to IV19, a NOA gate NOR4, a NAND gate ND4, ND5, and a transfer gate T3.

Here, inverter IV13 inverts row address RA <6>. Inverter IV14 then inverts the test signal Tnor_red. NAND gate ND4 performs a NAND operation on the output of inverter IV14 and the output of NAND gate ND5.

Inverter IV15 inverts the output of NAND gate ND4. A latch composed of inverter IV16 and NOR gate NOR4 latches the output of inverter IV15 and is reset in accordance with the reset signal RST. The transfer gate T3 selectively outputs the output of the NOR gate NOR4 in accordance with the row address RA <6> and the output state of the inverter IV13.

The latch composed of the inverter IV17 and the NAND gate ND5 latches the output of the transfer gate T3 and is reset in accordance with the reset signal RST inverted by the inverter IV18. Inverter IV19 inverts the output of NAND gate ND5 and outputs row address RA <7>.

Referring to the operation of the present invention having such a configuration as follows.

First, the address output from the address buffer 200 is output to the row address decoder 400 via the multiplexer 320. When the auto-refresh signal AREF is activated in the command decoder 100, the T-flip-flop FF shown in FIG. 5 operates as a row address counter to sequentially generate row addresses RA <0:12>.

Here, the test signal Tnor_red input to the row address control unit 300 is a signal for refreshing the 8K row address by controlling all outputs of the 13 T-flip-flop FFs shown in FIG. 5 to a high level.

The T-flip-flop FF resets its output to a low level when the reset signal RST generated due to the termination of the power-up operation or the refresh operation of the normal or redundant cells is activated.

On the other hand, when the test signal Tnor_red is input with a high pulse and the auto-refresh signal AREF toggles from low to high, the outputs of the NOR3 NOR3 and NOR4, which are held at the high level by the reset signal RST, are all at a high level. do. Then, when the auto-refresh signal AREF transitions from high to low, the output becomes high level.

Therefore, the reverse level of the previous state is output from each T-flip-flop FF6 to FF11 every cycle in which auto-refresh is performed, so that the row address can be counted. That is, whenever one auto-refresh signal AREF is activated, the values of the T-flip flops FF6 to FF11, which are the row address counters, are sequentially increased from the row address RA <0>.

As such, when the test signal Tnor_red is activated, the outputs of the thirteen T-flip-flop FFs shown in FIG. 5 are all controlled at a high level to refresh the normal cell at the 8K th row address. When the auto-refresh signal AREF, which is the next refresh signal, is activated, the redundancy cell is immediately refreshed.

Meanwhile, the test signal Tred_nor controls only the output of the first group of flop flops FF6 to FF8 among the 13 T-flip flops FF shown in FIG. 5, and controls the outputs of the remaining second group of flop flops FF9 to FF11. It is a signal for refreshing the 128th redundancy row address cell by controlling at the low level. When the auto-refresh signal AREF, which is the next refresh signal, is activated, the normal cell is immediately refreshed.

As described above, the present invention generates the 8K th word line address without performing the 8K refresh using the test mode so that the normal cell can be directly moved from the refresh of the redundancy cell to the refresh operation of the redundancy cell. In addition, since the 128th redundancy word line address is generated without performing 128 refreshes, the refresh operation of the redundancy cell can be directly shifted to the normal cell refresh operation.

As described above, the present invention is to observe the timing that may be a problem in the period when the operation is switched to the redundancy / normal or normal / redundancy refresh when refreshing the row main cell and the row redundancy cell at the same time in the failure analysis By effectively reducing test cycles, you can reduce test time.

In addition, the refresh operation provides an effect of easily monitoring the timing at which the 8th and 128th refreshes are performed.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (19)

delete delete A command decoder for outputting an auto-refresh signal in accordance with a erase signal, a cas signal, a write enable signal, and a clock; An address buffer buffering the input address and providing the buffer to the following address controller; When the first test signal is activated while the auto-refresh signal is activated, the ROH addresses of the first group and the second group for performing the refresh of the redundancy cell are activated and output, and the normal when the second test signal is activated. The row address control unit for activating and outputting a row address of the first group for performing a cell refresh; A row address decoder configured to decode the row address applied from the row address control unit to activate word lines of the normal cell and the redundancy cell; The row address control unit, An internal address generator for generating the row address according to the auto-refresh signal, the first test signal and the second test signal, and an output address of the internal address generator or an output address of the address buffer to be selected and output; A semiconductor memory device comprising a multiplexer. The method of claim 3, wherein the internal address generator A first counter that sequentially generates the row addresses of the first group by countering the auto-refresh signal according to the first test signal and the second test signal; And And a second counter that sequentially generates the second group of row addresses by counting an output address of the first counter according to the first test signal. The method of claim 4, wherein the first counter And a plurality of T-flip flops that sequentially generate the first group of row addresses according to the auto-refresh signal, the first test signal, the second test signal, and the reset signal. . The method of claim 5, wherein each of the plurality of T-flip flop A first logic combining unit for logically combining the first test signal and the second test signal; A second logical combiner for logically combining the output and the output signal of the first logical combiner; First latch means for latching an output of said second logical combination portion and resetting in accordance with said reset signal; First selecting means for selectively outputting the output of the first latch means in accordance with the auto-refresh signal; And And second latch means for latching the output of said first selecting means to output said output signal and to reset in response to an inverted signal of said reset signal. 7. The semiconductor memory device according to claim 6, wherein the first logical combination unit comprises a first nodal gate that performs a no operation on the first test signal and the second test signal. The method of claim 6, wherein the second logical combination unit A first NAND gate NAND-operating the output of the first logical combination unit and the output signal; And And a first inverter for inverting the output of the first NAND gate. The method of claim 6, wherein the first latch means A second NOR gate for performing a NO operation on the output of the second logical combination unit and the reset signal; And And a second inverter that inverts the output of the second NOR gate and outputs it to an input terminal of the second NOR gate. 7. The semiconductor memory device according to claim 6, wherein said first selecting means comprises a first transfer gate. The method of claim 6, wherein the second latch means A second NAND gate NAND-operating the output of the first selection means and the inverted signal of the reset signal; And And a third inverter for inverting the output of the second NAND gate and outputting the inverted output to an input terminal of the second NAND gate. The method of claim 4, wherein the second counter And a plurality of T-flip flops that sequentially generate the second group of row addresses according to the auto-refresh signal, the first test signal, and the reset signal. The method of claim 12, wherein each of the plurality of T-flip flop A fourth inverter for inverting the first test signal; A third logic combining unit for logically combining the output of the fourth inverter and the output signal; Third latch means for latching an output of the third logical combination unit and being reset according to the reset signal; Second selection means for selectively outputting the output of the third latch means according to the output address of the first counter; And And fourth latch means for latching the output of the second selection means to output the output signal, and reset in accordance with the inverted signal of the reset signal. The method of claim 13, wherein the third logical combination portion A third NAND gate NAND-operating the output of the fourth inverter and the output signal; And And a fifth inverter for inverting the output of the third NAND gate. The method of claim 13, wherein the third latch means A third NOR gate for performing a NO operation on the output of the third logical combination unit and the reset signal; And And a sixth inverter inverting the output of the third NOR gate and outputting the inverted output to an input terminal of the third NOR gate. 14. The semiconductor memory device according to claim 13, wherein said second selecting means includes a second transfer gate. The method of claim 13, wherein the fourth latch means A third NAND gate NAND-operating the output of the second selection means and the inverted signal of the reset signal; And And a seventh inverter inverting the output of the third NAND gate and outputting the inverted output to an input terminal of the third NAND gate. The method of claim 3, wherein the row address control unit is set to a specific address for performing the refresh of the redundancy cells without performing the refresh of the normal cells when the row addresses of the first group and the second group are activated. A semiconductor memory device. The semiconductor memory device of claim 3, wherein the row address control unit is set to a specific address for performing the refresh of the normal cell without performing the refresh of the redundancy cell when the row address of the first group is activated. .

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