KR100847768B1 - Refresh controller in semiconductor memory device - Google Patents

Abstract

The present invention relates to a circuit for preventing malfunctions that may occur in a refresh control apparatus of a semiconductor memory device during a word line refresh test of a semiconductor memory device, and includes a bank including a plurality of normal word lines and a redundancy word line; An internal command signal generating means for generating a refresh signal and a bank active signal in response to an external command, and outputting an external address or an internal counting address as a row address signal in response to the refresh signal, and a wordline refresh test mode-the plurality of A test mode for sequentially refreshing the normal word lines and the redundancy word lines of the control unit; a refresh control means for outputting a redundancy word line refresh start signal at; and a response to the delay control test signal in the word line refresh test mode. Delay control means for selectively delaying the bank active signal, and driving the normal word line and the redundancy word line corresponding to the row address signal in response to an output signal of the delay control means and the redundancy word line refresh start signal. A semiconductor memory device having a word line driving means therefor is provided.

Word line refresh test, normal word line, redundancy word line

Description

Refresh control device for semiconductor memory devices {REFRESH CONTROLLER IN SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram showing a refresh control apparatus of a semiconductor memory device according to the prior art.

FIG. 2 is a timing diagram showing waveforms of signals used in the refresh control apparatus of the semiconductor memory device according to the related art shown in FIG.

3 is a block diagram illustrating an apparatus for controlling refresh of a semiconductor memory device according to an exemplary embodiment of the present invention.

4 is a circuit diagram illustrating in detail a delay control unit among components of a refresh control apparatus of a semiconductor memory device according to an embodiment of the present invention shown in FIG. 3.

FIG. 5 is a timing diagram showing waveforms of signals used in the refresh control apparatus of the semiconductor memory device according to the embodiment of the present invention shown in FIG.

* Explanation of symbols for the main parts of the drawings.

100, 300: signal generator 110, 310: refresh controller

120, 320: word line driver 130, 330: bank

340: delay control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a refresh control device for a semiconductor memory device. More particularly, the present invention relates to a malfunction that may occur in the refresh control device for a semiconductor memory device during a word line refresh test of the semiconductor memory device. It relates to a circuit for preventing.

In a semiconductor memory device, a dynamic RAM (hereinafter, referred to as "DRAM") generally uses a capacitor as a unit memory device for recording data, which is called a cell.

When storing '1' (or logic 'high') data in a cell, store the data of '0' (or logic 'low') by applying high potential to the cell In this case, data is recorded by applying a low potential to the cell and confining it.

By the way, in the ideal case of the capacitor constituting the cell, the accumulated charge must always be maintained unless the potential of the connection terminal of the capacitor is changed.

However, the actual capacitor has a characteristic that it is impossible to distinguish whether the recorded data is '1' or '0' because the stored charge is lost in the form of leakage current over time.

Therefore, in order to continuously maintain data, a process of periodically sensing, amplifying, and restoring data stored in a cell must be essentially performed. It is called (refresh).

Since the refresh operation is necessary to prevent the signal charge accumulated in the cell from being lost by the leakage current, it is necessary to test whether a normal refresh operation occurs in a plurality of cells belonging to the DRAM during DRAM production.

On the other hand, if any one of a plurality of cells belonging to the DRAM is defective, the DRAM cannot serve as a defective product.

However, as the density of DRAM increases, there is a high probability that defects will occur only in a small number of cells, but discarding it as a defective product is an inefficient treatment method that lowers the yield.

Therefore, a redundancy cell capable of replacing a defective cell is provided in advance in case a small amount of cells among the plurality of cells belonging to the DRAM fail.

That is, when a defect occurs in a small amount of cells among a plurality of cells belonging to the DRAM in the production process of the DRAM, a method of increasing the yield by replacing the defective cell by using a redundancy cell is used.

Since the redundancy cell may be replaced with a normal cell in the production process of the DRAM, the testing of the above-described refresh operation also includes a process of testing whether the refresh operation of the redundancy cell occurs normally.

However, since the redundancy cell should be distinguished from the normal cell, the control for driving the word line to which the normal cell belongs and the control for driving the word line to which the redundancy cell belongs should be distinguished.

Therefore, in the prior art, the refresh test of the cells belonging to the DRAM was performed in the following manner.

1 is a block diagram illustrating a refresh control apparatus for a semiconductor memory device according to the related art.

Referring to FIG. 1, the refresh control apparatus for a semiconductor memory device according to the related art has the following configuration.

A bank 130 including a plurality of normal word lines and a redundancy word line, and an internal command signal generator 100 for generating a refresh signal REF and a bank active signal BACT in response to an external command. And outputs an external address A <0:12> or an internal counting address as a row address signal XA <0:12> in response to the refresh signal REF, and a wordline refresh test mode-a plurality of normal words. In the test mode for sequentially refreshing the line and the redundancy word line, the refresh control unit 110 for outputting the redundancy word line refresh start signal TRWLREFX, and the bank active signal BACT and the redundancy word line refresh start signal TRWLREFX. ), A word line driver 120 for driving the normal word line and the redundancy word line corresponding to the row address signals XA <0:12>.

Here, the bank 130 is a concept introduced to increase the efficiency of an access time (tAC) of data in a DRAM, and is mainly one or more cell blocks that share timing control signals.

That is, the cells in the bank 130 share a data bus and share an address and a control signal line.

However, since a DRAM may be divided into a plurality of banks, each bank may have an independent row decoder and a column decoder, and may perform an independent DRAM operation.

Therefore, each bank 130 belonging to the DRAM is independent, so that while the data is read from one bank, the other bank performs a precharge or refresh operation or selects a word line by a new row address. Operation is possible.

That is, if one bank of the plurality of banks reads data through a sense amplifier, the other bank performs the operation of selecting a word line, thereby greatly reducing the row access time of the DRAM. have.

Since the respective banks 130 belonging to the DRAM operate independently, as shown in the drawing, each bank 130 can independently perform a refresh test, and independently a plurality of normal word lines and a plurality of redundancy words. Lines will be provided.

In the bank 130 shown in FIG. 1, 8k normal word lines are provided on the assumption that 13 row address signals XA <0:12> output from the refresh control unit 110 are 0 to 12, and 128 are provided. Assume that you have a redundancy word line.

The refresh control unit 110 selects a word line to be refreshed among the plurality of normal word lines and the redundancy word lines belonging to the bank 130 in response to the refresh signal REF, thereby providing the row address signal XA <0:12>. Output as

In addition, by controlling the level of the redundancy word line refresh start signal TRWLREFX in response to the word line refresh test mode signal TRWLREF controlling the entry of the word line refresh test mode, the plurality of redundancy word lines belonging to the bank 130 may be controlled. Controls what happens to the refresh operation.

The operation of the refresh control apparatus for a semiconductor memory device according to the related art based on the above-described configuration is as follows.

First, when the word line refresh test mode signal TRWLREF is activated, the refresh control device of the semiconductor memory device operates in the word line refresh test mode.

At this time, when the bank active signal BACT and the refresh signal REF are activated and output by the internal command signal generation unit 100, the refresh control unit 110 sends a response to the bank signal 130 in response to the refresh signal REF. The row address signal XA <0:12> indicating one of the plurality of normal word lines to which the word line belongs is outputted, and the word line driver 120 responds to the row active signal BACT in response to the bank active signal BACT. One of the plurality of normal word lines belonging to the bank 130 indicated by XA <0:12> is driven.

Thereafter, the above-described bank active signal BACT and refresh signal REF continue toggling to drive a plurality of normal word lines belonging to the bank.

When the plurality of normal word lines belonging to the bank are driven in this way, since the word line refresh test mode signal TRWLREF is activated, the refresh control unit 100 activates the redundancy word line refresh start signal TRWLREFX so that the word line driver 120 is activated. ) Controls to drive the redundancy word line of the bank 130.

That is, in response to toggling of the bank active signal BACT and the refresh signal REF input after the plurality of normal word lines belonging to the bank 130 are all driven, the plurality of redundancy word lines belonging to the bank 130 are generated. Drive.

Therefore, in the word line refresh test mode in which the word line refresh test mode signal TRWLREF is activated, after driving the plurality of normal word lines belonging to the bank 130, a plurality of redundancy word lines are sequentially driven. Proceed with the refresh test.

On the other hand, if the word line refresh test mode signal TRWLREF is inactivated and the refresh control device of the semiconductor memory device does not operate in the word line refresh test mode, redundancy may occur even after all the normal word lines belonging to the bank 130 are all driven. Since the word line refresh start signal TRWLREFX is continuously inactivated, a plurality of redundancy word lines belonging to the bank 130 are not driven.

FIG. 2 is a timing diagram illustrating waveforms of signals used in the refresh control apparatus of the semiconductor memory device according to the related art illustrated in FIG. 1.

Referring to FIG. 2, the signals used in the refresh control apparatus of the semiconductor memory device according to the related art are output from the external command signal generator 100 and the refresh control unit 110 and input to the word line driver 120. In response to the signals BACT and TRWLREFX and the input signals BACT and TRWLREFX, the signals NXE, MWLEN and RWLEN used inside the word line driver 120 and the word line driver 120 are output to the outside. Signals MWLB, RMWLB.

As shown in FIG. 2, the timing at which the above-described signals operate indicates the timing before driving the plurality of redundancy word lines after the driving of the plurality of normal word lines belonging to the bank 130.

That is, the waveforms of the aforementioned signals before and after the moment when the refresh control unit 110 activates the redundancy word line refresh start signal TRWLREFX to drive a plurality of redundancy word lines belonging to the bank 130 are illustrated.

By the way, the waveform of the signal shown in Figure 2 is a timing diagram showing the waveform of the signal used when the refresh control device of the semiconductor memory device according to the prior art operates under the following conditions.

First, it is assumed that the word line refresh test mode signal TRWLREF is activated so that the refresh control device of the semiconductor memory device operates in the word line refresh test mode.

That is, this is not applicable when the word line refresh test mode signal TRWLREF is inactivated and the refresh control device of the semiconductor memory device does not operate in the word line refresh test mode.

Referring to FIG. 2, the operation of the word line driver 120 is as follows.

When the bank active signal BACT is activated and input, the NXE signal is activated after a predetermined time passes, and the MWLEN signal and the MWLB signal are determined to be activated in response to the activation of the NXE.

That is, when the redundancy word line refresh start signal TRWLREFX is activated when the NXE signal is activated, the MWLEN signal and the MWLB signal are not activated.

Since the MWLB signal is inactive, the normal word line belonging to the bank 130 is not driven.

Conversely, if the redundancy word line refresh start signal TRWLREFX is deactivated when the NXE signal is activated, the MWLEN signal and the MWLB signal are activated.

Since the MWLB signal is activated, the normal word line belonging to the bank 130 is driven.

Accordingly, it can be seen that the normal word line belonging to the bank 130 is driven in response to whether the redundancy word line refresh start signal TRWLREFX is activated.

Here, the NXE signal and the MWLEN signal are signals processed inside the word line driver and are signals related to the normal word line driving operation.

When the redundancy word line refresh start signal TRWLREFX is activated and input, the RWLEN signal and the RMWLB signal are activated.

Since the RMWLB signal is activated, the redundancy word line belonging to the bank 130 is driven.

On the contrary, if the redundancy word line refresh start signal TRWLREFX is deactivated and input, the RWLEN signal and the RMWLB signal remain inactive.

Since the RMWLB signal is inactive, the redundancy word line belonging to the bank 130 is not driven.

Accordingly, it can be seen that the redundancy word line belonging to the bank 130 is activated in response to the redundancy word line refresh start signal TRWLREFX regardless of whether the normal word line is driven.

Here, the RWLEN signal is a signal processed inside the word line driver and is a signal related to the driving operation of the redundancy word line.

The timing at which the aforementioned signals are input to the word line driver 120 is as follows.

 First, the refresh command REF and the bank active signal BACT are simultaneously activated by the internal command signal generator 100.

At this time, the bank active signal BACT is immediately input to the word line driver 120 to activate the NXE signal after a predetermined time passes.

However, the refresh signal REF is input to the refresh control unit 110 and determines that the redundancy word line refresh start signal TRWLREFX is activated according to the activation state of the word line refresh test mode signal TRWLREF. After the REF is input to the refresh control unit 110, the level of the redundancy word line refresh start signal TRWLREFX is determined and output after an unpredictable time, which means a random time.

Accordingly, the timing of activation of the NXE signal inside the word line driver 120 according to an unpredictable time taken after the refresh signal REF is input to the refresh control unit 110 until the redundancy word line refresh start signal TRWLREFX is output. The refresh control unit 110 may be faster or slower than an activation timing of the redundancy word line refresh start signal TRWLREFX.

Here, when the activation timing of the NXE signal inside the word line driver 120 is slower than the activation timing of the redundancy word line refresh start signal TRWLREFX input from the refresh control unit 110, the operation is normally performed.

However, when the activation timing of the NXE signal inside the word line driver 120 is earlier than the activation timing of the redundancy word line refresh start signal TRWLREFX input from the refresh control unit 110, the following problem occurs.

First, the MWLEN and MWLB signals are activated and output in response to the activation of the activated NXE signal earlier than the activation timing of the redundancy word line refresh start signal TRWLREFX.

Thereafter, when the redundancy word line refresh start signal TRWLREFX is activated and input to the word line driver, the MWLEN signal is deactivated, but the RWLEN signal and the RMWLB signal are activated while the MWLB signal is already activated.

Accordingly, since the normal word line belonging to the bank 130 is already driven at the timing at which the redundancy word line belonging to the bank 130-the timing at which the RMWLB signal is activated-the MWLB signal is already activated-the bank 130 A problem arises in that the redundancy word line belonging to C cannot be driven.

In addition, the bank 130 is a state in which any word line of the plurality of normal word lines is driven in response to the activation of the MWLB signal, the RMWLB signal is activated again to drive any one of the plurality of redundancy word lines Since it does not operate normally, a defect occurs.

That is, when the word line refresh start signal TRWLREFX is to be activated in the word line driver 130, the NXE signal is activated first to generate a glitch in the MWLEN signal, which causes the MWLB signal and the RMWLB signal to be simultaneously generated. When activated, a plurality of normal word lines are driven at a timing when a redundancy word line belonging to the bank 130 needs to be driven.

If the above-mentioned problem occurs, the word line refresh test cannot be completed, and the circuit inside the refresh control device of the semiconductor memory device must be modified.

Therefore, problems such as increased development costs and delayed development schedules due to test failures and circuit modifications occur.

The present invention has been proposed to solve the above problems of the prior art, and provides a circuit for preventing a malfunction that may occur in the refresh control apparatus of the semiconductor memory device due to the input timing of the bank active signal during the test mode operation. The purpose is.

According to an aspect of the present invention for achieving the above technical problem, a bank having a plurality of normal word lines and redundancy word lines; Internal command signal generating means for generating a refresh signal and a bank active signal in response to an external command; In response to the refresh signal, an external address or an internal counting address is output as a row address signal, and a word line refresh test mode is a test mode for sequentially refreshing the plurality of normal word lines and redundant word lines. Refresh control means for outputting a start signal; Delay control means for selectively delaying the bank active signal in response to a delay adjustment test signal in the word line refresh test mode; And word line driving means for driving the normal word line and the redundancy word line corresponding to the row address signal in response to the output signal of the delay control means and the redundancy word line refresh start signal. .

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

3 is a block diagram illustrating an apparatus for controlling a refresh of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the refresh control apparatus of the semiconductor memory device according to the embodiment of the present invention has the following configuration.

A bank 330 including a plurality of normal word lines and a redundancy word line, and an internal command signal generator 300 for generating a refresh signal REF and a bank active signal BACT in response to an external command. And outputs an external address A <0:12> or an internal counting address as a row address signal XA <0:12> in response to the refresh signal REF, and a wordline refresh test mode-a plurality of normal words. In the test mode to sequentially refresh the line and the redundancy word line-In response to the refresh control unit 110 for outputting the redundancy word line refresh start signal (TRWLREFX), and in response to the delay control test signal (TMREFINC) in the word line refresh test mode Delay control unit 340 for selectively delaying the bank active signal BACT, and output signal and redundancy word line refresh of the delay control unit 340 A word line driver 320 is provided to drive the normal word line and the redundancy word line corresponding to the row address signals XA <0:12> in response to the time signal TRWLREFX.

In the signal generation unit 300 when the refresh control apparatus of the semiconductor memory device according to the embodiment of the present invention is in the word line refresh test mode as compared to the refresh control apparatus of the semiconductor memory device according to the related art shown in FIG. 1. It can be seen that the delay control unit 340 is further provided to control the delay of the output bank active signal BACT by a predetermined time in response to the delay control test signal TMREFINC.

Based on the above configuration, the refresh control apparatus of the semiconductor memory device according to the embodiment of the present invention performs the following operations.

First, when the word line refresh test mode signal TRWLREF is activated, the refresh control device of the semiconductor memory device operates in the word line refresh test mode.

At this time, when the refresh signal REF is activated and output from the internal command signal generator 300, the refresh control unit 310 responds to any of the plurality of normal word lines belonging to the bank 330 in response to the refresh signal REF. The row address signals XA <0:12> indicating one word line are output.

In addition, when the bank active signal BACT is activated and output at the same timing as the refresh signal REF, the delay controller 340 delays the bank active signal BACT by a predetermined time in response to the delay adjustment test signal TMREFINC. Output BACTD or output BACTD without delay.

In this case, the word line driver 320 may select any one of a plurality of normal word lines belonging to the bank 330 indicated by the row address signals XA <0:12> in response to the output signal BACTD of the delay controller 340. Drive one word line.

Thereafter, the above-described bank active signal BACT and refresh signal REF continue toggling to drive a plurality of normal word lines belonging to the bank.

When the plurality of normal word lines belonging to the bank are driven in this way, since the word line leaf refresh test mode signal TRWLREF is activated, the refresh control unit 300 activates the redundancy word line refresh start signal TRWLREFX to activate the word line driver ( 320 controls to drive the redundancy word line of the bank 330.

That is, in response to toggling of the bank active signal BACT and the refresh signal REF input after the plurality of normal word lines belonging to the bank 330 are all driven, the plurality of redundancy word lines belonging to the bank 330 may be generated. Drive.

Therefore, in the word line refresh test mode in which the word line refresh test mode signal TRWLREF is activated, after driving the plurality of normal word lines belonging to the bank 330, a plurality of redundancy word lines are sequentially driven. Proceed with the refresh test.

On the other hand, if the word line refresh test mode signal TRWLREF is inactivated and the refresh control device of the semiconductor memory device does not operate in the word line refresh test mode, redundancy may occur even after all the normal word lines belonging to the bank 330 are all driven. Since the word line refresh start signal TRWLREFX is continuously inactivated, a plurality of redundancy word lines belonging to the bank 330 are not driven.

However, in the above-described refresh control apparatus of a semiconductor memory device, the delay controller 340 does not always delay the bank active signal BACT input in the word line refresh test mode as follows. .

In the above-described refresh control apparatus of a semiconductor memory device, the NXE signal generated in the word line driver 320 is activated before the redundancy word line start signal TRWLREFX in response to the bank active signal BACT. The reason for this is that the time taken for the redundancy word line refresh start signal TRWLREFX to be output after the refresh signal REF is input to the refresh control unit 110 cannot be predicted.

However, in some cases, the NXE signal generated inside the word line driver 320 may be activated before the redundancy word line start signal TRWLREFX in response to the bank active signal BACT. It may not occur.

That is, the above-described problem does not always occur when the test is performed in the word line refresh test mode.

The bank active signal BACT is not only controlling the activation of the NXE signal generated inside the word line driver 320 but is also a signal for controlling the on / off operation of the bank 330.

Therefore, when the bank active signal BACT is delayed and input to the word line driver 320, the operation of the bank 330 is delayed by the delayed time.

Therefore, if the delay control unit 340 always delays and outputs the bank active signal BACT, the problem caused by the refresh control apparatus of the semiconductor memory device according to the related art described above may be solved. Can be.

If the above-mentioned problem occurs in the word line refresh test operation in the word line refresh test mode due to the aforementioned reasons, the delayed test mode signal is activated to delay and output the bank active signal BACT by a predetermined time. Solve it.

On the other hand, if the above-mentioned problems do not occur in the word line refresh test operation in the word line refresh test mode, the delay control test mode signal may be activated to perform the test without delaying the bank active signal BACT by a predetermined time. Proceed.

FIG. 4 is a circuit diagram illustrating in detail a delay controller among components of a refresh control apparatus of a semiconductor memory device according to an exemplary embodiment of the present invention shown in FIG. 3.

Referring to FIG. 4, the refresh control apparatus for a semiconductor memory device according to an exemplary embodiment of the present invention may include a delay unit 341 receiving and delaying a bank active signal BACT and a delay in response to a delay adjustment test signal TMREFINC. A selector 345 for selecting and outputting one of the output signal of the unit 341 and the bank active signal BACT is provided.

FIG. 5 is a timing diagram showing waveforms of signals used in the refresh control apparatus of the semiconductor memory device according to the embodiment of the present invention shown in FIG.

Referring to FIG. 5, signals used in the refresh control apparatus of the semiconductor memory device according to an exemplary embodiment of the present invention are output from the external command signal generator 300, the delay controller 340, and the refresh controller 310 to be worded. Signals BACTD and TRWLREFX input to the line driver 320 and signals NXE, MWLEN and RWLEN used in the word line driver 320 in response to the input signals BACTD and TRWLREFX, and word lines. The signals MWLB and RMWLB are output to the outside of the driver 320.

As shown in FIG. 5, the timing at which the aforementioned signals operate includes a timing before driving a plurality of redundancy word lines after all of the plurality of normal word lines belonging to the bank 330 are driven.

That is, the waveforms of the above-described signals before and after the moment when the redundancy word line refresh start signal TRWLREFX is activated by the refresh control unit 310 to drive a plurality of redundancy word lines belonging to the bank 330 are illustrated.

By the way, the waveform of the signal shown in Figure 5 is a timing diagram showing the waveform of the signal used when the refresh control device of the semiconductor memory device according to an embodiment of the present invention operates under the following conditions.

 First, it is assumed that the word line refresh test mode signal TRWLREF is activated so that the refresh control device of the semiconductor memory device operates in the word line refresh test mode.

That is, this is not applicable when the word line refresh test mode signal TRWLREF is inactivated and the refresh control device of the semiconductor memory device does not operate in the word line refresh test mode.

In addition, it is assumed that the delay control test signal is activated so that the delay control unit 340 delays and outputs the bank active signal for a predetermined time.

The operation of the word line driver 320 will now be described with reference to FIG. 5.

Since the output signal of the delay controller 340 is delayed for a predetermined time tD and output, the delayed signal 340 is activated later than the redundancy word line refresh start signal TRWLREFX.

This means that the NXE signal activated in response to the output signal of the delay controller 340 is always activated later than the RWLEN signal activated in response to the redundancy word line refresh start signal TRWLREFX.

Therefore, the MWLEN signal and the MWLB signal for controlling the driving of the plurality of normal word lines belonging to the bank 330 in response to NXE are not activated.

On the other hand, the RWLEN signal and the RMWLB signal for controlling the driving of the plurality of redundancy word lines belonging to the bank 330 are activated in response to the redundancy word line refresh start signal TRWLREFX.

As described above, when the word line refresh test mode is operated in the refresh control device of the semiconductor memory device, the activation time of the bank active signal BACT is higher than the activation time of the word line refresh start signal TRWLREFX. Since it is controlled to be late, a malfunction in which the normal word line is driven does not occur at a timing at which the redundancy word line belonging to the bank 330 needs to be driven.

In addition, since the bank active signal BACT may be selectively controlled according to the delay control test signal TMREFINC, and the above-described problem occurs during the operation of the word line refresh test mode in the refresh control device of the semiconductor memory device. May be optionally applied.

Therefore, if the above-mentioned problem does not occur during the word-line refresh test, the word-line refresh test can be completed relatively quickly. If the above-mentioned problem occurs, the circuit of the refresh control device of the semiconductor memory device is not modified. The word line refresh test can be performed instead.

That is, it is possible to prevent an increase in development costs and a delay in development schedule, which have been a problem in the related art.

Since the activation time of the bank active signal BACT is controlled later than the activation time of the word line refresh start signal TRWLREFX during the word line refresh test mode operation in the refresh control apparatus of the semiconductor memory device, the bank 330 is controlled. The malfunction that the normal word line is driven does not occur at the timing at which the redundancy word line belonging to) is to be driven.

In addition, since the bank active signal BACT may be selectively controlled according to the delay control test signal TMREFINC, and the above-described problem occurs during the operation of the word line refresh test mode in the refresh control device of the semiconductor memory device. May be optionally applied.

Therefore, when the above-described problem does not occur during the word-line refresh test, the word-line refresh test can be completed relatively quickly. When the above-mentioned problem occurs, the circuit of the refresh control device of the semiconductor memory device is not modified. The word line refresh test can be performed instead.

That is, it is possible to prevent an increase in development costs and a delay in development schedule, which have been a problem in the related art.

Claims (5)

A bank having a plurality of normal word lines and a redundancy word line; Internal command signal generating means for generating a refresh signal and a bank active signal in response to an external command; In response to the refresh signal, an external address or an internal counting address is output as a row address signal, and a word line refresh test mode is a test mode for sequentially refreshing the plurality of normal word lines and redundant word lines. Refresh control means for outputting a start signal; Delay control means for selectively delaying the bank active signal in response to a delay adjustment test signal in the word line refresh test mode; And Word line driving means for driving the normal word line and the redundancy word line corresponding to the row address signal in response to the output signal of the delay control means and the redundancy word line refresh start signal. A semiconductor memory device having a. The method of claim 1, The delay control means, And a delay unit for delaying the bank active signal by a predetermined time, and a multiplexer for selectively outputting the bank active signal or an output signal of the delay unit in response to the delay control test signal. . The method of claim 1, The delay control means, In the word line refresh test mode, when the delay control test signal is activated, the bank active signal is delayed and output for a predetermined time, and when the delay control test signal is inactivated, the semiconductor memory is output. device. The method of claim 1, The word line driving means, And when the output signal of the delay control means is activated and the redundancy word line refresh start signal is deactivated, the plurality of normal word lines are driven. The method of claim 1, The word line driving means, And a plurality of redundancy word lines when the output signal of the delay control means is activated and the redundancy word line refresh start signal is activated.

Images