KR100819648B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device having an active column pulse control circuit that performs a mask operation of an active column pulse when performing a data input / output mask (DQM).

In order to significantly reduce power consumption of the entire memory device by removing signals generated in the same manner as the operation of the actual memory device even when performing the data input / output mask,

Considering the CAS latency and the DQM latency, the DQM signal input masks the active column pulses in which the corresponding DQM operation occurs.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram showing a portion of a semiconductor memory device according to the prior art.

2 is a block diagram illustrating a portion of a semiconductor memory device according to an embodiment of the present invention.

3 is a circuit diagram showing an active column pulse control circuit according to an embodiment of the present invention.

4 is a timing diagram showing unnecessary operations in a semiconductor memory device of the prior art.

5 is a timing diagram illustrating that unnecessary operations are removed in a semiconductor memory device according to an embodiment of the present invention.

6 is a timing diagram illustrating an active column pulse to be masked during a write operation according to an embodiment of the present invention.

7 is a timing diagram illustrating active column pulses to be masked according to CAS latency in a read operation according to an embodiment of the present invention.

8 is a waveform diagram comparing current consumptions of a semiconductor memory device according to an embodiment of the present invention during a write operation;

9 is a waveform diagram comparing current consumptions of a semiconductor memory device according to an embodiment of the present invention and a prior art semiconductor memory device during a read operation;

<Description of Symbols for Major Parts of Drawings>

CTRL: control command ADDR: address

AYP: Active Column Pulse CASP: CAS Active Pulse

ICASP: Internal CAS Active Pulse WTRDZ: Write / Read Signal

LAY: local column address

IOSASTB: I / O sense amplifier strobe signal

BWEN: Block write enable signal WDQM: Write DQM signal

RDQM: Read DQM signal YI: Column select signal

LIO: Local I / O Signal AT_COL: Column Address

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an active column pulse which is a basis for generating a control signal, a precharge and potential equalization signal, or an internal address signal generated in an entire semiconductor memory device during a data input / output mask operation. The present invention relates to a semiconductor memory device having an active column pulse control circuit capable of significantly reducing the current consumption in the semiconductor memory device by masking the occurrence of?

1 is a block diagram illustrating a part of a general semiconductor memory device. Hereinafter, the operation of the conventional semiconductor memory device will be described focusing on the operation during the data input / output mask.

Input / output data DQ, address ADDR, and control commands CTRL (e.g., / CS, / RAS, / CAS, / WE) are input to the address buffer 10 and the command decoder 20, respectively. The input control command CTRL is decoded, and a CAS active pulse (CASP) and an internal CAS active pulse (ICASP), and a write / read signal WTRDZ indicating a write / read operation are output. The CAS active pulse signal CASP is a signal that is activated based on various control commands CTRL input to the command decoder 20, and the internal CAS pulse signal ICASP is an internal clock continuously during a bursting operation. It is a CAS active pulse generated in synchronization with the signal iCLK. The active column pulse generator 40 generates an active column pulse AYP based on the CAS active pulse signal CASP and the internal CAS pulse signal ICASP.

The address ADDR input to the address buffer 10 passes through a column address counter (not shown) in the address buffer 10, and then outputs a column address AT_COL or a row address AT_ROW (not shown).

The column address AT_COL output from the address buffer 10 and the active column pulse AYP output from the active column pulse generator are input to the column controller 50.

The column controller 50 is configured to perform various operations such as a local column address LAY, an I / O sense amplifier strobe signal IOSASTB, a block write enable signal BWEN, and the like based on the column address AT_COL and the active column pulse AYP. Enable or disable the signal.

The input / output data DQ is buffered in the data input / output buffer 30 and then input / output.                         

The write driver 60 receives data buffered in the data input / output buffer unit 30 based on the block write enable signal BWEN, and receives the memory cells through the local input / output line LIO and the bit line sense amplifier 90. Write data to The data read from the local input / output line LIO is amplified by the input / output sense amplifier 70 to output data to the data input / output buffer unit 30.

For example, when the state of the control signal CTRL input from the outside is / CS = L, / RAS = H, / CAS = L, / WE = H, the write command (WTRDZ = H) becomes / CS = L, When / RAS = H, / CAS = L, and / WE = L, the read command (WTRDZ = L) becomes the CAS active pulse (CASP) and the internal CAS active pulse (ICASP).

When the write / read signal WTRDZ becomes high (hereinafter, H) level so that the write operation WRITE is performed, block write enable output from the column control circuit unit 50 based on the active column pulse AYP. The signal BWEN is activated to enable the write driver 60, and the memory cell through the local I / O line LIO and the bit line sense amplifier 90 corresponding to data stored in the data input / output buffer 30. Data is written to (not shown).

When the write / read signal WTRDZ is at a low level so that the read operation READ is performed, after the data output from the memory cell is sensed by the bit line sense amplifier 90, the local I It is inputted to the input / output sense amplifier 70 through the / O line LIO, and amplified by the input / output sense amplifier 70 based on the I / O sense amplifier strobe signal IOSASTB output from the column control circuit unit 50. The data is output to the outside through the data input / output buffer 30.

When the data input / output mask signal DQM is input during such a write or read operation, the data input / output mask control unit 70 performs the write mask signal WDQM or the read mask signal RDQM based on the write / read signal WTRDZ. ) And the data input / output mask (DQM) operation is performed by disabling the write driver 60 or the data input / output buffer 30.

In the conventional semiconductor memory device, the column control circuit unit 50 continues to operate normally due to the address signal ADDR and the column active signal AYP even during the DQM operation. LAY, IOSASTB, BWEN, WDQM) are output, and current consumption due to the operation of the sense amplifier, precharging or equalization of the data path is generated regardless of the actual operation.

These unnecessary signals and operations are shown in FIG.

As shown, the operation of the bit line and the associated control signals (BIT1, BIT1Z, BIT2, BIT2Z, BWEN) when the write DQM signal WDQM is activated and when the read DQM signal RDQM is activated. , And operations of local I / O lines (LIO_RST, LIO, LIOZ) become unnecessary operations and signals.

The symbols BIT1 and BIT1Z are signals of bit line pairs to be masked, and the symbols LIO_RST are signals for precharging and equalizing the local I / O line (LIO).

The technical problem to be achieved by the present invention is to significantly reduce the current consumption by disabling the signals irrelevant to the operation of the actual memory device during the DQM operation.

In accordance with another aspect of the present invention, a semiconductor memory device includes a DQM controller configured to output a DQM signal for masking data input / output according to a corresponding DQM latency; An active column pulse generator for generating an active column pulse for activating the column; And based on an active column pulse and an address input, based on a column control unit controlling the operation of the corresponding column among the plurality of memory cells, a DQM signal, a CAS latency, and a write / read signal indicating execution of a write or read command. And an active column pulse controller for masking the output of the active column pulse output from the column pulse generator and outputting the mask to the column controller.

The active column pulse controller may further include a delay unit configured to delay the DQM signal by a difference between the DQM latency and the CAS latency when the DQM latency is greater than the CAS latency; A first passage for passing a delayed DQM signal; And a first mask unit that masks an active column pulse based on the DQM signal that is passed through.

Also, the first pass unit may determine whether the delayed DQM signal passes based on the write / read signal and the CAS latency.

The active column pulse controller may further include: a second passer configured to pass the DQM signal without delay when the DQM latency is equal to the CAS latency; And a second DQM control unit including a second mask unit that masks an active column pulse based on the passed DQM signal.

Also, the second pass unit of the second DQM controller may determine whether the DQM signal passes based on the write / read signal and the CAS latency.                     

The active column pulse controller may further include: a third pass portion for passing a fixed level signal of a high level or a low level when the DQM latency is smaller than the CAS latency; And a third DQM controller including a third mask unit that masks an active column pulse based on the fixed level signal passed.

In addition, the third pass unit may determine whether the fixed level signal passes based on the write / read signal and the CAS latency signal.

In addition, two or more of the first to third DQM controllers may be commonly connected to the mask means in parallel.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram illustrating a portion of a semiconductor memory device according to an embodiment of the present invention.

As shown, the semiconductor memory device according to an embodiment of the present invention detects that the CAS latency CLn and the DQM signal are input and writes with an internal DQM signal IDQM that is internally activated at the corresponding DQM latency. And an active column pulse controller 100 for masking the active column pulse AYP output from the active column pulse generator 40 based on the / read signal WTRDZ and outputting the mask to the column controller 50.

6 is a timing diagram illustrating a case in which a DQM signal is applied during a write operation of a semiconductor memory device according to an exemplary embodiment of the present invention.

In the illustrated embodiment, assuming that the DQM latency (clock time at which data input / output is masked after inputting the DQM signal) is set to 0, the data D1 of the clock on which the DQM signal DQM is activated is masked. Thus, as shown, the second active column pulse 62 to which the DQM signal DQM is applied should be masked.

7 is a timing diagram illustrating a case in which a DQM signal DQM is applied during a read operation according to an embodiment of the present invention.

In the illustrated embodiment, assuming that the DQM latency in the read operation is set to 2, it is determined which column active signal AYP should be masked according to the CAS latency CL. That is, data Q2, Q5, and Q9 after two clock cycles are masked at the clock at which the DQM signal DQM is activated.

As shown, when the DQM signal is activated at the second clock and the CAS latency is 1 (CL1), the third column active signal 72 is masked so that the data Q2 is masked and the CAS latency is 2 In the case of (CL2), since the DQM latency and the CAS latency are the same, the second column active signal 74 is masked and the data Q5 is masked.

When the CAS latency is 3 (CL3), the first column active signal 76 should be masked, but the first active column pulse AYP is activated before the DQM signal DQM is applied, and thus masking is impossible. That is, when the CAS latency is greater than the DQM latency, according to the present invention, the DQM operation is inevitably performed in the prior art without masking the active column pulse AYP.

3 is a circuit diagram illustrating an active column pulse controller according to an exemplary embodiment of the present invention, and is configured to perform the operation as described above.                     

That is, when the read operation is performed and the CAS latency is smaller than the DQM latency, when the DQM latency is the same as the CAS latency or when the write operation is performed, and when the read operation is performed and the CAS latency is larger than the DQM latency, As configured, various embodiments may be possible by the same principle.

The CAS latency signal CL1 is activated at H level when CAS latency is 1, the CAS latency signal CL2 is activated at H level when CAS latency is 2, and the CAS latency signal CL3 is 3 at CAS latency. Is activated at the H level.

When the write operation is performed, the write / read signal WTRDZ of FIG. 2 becomes H level, and when the read operation READ is performed, the write / read signal WTRDZ of FIG. 2 becomes L level.

The internal DQM signal IDQM is a signal passing through a DQM buffer (not shown) in the DQM control unit of FIG. 2 and becomes H level when the DQM operation is performed according to the DQM latency.

The active column pulse AYP generated by the active column pulse generator 40 may be configured based on the internal DQM signal IDQM, the write / read signal WTRDZ, and the CAS latency signal CAS Latency. In order to be masked, the active column pulse controller 100 according to an embodiment of the present invention may include a first DQM controller 110 and a CAS latency of 2 in case a CAS latency is set to 1 and a read operation is performed. 2 DQM control unit 120 for the case where the write operation is performed, or CAS latency is set to 3 (CL3), the third DQM control unit 130 for the case where the read operation is performed, And a mask unit 140 for masking the active column pulse AYP based on the first to third DQM controllers 110, 120, and 130.

 The first DQM controller 110 may include a delay unit 102 for delaying the internal DQM signal IDQM, a transmission gate TG1 for synchronizing the delayed internal DQM signal IDQM with the internal clock signal ICLK, and a synchronized internal circuit. Inverters INV2 and INV3 that delay the clock signal ICLK, and the delayed internal DQM signal IDQM when the CAS latency signal CL1 is at H level and the write / read signal WTRDZ is at L level (READ) And a transmission gate TG2 passing through.

Therefore, when the CAS latency is 1 and a read operation is performed, the transmission gate TG2 passes the delayed internal DQM signal IDQM of H level.

The delayed internal DQM signal IDQM of the H level is inverted by the inverter INV7 and input to the first input of the NAND gate NAND3, and the active column pulse AYP generated by the active column pulse generator 40 is input. Since it is input to the second input of the NAND gate NAND3, the active column pulse AYP is masked to L level when the CAS latency is 1 and a read operation is performed, and is output as it is otherwise.

The second DQM control unit 120 transmits the transmission gate TG3 and the transmission gate through which the internal DQM signal IDQM passes when the CAS latency signal CL2 is H level or the write / read signal WTRDZ is H level. And a NOR gate (NOR) to which the CAS latency signal CL2 and the write / read signal WTRDZ are input to provide a control input of TG3.

When the CAS latency signal CL2 is at the H level or the write / read signal WTRDZ is at the H level, the internal DQM signal IDQM passed by the transmission gate TG3 is inverted in the inverter INV7, and the NAND gate is inverted. It is input to (NAND3).

Therefore, when the CAS latency is set to 2 or the write operation is performed, as shown in FIGS. 6 and 7, the active column pulse AYP is masked to the L level at the clock to which the DQM signal DQM is applied. Otherwise, the active column pulse (AYP) is output as it is.

When the CAS latency is set to 3 (CL3) and the read operation is performed, as described above, it is impossible to mask the active column pulse AYP before generation of the DQM signal DQM, and thus the DQM operation as in the prior art. This should be done.

Therefore, when the CAS latency signal CL3 is at the H level and the write / read signal WTRDZ is at the L level READ, the third DQM control unit 130 passes the fixed voltage Vss at the L level. And a transmission gate TG64. The passed L level voltage is inverted and output from the inverter INV7 and input to the NAND gate NAND3. Therefore, when the CAS latency signal CL3 is at the H level and the write / read signal WTRDZ is at the L level, the active column pulse AYP is not masked, and the write or read DQM signal WDQM is as in the prior art. Alternatively, the RDQM is input to the data input / output buffer 30 or the write driver 60 to perform the DQM operation.

The fixed voltage is set to H level, and an inverter may be added after the transmission gate TG4.

From the foregoing description, in view of the DQM latency and CAS latency, it will be apparent to those skilled in the art that the present invention can be variously applied.                     

In addition, the active column pulse control circuit of the present invention may be configured to mask the active column pulse (AYP) only during a write operation, or may be configured to mask the active column pulse (AYP) only during a read operation. Will be self-explanatory.

In addition, it will be apparent that any one or two of the first to third mask controllers may be selectively employed.

5 is a timing diagram illustrating states of various signals in a semiconductor memory device according to an embodiment of the present invention.

Compared with FIG. 4, it can be seen that all unnecessary internal operations have disappeared.

That is, since the active column pulse AYP is masked in the corresponding clock period according to the input of the DQM signal, the column operation or signals generated based on the active column pulse AYP are disabled. That is, the column select signal YI is in a disabled state, and the bit line sense amplifier 90 does not transfer data to the local I / O line LIO, and precharges the local I / O line LIO. Since the potential equalization is not performed and the I / O sense amplifier strobe signal IOSASTB is disabled, the input / output sense amplifier 70 does not operate, thereby reducing current consumption.

In the actual experiment, we experienced 30% reduction in current consumption during write operation and 20% reduction during write operation. When excluding the power consumed in the data input / output buffer 30, the reduction of current consumption by 45% in the entire memory device was achieved. Occurred. This is illustrated in FIGS. 8 and 9.

 According to the present invention, by masking the active column pulses during the DQM operation, internal operations and signals generated based on the active column pulses are not generated, thereby greatly reducing current consumption.

Claims (9)

DQM control means for outputting a DQM signal for masking data input / output according to a corresponding DQM latency; Active column pulse generating means for generating an active column pulse for activating the column; Column control means for controlling the operation of each column according to the CAS latency of the corresponding column among a plurality of memory cells based on the active column pulse and the address input; And An active masking the output of the active column pulse output from the active column pulse generating means based on the DQM signal, the CAS latency, and a write / read signal indicating execution of a write or read command, and outputting the mask to the column control means And a column pulse control means. The method of claim 1, The active column pulse control means, Delay means for delaying the DQM signal by the difference between the DQM latency and the CAS latency when the DQM latency is greater than the CAS latency; First passing means for passing the delayed DQM signal; And a first DQM control unit having first mask means for masking the active column pulse based on the passed DQM signal. The method of claim 2, And the first DQM controller further includes an internal clock signal synchronizing means for synchronizing the delayed DQM signal with an internal clock signal. The method of claim 2, And the first passing means determines whether the delayed DQM signal passes based on the write / read signal and the CAS latency. The method of claim 1, The active column pulse control means, Second passing means for passing the DQM signal without delay when the DQM latency is equal to the CAS latency; And second DQM control means having a second mask means for masking the active column pulse based on the passed DQM signal. The method of claim 5, wherein And the second passing means of the second DQM controller determines whether the DQM signal passes based on the write / read signal and the CAS latency. The method of claim 1, The active column pulse control means, Third passing means for passing a high level or low level fixed level signal when the DQM latency is less than the CAS latency; And a third DQM control unit having third mask means for masking the active column pulse based on the passed fixed level signal. The method of claim 7, wherein And the third passing means determines whether the fixed level signal passes based on the write / read signal and the CAS latency signal. delete

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