KR100818097B1 - A voltage generator - Google Patents

A voltage generator Download PDF

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KR100818097B1
KR100818097B1 KR1020060096609A KR20060096609A KR100818097B1 KR 100818097 B1 KR100818097 B1 KR 100818097B1 KR 1020060096609 A KR1020060096609 A KR 1020060096609A KR 20060096609 A KR20060096609 A KR 20060096609A KR 100818097 B1 KR100818097 B1 KR 100818097B1
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South Korea
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signal
pumping
control
voltage
operation signal
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KR1020060096609A
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Korean (ko)
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고한석
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Abstract

A voltage generator is provided to improve a peak voltage by reducing response time until a pumping part is controlled, by applying an operation signal of a detection part to an oscillator and the control part in common. According to a voltage generator for generating an internal voltage, a detection part(10) outputs an operation signal determining pumping operation by comparing a reference voltage with a generated voltage. An oscillator(20) generates a periodic clock signal by the operation signal. A control part(30) outputs a control signal controlling the pumping by the operation signal and the clock signal. A pumping part(40) performs the pumping by the control signal and feeds the generated voltage back to the detection part.

Description

전원 발생 회로{A voltage generator} Power generation circuit {A voltage generator}

도 1은 종래의 전압 발생 회로에 의해 생성되는 전압 파형도.1 is a voltage waveform diagram generated by a conventional voltage generation circuit.

도 2는 본 발명의 실시예에 따른 전압 발생 회로를 나타내는 블록도.2 is a block diagram illustrating a voltage generating circuit according to an embodiment of the present invention.

도 3은 도 2의 제어부를 나타내는 회로도.3 is a circuit diagram illustrating a control unit of FIG. 2.

도 4는 도 2의 펌프부를 나타내는 회로도. 4 is a circuit diagram illustrating a pump unit of FIG. 2.

본 발명은 반도체 메모리 회로에 관한 것으로, 보다 상세하게는, 피크 전압을 감소시키는 전압 발생 회로에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory circuits and, more particularly, to voltage generating circuits for reducing peak voltages.

일반적으로 전원 발생 회로는 디램(DRAM)의 동작에 필요한 내부 전압, 예를 들면, VPP, VBB, VBLP, VCORE 등을 생성하는 회로이다. In general, the power generation circuit is a circuit for generating internal voltages required for the operation of the DRAM (eg, VPP, VBB, VBLP, VCORE, etc.).

도 1은 종래의 전원 발생 회로에 의해 생성되는 전압 파형도이다. 1 is a voltage waveform diagram generated by a conventional power generation circuit.

도 1을 참조하여 종래 전원 발생 회로의 동작을 살펴보면, 검출부에서 현재 전압 VIN을 기준 전압 VREF과 비교하여 현재 전압 VIN이 기준 전압 VREF 이하로 떨어지면(T1) 동작 신호를 인에이블시켜 오실레이터를 동작시키고 오실레이터 신호에 의해 제어부에서 생성된 제어신호를 펌프부로 인가함으로써 펌핑 동작을 시작한 다(T2). Referring to FIG. 1, when an operation of a conventional power generation circuit is performed, the detection unit compares a current voltage VIN with a reference voltage VREF, and when the current voltage VIN falls below the reference voltage VREF (T1), enables the oscillator to operate the oscillator and operate the oscillator. The pumping operation is started by applying the control signal generated by the control unit to the pump unit by the signal (T2).

펌핑부에서 생성되는 전압은 검출부로 피드백되어 기준 전압 VREF와 비교하여 같아지면(T3) 동작 신호를 디스에이블시켜 오실레이터의 동작을 정지시키고 이에 따라 제어부에서 생성된 제어신호에 의해 펌프부의 동작이 멈춘다(T5).When the voltage generated by the pumping unit is fed back to the detection unit and is equal to the reference voltage VREF (T3), the operation signal is disabled to stop the operation of the oscillator, and thus the operation of the pump unit is stopped by the control signal generated by the control unit ( T5).

그러나, 종래의 전원 발생 회로는 검출부에서 현재 전압 VIN과 기준 전압 VREF를 비교하여 같을 때(T3)를 검출하고, 펌핑부의 동작이 멈추기까지(T5) 긴 응답시간(response time)이 소요된다. 즉, 검출부에서 현재 전압 VIN과 기준 전압 VREF를 비교하여 동작 신호를 출력하는데 소요되는 검출부 응답시간(D1)과 동작하는 오실레이터를 멈추게 하고 이에 따라 제어부에서 펌핑을 멈추는 신호를 발생하는데 소요되는 기생 동작 시간(D2)이 필요하다. However, the conventional power generation circuit compares the current voltage VIN and the reference voltage VREF at the detector to detect when it is the same (T3), and takes a long response time until the operation of the pump is stopped (T5). That is, the detection unit compares the current voltage VIN and the reference voltage VREF to stop the detection unit response time (D1) required to output the operation signal and the oscillator to operate, and accordingly the parasitic operation time required to generate the signal to stop the pumping. (D2) is required.

특히, 기생 동작 시간(D2)은 동작하는 오실레이터를 멈추는데 소요되는 시간이 큰 비중을 차지한다. 오실레이터는 검출부에서 인가되는 동작 신호에 의해 주기적인 펄스를 갖는 클럭을 생성하여 제어부로 인가하므로 동작 신호가 디스에이블되어더라 해당 주기 동안은 이를 반영하지 못하므로 기생 동작 시간이 발생한다. In particular, the parasitic operation time D2 is a large portion of the time taken to stop the oscillator operating. The oscillator generates a clock having a periodic pulse by the operation signal applied from the detection unit and applies the clock to the controller, so that the operation signal is disabled, but the parasitic operation time is not reflected during the period.

따라서, 검출부에서 동작 신호가 디스에이블되는 시점(T4)으로부터 소정시간 이후 오실레이터가 멈추므로 응답시간(D1 + D2) 동안 계속하여 펌핑부의 동작이 지속되어 원하는 기준 전압 VREF(A)보다 높은 피크 전압(C)을 발생하는 문제가 있다. Therefore, since the oscillator stops after a predetermined time from the time T4 at which the operation signal is disabled in the detection unit, the operation of the pumping unit is continued for the response time D1 + D2, so that the peak voltage (higher than the desired reference voltage VREF (A) is maintained. There is a problem that occurs C).

따라서, 본 발명의 목적은 검출부의 동작 신호를 오실레이터와 제어부에 공통으로 인가함으로써 펌핑부를 제어하기까지의 응답시간을 줄여 피크 전압을 개선 하는 전원 발생 회로를 제공하는 데 있다. Accordingly, an object of the present invention is to provide a power generation circuit that improves the peak voltage by reducing the response time until controlling the pumping unit by applying the operation signal of the detection unit to the oscillator and the control unit in common.

상기와 같은 목적을 달성하기 위한 전원 발생 회로는 기준전압과 발생전압을 비교하여 펌핑 여부를 결정하는 동작신호를 출력하는 검출부; 상기 동작신호에 의해 주기적인 클럭신호를 발생하는 오실레이터; 상기 동작신호와 상기 클럭신호에 의해 펌핑을 제어하는 제어신호를 출력하는 제어부; 및 상기 제어신호에 의해 펌핑을 수행하고 발생된 전압을 상기 검출부로 피드백하는 펌핑부;를 포함하여 구성됨을 특징으로 한다. The power generation circuit for achieving the above object includes a detector for outputting an operation signal for determining whether to pump by comparing the reference voltage and the generated voltage; An oscillator for generating a periodic clock signal by the operation signal; A control unit for outputting a control signal for controlling pumping by the operation signal and the clock signal; And a pumping unit performing pumping by the control signal and feeding back the generated voltage to the detection unit.

상기 제어부는 상기 클럭신호를 입력받아 상반된 위상을 갖는 2쌍의 제어신호를 생성하고, 상기 제어신호와 상기 동작신호를 논리조합하여 출력하는 것이 바람직하다.The control unit may receive the clock signal, generate two pairs of control signals having opposite phases, and output the logical combination of the control signal and the operation signal.

상기 제어부는 상기 각 제어신호와 상기 동작신호를 낸드결합하여 출력함이 바람직하다. The control unit preferably outputs the NAND-combined control signals and the operation signals.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 전압 발생 회로를 나타내는 블록도이다. 2 is a block diagram illustrating a voltage generator circuit according to an exemplary embodiment of the present invention.

도 2를 참조하면, 본 발명의 실시예에 따른 전압 발생 회로는, 현재 전압 VIN과 기준 전압 VREF를 비교하여 펌핑 여부를 결정하는 동작 신호(ppe)를 출력하는 검출부(10)와, 동작 신호(ppe)에 의해 주기적인 클럭 신호(osc)를 발생하는 오실레이터(20)와, 동작 신호(ppe)와 클럭 신호(osc)를 받아 펌프를 제어하는 제어신호(p1, p2, g1, g2)를 출력하는 제어부(30) 및 제어신호(p1, p2, g1, g2)에 의해 펌핑을 수행하여 전압을 생성하고 이를 검출부로 피드백하는 펌핑부(40)를 포함하여 구성된다. Referring to FIG. 2, the voltage generation circuit according to an exemplary embodiment of the present invention includes a detector 10 that outputs an operation signal ppe for determining whether to pump by comparing a current voltage VIN and a reference voltage VREF, and an operation signal ( The oscillator 20 generates a periodic clock signal osc by ppe), and outputs control signals p1, p2, g1, g2 that receive the operation signal ppe and the clock signal osc and control the pump. The control unit 30 and the control signal (p1, p2, g1, g2) by the pumping unit 40 to generate a voltage by feeding back to the detection unit is configured to include.

여기서, 검출부(10)와 오실레이터(20)는 당업계에 널리 알려진 회로이므로 그 구성 및 동작에 대한 설명은 생략하기로 한다.Here, since the detector 10 and the oscillator 20 are circuits well known in the art, a description of the configuration and operation will be omitted.

도 3을 참조하면, 제어부(30)는 오실레이터(20)로부터 클럭 신호(osc)를 입력받아 인버터에 의해 상반된 위상을 갖는 2쌍의 제어신호(<p1,p2>,<g1,g2>)를 생성한다. 다시말해, 클럭 신호(ocs)를 각각 2개의 인버터(<INV1, INV2>, <INV4, INV5>)에 의해 지연시켜 제어신호(p1, g2)를 생성하고, 클럭 신호(osc)를 각각 1개의 인버터(<INV3>, <INV6>)에 의해 반전시켜 제어신호(p2, g1)를 생성한다. 그리고, 검출부(10)으로부터 인가받은 동작 신호(ppe)와 제어신호(p1, p2, g1, g2)를 각각 낸드게이트(NAND1 내지 NAND4)를 통해 낸드결합하여 펌핑부(40)로 제공한다. Referring to FIG. 3, the controller 30 receives a clock signal osc from the oscillator 20 and outputs two pairs of control signals <p1, p2>, <g1, g2> having phases opposite to each other by the inverter. Create In other words, the clock signals ocs are respectively delayed by two inverters <INV1, INV2>, <INV4, INV5> to generate the control signals p1 and g2, and each of the clock signals osc is one. The inverters <INV3> and <INV6> are inverted to generate the control signals p2 and g1. Then, the operation signal ppe and the control signals p1, p2, g1, and g2 applied from the detection unit 10 are NAND-coupled through the NAND gates NAND1 to NAND4, respectively, and are provided to the pumping unit 40.

따라서, 제어부(30)는 동작 신호(ppe)가 인에이블되는 동안은 동작 신호(ppe)에 관계 없이 오실레이터(20)로부터 인가되는 클럭 신호(osc)에 의해 생성되는 제어신호(p1, p2, g1, g2)를 출력하고, 동작 신호(ppe)가 디스에이블될 때 즉각 이를 반영하여 오실레이터(20)로부터 인가되는 클럭 신호(osc)에 관계 없이 제어신호(p1, p2, g1, g2)를 출력함으로써 펌핑부(40)의 동작을 제어한다. Accordingly, the controller 30 controls the control signals p1, p2, and g1 generated by the clock signal osc applied from the oscillator 20 regardless of the operation signal ppe while the operation signal ppe is enabled. outputs the control signals p1, p2, g1 and g2 regardless of the clock signal osc applied from the oscillator 20 by outputting g2 and immediately reflecting the operation signal when the operation signal ppe is disabled. The operation of the pumping unit 40 is controlled.

도 4는 펌핑부(40)의 일예로 커플링 캡을 이용한 VPP 펌프를 나타내고 있다.4 shows a VPP pump using a coupling cap as an example of the pumping unit 40.

도 4를 참조하면, 펌핑부(40)는 VPP에 소스가 공통으로 연결되고 게이트가 상호 드레인에 래치된 PMOS 트랜지스터(P1, P2)와 외부전원 VEXT에 소스가 공통으로 연결되고 드레인이 PMOS 트랜지스터(P1, P2)의 드레인과 공통으로 연결된 NMOS 트랜지스터(N1, N2)를 포함하여 구성되며, 공통 드레인 노드(ND1, ND2)로 커플링 캡(C1, C2)을 통해 전달되는 제어신호(p1, p2)를 인가받고, NMOS 트랜지스터(N1, N2)의 게이트로 커플링 캡(C1, C2)을 통해 전달되는 제어신호(g1, g2)를 인가받는다. Referring to FIG. 4, the pumping unit 40 includes a PMOS transistor P1 and P2 having a source connected to the VPP in common, a gate latched to the drain, and a source connected to the external power supply VEXT in common, and a drain of the PMOS transistor ( NMOS transistors N1 and N2 connected in common with the drains of P1 and P2 are included, and control signals p1 and p2 are transmitted to the common drain nodes ND1 and ND2 through the coupling caps C1 and C2. ) And the control signals g1 and g2 transmitted through the coupling caps C1 and C2 to the gates of the NMOS transistors N1 and N2.

펌핑부(40)는 제어신호(g1, g2)가 펌핑 부트 스트래핑(boot strapping) 준비 동작인 프리차지(precharge) 시에 커플링 캡(C3, C4)으로 전위를 전달해서 NMOS 트랜지스터(N1, N2)를 열어주고, 제어신호(p1, p2)가 각각의 커플링 캡(C1, C2)을 통해 공통 드레인 노드(ND1, ND2)로 전달되어 전압 레벨이 부트 스트래핑된 후 전하(charge)를 PMOS 트랜지스터(P1, P2)를 통해 VPP로 전달하는 펌핑 동작을 수행한다. The pumping unit 40 transfers a potential to the coupling caps C3 and C4 when the control signals g1 and g2 are precharged in preparation for pumping boot strapping, and the NMOS transistors N1 and N2. ), The control signals p1 and p2 are transferred to the common drain nodes ND1 and ND2 through the respective coupling caps C1 and C2 so that the voltage is bootstrapped and the charge is transferred to the PMOS transistor. The pumping operation is performed to deliver VPP through (P1, P2).

따라서, 펌핑부(40)는 동작 신호(ppe)가 인에이블인 동안 제어부(30)에서 오실레이터(20)로부터 출력된 클럭 신호(osc)에 의해 생성되는 일정한 주기를 갖는 제어신호(p1, p2, g1, g2)에 상응하여 상기와 같은 펌핑 동작을 수행한다.Therefore, the pumping unit 40 may control the control signals p1, p2, and the like, which are generated by the clock signal osc output from the oscillator 20 by the controller 30 while the operation signal ppe is enabled. The pumping operation as described above is performed corresponding to g1 and g2).

그러나, 동작 신호(ppe)가 오실레이터(20)와 제어부(30)로 동시에 인가됨으로 동작 신호(ppe)가 디스에이블될 때(도 1의 T4), 제어부(30)는 오실레이터(20)로부터 출력되는 클럭 신호(osc)에 관계 없이 동작 신호(ppe)에 의해 모두 로우 상태의 제어신호(p1, p2, g1, g2)를 출력함으로 펌핑부(40)는 동작을 즉각 멈춘다. However, when the operation signal ppe is disabled because the operation signal ppe is simultaneously applied to the oscillator 20 and the control unit 30 (T4 in FIG. 1), the control unit 30 is output from the oscillator 20. The pumping unit 40 immediately stops the operation by outputting the control signals p1, p2, g1, and g2 in the low state by the operation signal ppe regardless of the clock signal osc.

따라서, 종래의 전원 발생 회로에서 오실레이터를 멈추고 이어서 제어부에서 펌핑을 멈추는 신호를 발생하는데 소요되는 기생 동작 시간(도 1의 D2)을 감소하게 되므로 펌핑부(40)의 동작 지속시간이 개선되어 피크 전압(도 1의 B)을 낮출 수 있 다. Therefore, since the parasitic operation time (D2 of FIG. 1) required to stop the oscillator in the conventional power generation circuit and then generate a signal that stops pumping in the control unit is reduced, the operation duration of the pumping unit 40 is improved to provide a peak voltage. (B in Fig. 1) can be lowered.

이와 같이, 본 발명에 실시예에 따른 전원 생성 회로는 검출부에서 출력되는 동작 신호를 오실레이터와 제어부로 동시에 인가하여 펌핑부를 제어하기까지의 응답시간을 감소시킴으로서 피크 전압을 개선한다. As described above, the power generation circuit according to the embodiment of the present invention improves the peak voltage by reducing the response time until controlling the pumping unit by simultaneously applying the operation signal output from the detector to the oscillator and the control unit.

따라서, 본 발명에 의하면, 검출부에서 출력되는 신호를 오실레이터와 제어부에 공통으로 인가하여 전압을 감지하고 펌핑 동작을 제어하기까지 소요되는 응답시간을 줄인 전원 발생 회로를 제공함으로써 피크 전압을 개선하는 효과가 있다. Therefore, according to the present invention, by applying a signal output from the detector to the oscillator and the controller in common, it is effective to improve the peak voltage by providing a power generation circuit that reduces the response time required to sense the voltage and control the pumping operation. have.

Claims (3)

내부전원을 생성하는 전원 발생 회로에 있어서, In a power generation circuit for generating an internal power source, 기준전압과 발생전압을 비교하여 펌핑 여부를 결정하는 동작신호를 출력하는검출부;A detector for comparing the reference voltage and the generated voltage and outputting an operation signal for determining whether to pump the pump; 상기 동작신호에 의해 주기적인 클럭신호를 발생하는 오실레이터;An oscillator for generating a periodic clock signal by the operation signal; 상기 동작신호와 상기 클럭신호에 의해 펌핑을 제어하는 제어신호를 출력하는 제어부; 및A control unit for outputting a control signal for controlling pumping by the operation signal and the clock signal; And 상기 제어신호에 의해 펌핑을 수행하고 발생된 전압을 상기 검출부로 피드백하는 펌핑부;A pumping unit performing pumping by the control signal and feeding back the generated voltage to the detection unit; 를 포함하여 구성됨을 특징으로 하는 전원 발생 회로.Power generation circuit, characterized in that configured to include. 제 1 항에 있어서,The method of claim 1, 상기 제어부는 상기 클럭신호를 입력받아 상반된 위상을 갖는 2쌍의 제어신호를 생성하고, 상기 제어신호와 상기 동작신호를 논리조합하여 출력하는 것을 특징으로 하는 전원 발생 회로.And the control unit receives the clock signal, generates two pairs of control signals having opposite phases, and outputs a logical combination of the control signal and the operation signal. 제 2 항에 있어서,The method of claim 2, 상기 제어부는 상기 각 제어신호와 상기 동작신호를 낸드결합하여 출력하는 것을 특징으로 하는 전원 발생 회로.And the control unit outputs the NAND-combined control signals and the operation signals.
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JP2008000006A (en) * 2006-06-20 2008-01-10 Mitsubishi Agricult Mach Co Ltd Agricultural implement

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JP2008000006A (en) * 2006-06-20 2008-01-10 Mitsubishi Agricult Mach Co Ltd Agricultural implement

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US9230659B2 (en) 2013-06-26 2016-01-05 Samsung Electronics Co., Ltd. Nonvolatile memory device capable of reducing a setup/precharge speed of a bitline for reducing peak current and related programming method

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