KR100811261B1 - Method for fabricating storage node contact in semiconductor device - Google Patents

Abstract

A storage node contact forming method of a semiconductor device is provided. According to the present invention, a wafer edge exposure and removal (EBR / WEE) first process is performed such that bit line stacks are formed on a region other than the edge first region on the substrate on which the semiconductor device is formed. An insulating layer is formed on the bit line stacks, and an etch mask in the form of a line for forming a contact hole is formed, but is etched on a region other than the second region of the edge of the wafer which is equal to or extended to the first region. An etching mask is formed by using a wafer edge exposure and removal (EBR / WEE) second process so that the mask is formed. A contact hole is formed using an etch mask, and a storage node contact is formed.

Storage Node Contacts, Lifted, Wet Etch, Oxide Dissipation, SAC

Description

Method for fabricating storage node contact in semiconductor device

1 and 2 are cross-sectional views and plan views schematically illustrating an etching mask lifting phenomenon that may be caused in a typical method of forming a storage node contact.

3 to 12 are cross-sectional views schematically illustrating a method of forming a storage node contact of a semiconductor device according to an embodiment of the present invention.

FIG. 13 is a schematic plan view illustrating a wafer edge exposure and removal (EBR / WEE) range in a method of forming a storage node contact of a semiconductor device according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a storage node contact of a line type having improved lifting of an etching mask.

As the design rule of the semiconductor device is miniaturized to 100 nm or less, a photo process for forming a contact having a fine line width, for example, a contact electrically connected to a storage node of a capacitor. The exposure process using ArF light source is calculated | required. Nevertheless, the development of a method for forming a storage node contact at the required level of fine line width while using KrF light source instead of ArF light source has been attempted.

In particular, a method of forming a storage node contact having a fine line width, which is also required by a KrF exposure process, has been proposed by applying a line-type self aligned contact (SAC) method.

FIG. 1 is a cross-sectional view schematically illustrating an etching mask lifting phenomenon that may be caused by a method of forming a line-type storage node contact. FIG. 2 is a plan view schematically illustrating a cause of an etching mask lifting phenomenon that may be caused in a method of forming a line-type storage node contact. In FIG. 1, X-X 'denotes a cutting line intersecting a bit line in a direction in which a word line extends, ie, a bit line, and Y-Y' denotes a cross line between bit lines. It means a cutting line.

Referring to FIG. 1, a gate stack 20 as a word line on a semiconductor substrate or wafer 10 may include a gate dielectric layer (not shown), a gate 21, a capping layer 23, and a gate spacer 25. ) And the like. A first insulating layer 31 filling the gate stacks 20 may be formed, and a contact pad 40 penetrating the first insulating layer 31 may be formed.

The second insulating layer 33 covering the contact pad 40 is formed as the first interlayer insulating layer, and the bit line stack 50 is formed on the second insulating layer 33, the bit line 51 and the bit line cap layer. 53, the bit line spacer 55, and the like. A third insulating layer 35 as a second interlayer insulating layer filling the bit line stacks 50 is formed and planarized to expose the surface of the bit line cap layer 53.

The etching mask 60 for forming the line-type contact may be formed as a hard mask including a polysilicon layer. In this case, the etch mask 60 may be formed in a pattern of a line shape extending to cross the bit line 51. The third and second insulating layers 35 and 33 exposed by the etching mask 60 are sequentially SAC-etched to form contact holes 70 exposing the lower contact pads 40.

In this case, in order to further secure an area where the storage node contacts overlap with the storage node (not shown), the contact hole 70 performs a width expansion process for inducing the bit line 51 to extend further in the extending direction. Can be considered

For example, after the partial etching of the contact hole 70, the isotropic etching of the contact hole 70 may be considered to induce the width of the contact hole 70 to extend in the extending direction of the gate 21 relative to the etching mask 60. . The isotropic etching may be mainly performed by wet etching using an etching solution, for example, a hydrofluoric acid solution or a BOE, for the silicon oxide, which preferably forms the third insulating layer 25.

However, an unwanted phenomenon in which the etching mask 60 is lifted up may occur during the wet etching. It is confirmed that such a lifting phenomenon occurs mainly at the edge of the wafer 10. This is expected to be due to the absence of the bit line stack 50 at the bottom of the etching mask 60 at the edge portion of the wafer 10 and only the third insulating layer 35.

Referring to FIG. 2 together with FIG. 1, a first photoresist 57 for patterning a bit line etch mask, for example, a bit line cap layer 53, for a selective etching process for forming the bit line stack 50 may be a wafer. After being applied on (10), a wafer edge exposure and removal (EBR / WEE) process is performed to remove some of its edges. Accordingly, such first photoresist in some regions is selectively removed from the edge of the wafer 10. This is to prevent contamination and the like on the bit line 21 when patterning a metal layer such as the bit line 21.

However, the second photoresist 67 for patterning the etching mask 60 for the line-type contact is not substantially subjected to the EBR / WEE process after being applied on the wafer 10. It is recognized that the formation process of the storage node contact hole 70 is not seriously affected by the problem of recontamination caused by photoresist. Therefore, the EBR / WEE process is not performed to increase the net die. not.

However, when performing the process of expanding the contact hole 70 as previously considered, the wet process is preferably introduced into the intermediate step after the partial etching of the contact hole 70. In this wet process, a portion of the third insulating layer 35 below the etching mask 60 by wet in the state where the etching mask 60 and the third insulating layer 35 are in contact with each other in the edge region of the wafer 10. Is removed. Therefore, since the bit line stack 50 does not exist in the edge region of the wafer 10, the etch mask 60 is not supported by the bit line stack 50 and is excited in the space, and thus is excited. It is understood that the lift off phenomenon is caused.

The lift-off generation of the etching mask 60 may not only lower the yield but also cause contamination of the wet bath equipment used in the wet process, and thus, development of a method for improving the etching mask 60 is required. .

An object of the present invention is to provide a method for forming a line-type storage node contact that can prevent the etching mask from lifting during the wet etching process when the wet etching process is introduced to expand the contact hole for the storage node contact. There is.

One aspect of the present invention for achieving the above technical problem, the step of forming a bit line stacks on a region other than the edge first area on the substrate, and forming an insulating layer on the bit line stacks, the first Forming an etch mask on the insulating layer in the region other than the edge second region that is equal to or extending inwardly than the region, and etching the portion of the insulating layer exposed by the etch mask to form a contact hole A storage node contact forming method of a semiconductor device is provided.

The method may further include forming a second insulating layer under the bit line stack on the semiconductor substrate, wherein forming the contact hole may partially etch the insulating layer using the etching mask to form a partial contact hole. Forming a portion of the second contact layer by forming a portion of the second insulating layer; and forming a contact hole by etching the sidewall of the partial contact hole to extend a width thereof. have.

Extending the width of the partial contact holes may include wet etching the portion of the second insulating layer that forms the sidewalls and the bottom of the partial contact hole.

After expanding the width of the partial contact holes, the method may further include forming a protective layer including silicon nitride to protect sidewalls of the partial contact holes.

The forming of the storage node contacts may include forming the conductive layer filling the contact holes including conductive polysilicon, and planarizing the conductive layer to expose a surface of a cap layer of the bit line stack to separate the node. It may include.

Excluding the extension of the bit line stack to the first region may be performed by exposing and removing the first region.

The first region exposing and removing process may include applying a first photoresist layer and removing a portion of the first photoresist layer located in the first region.

Excluding the extension of the etch mask to the second region may be performed by exposing and removing the second region.

The exposing and removing of the second region may include applying a second photoresist layer and removing a portion of the second photoresist layer located in the second region of the second photoresist layer.

An etching mask having a line shape may be used as the etching mask for forming the contact hole.

According to the present invention, when the wet etching process is introduced to expand the contact hole for the storage node contact, the etching mask is prevented from being lifted during the wet etching process, thereby extending the storage node contact in the direction in which the bit line extends. A method of forming a line-type storage node contact can be provided.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it should not be construed that the scope of the present invention is limited by the embodiments described below. Embodiments of the invention are preferably to be interpreted as being provided to those skilled in the art to more fully describe the invention.

In the embodiment of the present invention, when forming a line-type storage node contact, after partially etching the contact hole for the contact, isotropic etching is introduced to extend the line width in the bit line direction, wherein the contact is isotropically etched. In order to prevent a defect of the etching mask used in forming the hole, a process of inducing the bit line stack under the etching mask is performed at the edge of the wafer.

To this end, the second wafer edge exposure introduced for the etching process introduced to form the storage node contact hole, rather than the first wafer edge exposure and removal (EBR / WEE) process in the process of patterning the bit line stack. And the removal range of the removal (EBR / WEE) process can be set to be relatively wider.

That is, the SNC EBR / WEE range may be set equal to or smaller than the bit line EBR / WEE range so that the range of the second photoresist for the storage node contact hole is set within the range of the first photoresist for bit line patterning. . In other words, the width of the edge portion removed from the bit line EBR / WEE may be set equal to or larger than the width of the edge portion removed from the SNC EBR / WEE.

3 to 12 are cross-sectional views schematically illustrating a method of forming a line-type storage node contact according to an exemplary embodiment of the present invention. 3 to 12, X-X 'denotes a cutting line extending in a word line, that is, a bit line, and Y-Y' denotes a bit line. It means the cutting line passing through. FIG. 13 is a plan view schematically illustrating a wafer edge exposure and removal range in a method of forming a line-type storage node contact according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the method for forming a contact according to an embodiment of the present invention may be performed by forming a self-aligned contact (SAC) using an etch mask having a line shape. Specifically, the gate stack 200 as a word line is formed on the semiconductor substrate or wafer 100. For example, a gate dielectric layer (not shown), a gate 210, a gate cap layer 230, a gate spacer 250, and the like are preferably included to extend in the word line direction. A first insulating layer 310 between the gate stacks 200, ie, filling the gap, is formed including an insulating material such as silicon oxide, and contacts as a connection contact penetrating the first insulating layer 310. The pad 400 is formed including a conductive polysilicon layer.

The second insulating layer 330 covering the contact pad 400 is formed of the first interlayer insulating layer ILD1, and the first conductive layer 510 for the bit line is formed on the second insulating layer 330. . The first conductive layer 510 may include a metal layer such as tungsten (W), and may include a titanium nitride layer (TiN layer, not shown) as a barrier metal layer or an adhesive layer under the first conductive layer 510.

The bit line cap layer 530, which may be used as a hard mask or an etching mask for patterning the first conductive layer 510 on the first conductive layer 510, preferably includes a second insulating layer 330 such as silicon nitride, or the like. It is formed by including an insulating material having an etching selectivity. Thereafter, a photo and etching process for patterning the first conductive layer 510 into a bit line is performed.

First, after applying the first photoresist layer 610 on the bit line cap layer 530, the first wafer edge exposure and removal (EBR / WEE) process is performed. The first wafer edge exposure and removal (EBR / WEE) process is preferably introduced to prevent contamination of the wafer 100 and / or contamination of the bit line.

In this case, as shown in FIG. 13, the first photoresist layer 610 removes a portion located in the edge first region 613 of FIG. 3 so as to remain only in the first range 611. The edge first region 613 in which the portion of the first photoresist layer 610 is removed by the first wafer edge exposure and removal (EBR / WEE) process may be set to a width of about 2.3 mm. As described above, a portion of the first photoresist layer 610 positioned at the edge first region 613 of the wafer 100 is removed, so that the bit line stack does not exist on the edge first region 613.

Referring to FIG. 4, a first photoresist pattern 615 is formed on the first photoresist layer 610 of FIG. 3 by performing a photo process, that is, an exposure and development process. Thereafter, the lower bit line cap layer 530 of FIG. 3 is selectively etched using the first photoresist pattern 615 as an etching mask to form a pattern of a cap layer 531 as a hard mask or an etching mask.

Thereafter, the first photoresist pattern 615 is preferably removed, and the pattern of the bit line 511 is selectively etched by using the cap layer 531 as an etching mask to selectively etch the lower first conductive layer (510 of FIG. 3). To form. As a result, the bit line stacks 500 including the bit line 511 and the cap layer 531 are formed. In this case, since the first photoresist layer 610 does not exist on the edge first region 613, the bit line stack 500 is also not formed.

Referring to FIG. 5, the bit line spacer 550 is formed on the sidewalls of the bit line 511 and the cap layer 531, preferably including silicon nitride, to complete the bit line stack 500, and the bit line stack 500. The third insulating layer 350, which fills the gaps, is formed as the second interlayer insulating layer ILD2.

In this case, the third insulating layer 350 may be formed using deposition of silicon oxide, and after the deposition, the surface is planarized by chemical mechanical polishing (CMP) to expose the upper surface of the bit line cap layer 531. It is preferable. This is to form individual contact holes in the SAC process by introducing an etch mask in the form of a line in the process of forming subsequent storage node contacts.

After the deposition of the HDP, BPSG, TEOS, and the like, the third insulating layer 350 may be planarized by CMP performed to finish polishing on the bit line cap layer 531.

Referring to FIG. 6, a layer 630 for an etch mask to be used in forming a contact hole for a storage node contact is formed. The layer 630 for the etching mask may be formed as a hard mask, and may include a polysilicon layer having an etching selectivity with silicon oxide or / and silicon nitride. At this time, the polysilicon layer may be deposited to a thickness of about 500 to 2000Å.

A second photoresist layer 650 is formed on the etching mask layer 630 to pattern the etching mask layer 630 as an etching mask. In this case, after applying the second photoresist layer 650, the second wafer edge exposure and removal (EBR / WEE) process is performed. The second wafer edge exposing and removing process (EBR / WEE) is preferably set so that the processing range is located inward compared to the first wafer edge exposing and removing process (EBR / WEE).

That is, as shown in FIG. 13, the second photoresist layer 650 removes a portion located in the edge second region (653 of FIG. 6) so that the second photoresist layer 650 remains only in the first range (651 of FIG. 13). The edge second region 653 in which the portion of the second photoresist layer 650 is removed by the second wafer edge exposure and removal (EBR / WEE) process may be set to be equal or wider than the first region 613. have. For example, the second region 653 may be set to be about 0 to 50% wider than the first region 613. When the edge first region 613 is set to a width of approximately 2.3 mm in the first wafer edge exposure and removal (EBR / WEE) process for the bit line, the second region 653 may be set to approximately 3.5 mm. have.

As such, a portion of the second photoresist layer 650 positioned at the edge second region 653 of the wafer 100 is removed, so that an etch mask is formed on the edge second region 653 to eventually form a contact hole. You will not.

Referring to FIG. 7, a second photoresist pattern (not shown) is formed on the second photoresist layer 650 of FIG. 6 by performing a photo process, that is, an exposure and development process, and the second photoresist pattern is formed. The etch mask selectively etches the layer 630 for the underlying etch mask to pattern the etch mask 635. Thereafter, the second photoresist pattern is preferably removed.

In this case, the etching mask 635 is patterned to have a line shape extending in a direction in which the word line extends by crossing the plurality of bit line stacks 500. Accordingly, a plurality of storage node contact holes may be formed in the bit line stack 500 in a region where the etch masks 635 are exposed.

In this case, not only the third insulating layer 350 is in contact with the lower portion of the etching mask 635, but the cap layer 531 of the bit line stack 500 is in contact with each other. This is because the processing range of the second wafer edge exposure and removal (EBR / WEE) process is set equal to or inward compared to the first wafer edge exposure and removal (EBR / WEE) process. Since the etch mask 635 is in contact with the bit line cap layer 531, the etch mask 635 is supported by the bit line stack 500 even if the lower third insulating layer 350 is removed in a subsequent process. Can be. Therefore, the phenomenon in which the etching mask 635 is lifted up can be preferably prevented.

Referring to FIG. 8, a portion of the third insulating layer 350 exposed to the etching mask 635 is selectively etched to form a partial contact hole 351. In this case, the etching process may be performed by partial etching that is controlled not to completely penetrate the third insulating layer 350, and may be performed by anisotropic dry etching. At this time, the etching process is etched by the bit line cap layer 531 or / and the bit line spacer 550 is performed by the SAC process.

9, a process of expanding the width of the partial contact hole 351 is performed. For example, portions of the third insulating layer 350 of the bottom and sidewalls of the partial contact hole 351 are etched by isotropic etching, for example, by wet etching using an etchant for an oxide such as HF or BOE to form the partial contact hole 351. Extend the width At this time, the expansion in the direction in which the word line is extended by the bit line stack 500 is limited, and the width in the bit line direction is extended by etching in the bit line direction in which the bit line stack 500 extends.

In forming the contact holes 352 having such an extended width, the etching mask 60 extends to the edge of the wafer 10 as shown in FIG. 1, and the bit line stack 50 is disposed below. Since it is not present, the end portion of the etching mask 60 may not be supported by the disappearance of the third insulating layer 35. Accordingly, the lift-off phenomenon of the etching mask 60 may occur.

In contrast, in the embodiment of the present invention as shown in FIG. 9, since the etch mask 635 is supported by the bit line stack 500, the lift-off phenomenon of the etch mask 635 is prevented.

Referring to FIG. 10, a protective layer 670 is formed to cover sidewalls and bottoms of the contact holes 352 having an extended width. The protective layer 670 is introduced to serve to protect the sidewalls of the contact hole 352 and the like during the subsequent etching process of the contact hole 352. Accordingly, the protective layer 670 may be formed to include a layer of silicon nitride capable of implementing an etching selectivity with the third insulating layer 350.

Referring to FIG. 11, the bottom of the contact hole 352 having an extended width exposed by the etch mask 635 is etched, and then the second insulating layer 630 is etched to lower the contact pad ( A contact hole 353 penetrating through the third and second insulating layers 650 and 630 is formed to be connected to 400. In this case, the etching process may be performed including anisotropic dry etching. In this case, a portion of the protective layer 670 of the bottom portion of the contact hole 352 having an extended width may be selectively exposed by the etching mask 635 to be removed by etching.

Referring to FIG. 12, after forming the second conductive layer filling the contact holes 353, the nodes are separated to expose the bit line cap layer 531 by performing an etch back or CMP. The storage node contact 700 is formed for each of the 353 units. In this case, the second conductive layer may include a conductive polysilicon layer.

Subsequently, although not shown in the drawings, a buffer layer for forming a capacitor is deposited on the contact 700 with an oxide of about 300 to 700 GPa, and a silicon nitride layer as an etch stop layer is about 500 to 1500 GPa, A form layer for forming a three-dimensional shape, for example, a cylinder shape, on the storage node is formed thereon. The storage node imparted with the three-dimensional shape by the template layer is formed to be aligned with the contact 700, and the dielectric layer and the plate node are formed on the storage node to complete the capacitor.

In this case, since the upper portion of the storage node contact 700 is implemented to have an extended width, the storage node contact 700 can secure a larger overlap margin with the storage node.

According to the present invention described above, when forming a contact hole for a storage node contact using a self-aligned contact (SAC) process using a line-type etching mask and an etch stop of the bit line stack, the line-type etching mask is raised. Can be effectively excluded and a wet etching can be performed to induce a widening of the upper portion of the contact hole. Accordingly, the line width of the upper portion of the contact hole may be further secured in a direction in which the bit line extends, thereby further securing an overlap margin between the storage node and the contact.

The second wafer edge exposed and removed region of the second photoresist layer in the photolithography process for the line etch mask is less than the first wafer edge exposed and removed region of the first photoresist layer in the photolithography process for bit line patterning. By setting it toward the wafer center, i.e., inward, it is possible to induce the bit line stack to be always under the etch mask.

Accordingly, even when the insulating layer under the etch mask is lost in wet etching for contact hole expansion, the etch mask is supported by the bit line stack, so that the etch mask can be effectively prevented from being lifted.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

Claims (10)

Forming bit line stacks on a region other than the edge first region on the substrate; Forming an insulating layer on the bit line stacks; Forming an etch mask on the insulating layer in a region other than the edge second region that is equal to or extended to the inside of the first region; And Forming a contact hole by etching the portion of the insulating layer exposed by the etching mask. The method of claim 1, Forming a second insulating layer under the bit line stack on the substrate; Forming the contact hole Forming a partial contact hole by partially etching the insulating layer using the etching mask; Etching the sidewalls of the partial contact hole to expand the width; And And selectively etching the portion of the second insulating layer exposed at the bottom of the partial contact hole to form the contact hole. The method of claim 2, Extending the width of the partial contact holes And wet etching the portion of the second insulating layer forming sidewalls and bottoms of the partial contact holes. The method of claim 2, After expanding the width of the partial contact holes And forming a protective layer for protecting the sidewalls of the partial contact hole, including silicon nitride. The method of claim 1, Forming the storage node contacts Forming a conductive polysilicon layer filling the contact holes; And And planarizing the conductive polysilicon layer to expose the surface of the bit line stack to separate the node. The method of claim 1, Forming the bit line stack in a region other than the first region by performing selective exposure and removal of the first region. The method of claim 6, Selective exposure and removal of the first region Applying a first photoresist layer; And And removing a portion of the first photoresist layer positioned in the first region of the first photoresist layer. The method of claim 1 Formation of the etching mask in a region other than the second region may be performed. And performing a selective exposure and removal of the second region. The method of claim 8, Selective exposure and removal of the second region is Applying a second photoresist layer; And And removing a portion of the second photoresist layer located in the second region of the second photoresist layer. The method of claim 1, The etching mask for forming the contact hole is a storage node contact forming method of a semiconductor device, characterized in that for using a line-type etching mask.

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