KR100806970B1 - Liquid crystal panel of line on glass type and method of fabricating the same - Google Patents

Abstract

The present invention provides a LOG type liquid crystal display panel and a method of manufacturing the same, which can reduce the line resistance of a LOG type gate low voltage transmission line supplying a gate low voltage to a storage line within a limited region.

The LOG type liquid crystal display panel of the present invention has a plurality of liquid crystal cells formed at the intersections of the gate lines and the data lines, and a gate on storage type which maintains the pixel voltage charged in each of the liquid crystal cells. An image display unit including a storage capacitor and a storage line for forming a storage capacitor of liquid crystal cells included in the first scan line; Line on glass type signal lines formed in an outer region of the image display unit to transmit driving signals required by drive integrated circuits for driving gate lines and data lines; The storage line is connected through a line connected to the line on glass type gate low voltage transmission line for supplying a gate low voltage among the line on glass type signal lines and insulated from the other line on glass type signal lines. .

Description

Line on glass type liquid crystal display panel and manufacturing method thereof {LIQUID CRYSTAL PANEL OF LINE ON GLASS TYPE AND METHOD OF FABRICATING THE SAME}             

1 is a plan view schematically showing the configuration of a conventional line on glass type liquid crystal display device.

FIG. 2 is an enlarged plan view of the line-on-glass type signal line group and storage line shown in FIG. 1;

3 is an enlarged plan view illustrating a line on glass type signal line group and a storage line in a liquid crystal panel according to an exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view of the line-on-glass signal line shown in FIG. 3 taken along line AA ′. FIG.

5A through 5C are cross-sectional views illustrating a method of manufacturing the line-on-glass signal line illustrated in FIG. 4.

<Description of Symbols for Main Parts of Drawings>

1: liquid crystal panel 2, 42: lower substrate

4: Upper board 8: Data TCP

10: data drive IC 12: data PCB                 

14: gate TCP 16: gate drive IC

18: data line 20: gate line

21: image display unit 22, 28: gate drive signal transmission group

24: data TCP input pad 25: data TCP output pad

26, 44: LOG signal line group 36, 50: gate metal pattern

30: gate TCP output pad 32, 46: first LOG pad

34, 48: 2nd LOG pad 38, 52: gate low voltage transmission line

40, 54: source / drain metal pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a line on glass type liquid crystal display panel and a manufacturing method thereof capable of minimizing line resistance of a line on glass type signal line formed on a liquid crystal panel.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying various driving voltages used in the liquid crystal display device. It has a supply part. The timing controller controls the driving timing of the gate driver and the data driver and supplies the pixel data signal to the data driver. The power supply unit generates driving voltages, such as a common voltage Vcom, a gate high voltage Vgh, and a gate low voltage Vgl, which are required in the liquid crystal display using the input power. The gate driver sequentially supplies the scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Among them, a data driver and a gate driver directly connected to the liquid crystal panel are integrated into a plurality of integrated circuits (ICs). Each of the integrated data drive IC and the gate drive IC is mounted on a tape carrier package (TCP) and connected to a liquid crystal panel by a tape automated bonding (TAB) method or mounted on a liquid crystal panel by a chip on glass (COG) method.

Here, the drive ICs connected to the liquid crystal panel in a TAB manner through TCP are interconnected with the control signals and DC voltages input from the outside through signal lines mounted on a printed circuit board (PCB) connected to the TCP. . In detail, the data drive ICs are connected in series through signal lines mounted on the data PCB, and are commonly supplied with control signals from the timing controller, pixel data signals, and driving voltages from the power supply unit. The gate drive ICs are connected in series through signal lines mounted on the gate PCB, and are commonly supplied with control signals from the timing controller and driving voltages from the power supply.

The drive ICs mounted on the liquid crystal panel in the COG method are interconnected in a line on glass (hereinafter, LOG) method in which signal lines are mounted on the liquid crystal panel, that is, the lower glass, and from the timing controller and the power supply. Control signals and driving voltages are supplied.

Recently, even when the drive ICs are connected to the liquid crystal panel by the TAB method, the liquid crystal display device can be further thinned by adopting the LOG method and removing the PCB. In particular, the gate PCB is removed by forming the signal lines connected to the gate drive ICs requiring relatively few signal lines on the liquid crystal panel in the LOG method. In other words, the TAB type gate drive ICs are connected in series through signal lines mounted on the lower glass of the liquid crystal panel, and are commonly supplied with control signals and driving voltage signals (hereinafter referred to as gate driving signals). do.

In practice, the liquid crystal display device in which the gate PCB is removed by using the LOG type signal wires has a plurality of data TCPs connected between the liquid crystal panel 1 and the liquid crystal panel 1 and the data PCB 12 as shown in FIG. 8, a plurality of gate TCPs 14 connected to the other side of the liquid crystal panel 1, data drive ICs 10 mounted on each of the data TCPs 8, and gate TCPs ( 14) and gate drive ICs 16 mounted on each.

The liquid crystal panel 1 is injected between the lower substrate 2 on which the thin film transistor array is formed, the upper substrate 4 on which the color filter array is formed, and the lower substrate 2 and the upper substrate 4 together with various signal lines. Containing liquid crystals. The liquid crystal panel 1 is provided with an image display area 21 composed of liquid crystal cells provided at each intersection of the gate lines 20 and the data lines 18 to display an image. Data pads extended from the data line 18 and gate pads extended from the gate line 20 are positioned in the outer region of the lower substrate 2 positioned at the outer portion of the image display area 21. In addition, in the outer region of the lower substrate 2, a LOG type signal line group 26 for transmitting gate driving signals supplied to the gate drive IC 16 is positioned.

A data drive IC 10 is mounted on the data TCP 8, and input pads 24 of the data TCP 8 and output pads of the data TCP 8 electrically connected to the data drive IC 10. 25 is formed. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12, and the output pads 25 of the data TCP 8 are the data pads on the lower substrate 2. And electrically connected. In particular, the first data TCP 8 is further formed with a gate drive signal transmission group 22 electrically connected to the LOG signal line group 26 on the lower substrate 2. The gate driving signal transmission group 22 supplies the gate driving signals supplied from the timing controller and the power supply unit to the LOG type signal line group 26 via the data PCB 12.

The data drive ICs 10 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 18 on the liquid crystal panel.

A gate drive IC 16 is mounted on the gate TCP 14, and the gate drive signal transmission line group 28 and the output pads 30 of the gate TCP 14 are electrically connected to the gate drive IC 16. Is formed. The gate driving signal transmission line group 28 is electrically connected to the LOG signal line group 26 on the lower substrate 2, and the output pads 30 are electrically connected to the gate pads on the lower substrate 2. .

The gate drive ICs 16 sequentially supply the scanning signal, that is, the gate high voltage signal VGH, to the gate lines 20 in response to the input control signals. In addition, the gate drive ICs 16 supply the gate low voltage signal VGL to the gate lines for a period other than a period during which the gate high voltage signal VGH is supplied.

The LOG signal line group 26 has a power supply such as a gate low voltage signal VGH, a power signal VCC, a gate high voltage signal VGH, and a ground voltage signal GND from the outside as shown in FIG. Signal lines for supplying each of the DC voltage signals supplied from the supply unit and the gate control signals supplied from the timing controller, such as the gate enable signal GOE, the gate shift clock signal GSC, and the gate start pulse GSP. It is composed. In addition, the LOG signal line group 26 further includes a signal line for supplying a common voltage VCOM from the power supply unit. The LOG signal line group 26 shown in FIG. 2 includes a first LOG pad group 32 connected to the data TCP 8 together with data pads to which the data signals D1, D2, ... are supplied. And a second LOG pad group 34 connected to the gate TCP 14 together with the gate pads to which the gate signals G1, G2, ... are supplied.

The LOG signal line group 26 is formed side by side in a fine pattern in a very limited narrow space, such as a gate and a data pad unit located in the outer region of the image display unit 21. The LOG signal lines of the LOG signal line group 26 are formed of the gate metal pattern 36 in the same manner as the gate lines 20. As the gate metal, a metal having a relatively large resistivity value (0.046), such as AlNd, is usually used. As the LOG signal line group 26 is formed as a fine pattern within a limited region and is composed of a gate metal having a relatively large resistivity value, the resistance is relatively high compared to the signal lines formed of copper foil on a conventional gate PCB. It will contain ingredients.

The line resistance of the LOG signal line group 26 can be reduced by increasing the line width, but it is difficult to increase the line width due to the limited space. Accordingly, the LOG signal line group 26 is designed to reduce the line resistance of the gate low voltage (VGL) transmission line 38 among them in a limited space. Since the gate low voltage VGL affects the capacity of the storage capacitor Cst, which maintains the pixel voltage charged in the liquid crystal cell, when the gate low voltage VGL decreases, the charged pixel voltage is variable, thereby reducing the image quality. Because it has a significant impact on. In order to reduce the line resistance, the gate low voltage transmission line 38 is formed outwardly as shown in FIG. 2 to form the shortest distance and is patterned to have the maximum line width even in a limited space.

As the LOG type gate low voltage transmission line 38 is located outside, the gate low voltage VGL supplied to the storage line GL0 forming the storage capacitor Cst on the first scan line of the image display unit 21 is formed. The transmission path inevitably becomes long. Specifically, the LOG type gate low voltage transmission line 38 that supplies the gate low voltage VGL to the storage line GL0 may include a first LOG connected between the first data TCP 8 and the first gate TCP 14. Type gate low voltage transfer line 38A and second LOG gate low voltage transfer line 38B connected between first gate TCP 14 and storage line GL0. Accordingly, the gate low voltage VGL is stored in the storage line through the first LOG gate low voltage transfer line 38A-> first gate TCP 14-> second LOG gate low voltage transfer line 38B. GL0). As the length of the LOG type gate low voltage transmission line 38 that supplies the gate low voltage VGL to the storage line GL0 is increased, the line resistance value (for example, 30Ω) increases. In addition, since the gate low voltage VGL supplied to the storage line GL0 is decreased due to the increased line resistance, the capacity of the storage capacitor Cst is reduced, so that the first scan line appears relatively bright in the normal white mode. Will appear.                         

To prevent this, it is necessary to design a group of LOG signal lines that can reduce the line resistance of the LOG gate low voltage transmission line that supplies the gate low voltage to the storage line GL0.

Accordingly, an object of the present invention is to provide a LOG type liquid crystal display panel and a method of manufacturing the same, which can reduce the line resistance of a LOG type gate low voltage transmission line for supplying a gate low voltage to a storage line within a limited region.

In order to achieve the above object, the LOG type liquid crystal display panel according to the present invention includes a plurality of liquid crystal cells formed at each intersection of gate lines and data lines, and pixel voltages formed in each of the liquid crystal cells and charged in the liquid crystal cell. An image display unit including a storage capacitor of a gate-on storage type to be maintained, and a storage line for forming a storage capacitor of liquid crystal cells included in the first scan line; Line on glass type signal lines formed in an outer region of the image display unit to transmit driving signals required by drive integrated circuits for driving gate lines and data lines; The storage line is connected through a line-on-glass-gate low-voltage transmission line for supplying a gate-low voltage among the line-on-glass signal lines and a connection line that is insulated from another line-on-glass signal line. All.

The line-on-glass transmission line is configured to supply gate driving signals required by a gate drive integrated circuit driving gate lines and a common voltage required by a common electrode included in the image display unit.

The line-on-glass gate low-voltage transmission line to which the storage line is connected is connected to a line-on-glass signal line connected between a data tape carrier package on which a data drive integrated circuit is mounted and a gate tape carrier package on a gate drive integrated circuit. It is located in the outermost part of the.

In particular, the gate low voltage transmission line and the storage line are formed together with the gate line in a gate metal pattern, and the connection line includes a source / drain metal pattern intersecting another line on glass type signal line and a gate insulating layer therebetween, It is characterized by consisting of a transparent conductive layer pattern connected to the gate low voltage transmission line, the gate metal pattern of the storage line and the source / drain metal pattern through the contact hole while overlapping the / drain metal pattern and the passivation layer therebetween.

A method of manufacturing a LOG type liquid crystal display panel according to the present invention includes a plurality of liquid crystal cells formed at each intersection of gate lines and data lines, and a gate formed in each of the liquid crystal cells to maintain a pixel voltage charged in the liquid crystal cell. An image display unit including an on storage type storage capacitor and a storage line for forming a storage capacitor of liquid crystal cells included in the first scan line; A method of manufacturing a liquid crystal display panel including line on glass type signal lines formed in an outer region of an image display unit in a line on glass manner to transmit driving signals required by drive integrated circuits driving gate lines. Depositing and patterning a gate metal on a substrate to form a gate metal pattern of the line-on-glass signal lines together with gate lines and storage lines; Forming an active layer of a thin film transistor by applying a gate insulating film over the entire surface, depositing a semiconductor material, and then patterning the semiconductor material; Depositing and patterning the source / drain metal to form a source / drain metal pattern of connection lines that intersect the line-on-glass type signal lines with the data lines; Forming contact holes for partially exposing the gate metal pattern and the source / drain metal pattern after applying the passivation layer thereon; Depositing and patterning a transparent conductive material to interconnect the pixel electrode, the gate low voltage transmission line of the line-on-glass signal line, the gate metal pattern of the storage line, and the source / drain metal pattern of the connection line. And forming a transparent conductive material pattern of the line.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 5C.

3 is an enlarged plan view illustrating a group of LOG signal lines in a liquid crystal panel according to an exemplary embodiment of the present invention, and FIG. 4 is cut along the line A-A 'of the LOG gate low voltage transmission line shown in FIG. It is sectional drawing.

The LOG signal line group 44 shown in FIGS. 3 and 4 is formed in an outer region of an image display unit (not shown) including a plurality of liquid crystal cells to supply gate driving signals required by the gate drive IC. . For example, the LOG signal line group 44 is supplied from a power supply such as a gate low voltage signal VGL, a power signal VCC, a gate high voltage signal VGH, and a ground voltage signal GND from the outside. It is composed of signal lines for supplying each of the gate control signals supplied from the timing controller, such as the DC voltage signals, the gate enable signal GOE, the gate shift clock signal GSC, and the gate start pulse GSP. In addition, the LOG signal line group 44 further includes a signal line for supplying a common voltage VCOM from the power supply unit. The LOG signal line group 44 shown in FIG. 3 includes a first LOG pad group 46 connected to the data TCP together with data pads to which the data signals D1, D2, ... are supplied, and a gate signal. A second LOG pad group 48 is connected to the gate TCP with gate pads supplied with (G1, G2, ...).

The LOG signal line group 44 having such a configuration is composed of gate metal patterns 50 formed with gate lines and gate pads. In particular, the storage line GL0 for forming the storage capacitor Cst included in the first scanning line of the image display part is insulated from the other LOG signal lines, and is located at the outermost position through the connection line 56 formed across. It is connected to the low voltage transmission line 52. In detail, as illustrated in FIG. 4, the storage line GL0 may have a source / drain metal pattern 58 and a transparent conductive layer pattern that may cross the gate metal pattern 50 of the other LOG signal lines 44 insulated from each other. 60 is connected to the LOG type gate low voltage transmission line 52 on the outside.

Referring to FIG. 4, gate metal patterns 50 constituting the LOG signal line group 44 and the storage line GL0 are formed on the lower substrate 42. The source / drain metal pattern 58 of the connection line 56 is formed in the direction crossing the gate metal patterns 50 with the gate insulating layer 68 therebetween. The source / drain metal pattern 58 is connected to the transparent conductive layer pattern 60 of the connection line 56 formed with the passivation layer 70 therebetween through the first to third contact holes 62, 64, and 66. In addition, the gate type gate low voltage transmission line 52 and the gate metal pattern 50 of the storage line GL0 are connected to each other.

In this way, the storage line GL0 may be connected to the LOG type gate low voltage transmission line 52 at the shortest distance through the connection line 56 crossing the other LOG signal lines 44. As a result, the lengths of the LOG type gate low voltage transmission line 52 and the connection line 56 which supply the gate low voltage VGL to the storage line GL0 are shown in FIG. 2. Since it is shorter than the type gate low voltage transmission line 38, the line resistance value can be reduced. The reduction of the line resistance prevents the gate low voltage VGL supplied to the storage line GL0 from being reduced, thereby preventing the first scan line from appearing bright.

In addition, as the storage line GL0 is connected to the LOG type gate low voltage transmission line 52 through the connection line 56, the conventional first gate TCP 14 and the storage line GL0 shown in FIG. The second LOG type gate low voltage transmission line 38B connected to the second gate type gate low voltage transmission line 38B can be removed. Since the formation margin of the LOG signal line group 44 is increased by the removal of the second LOG gate low voltage transmission line 38B, the line resistance of the LOG signal line group 44 is increased to decrease the line resistance. Not only can the line design be facilitated.

5A to 5C are cross-sectional views illustrating a method of manufacturing the LOG signal line group 44 shown in FIG. The manufacturing method of the LOG signal line group 44 will be described below in conjunction with the thin film transistor array process on the lower substrate 42.

First, as shown in FIG. 5A, a gate metal is deposited on the lower substrate 42, and then patterned to form a group of LOG signal lines 44 together with gate lines GL0, GL1, GL2,..., And gate pads. Gate metal pattern 50 is formed.

Next, as shown in FIG. 5B, the gate insulating film 68 is entirely coated on the lower substrate 42 on which the gate metal patterns 50 are formed, amorphous silicon is deposited, and then patterned to form a thin film transistor. An active layer (not shown) is formed. Subsequently, the source / drain metal is deposited and then patterned to form a connection line between the LOG type gate low voltage transfer line 52 and the storage line GL0 together with the data lines DL1, DL2,. A source / drain metal pattern 58 included in 56 is formed.

Subsequently, as shown in FIG. 5C, the passivation layer 70 is entirely coated on the gate insulating layer 68 on which the source / drain metal pattern 58 is formed, and then patterned to form gate pads, data pads, and LOG signal lines. A contact hole for exposing the pad portion of 44) and the drain electrode of the thin film transistor is formed. At the same time, the first through the third gates exposing the gate metal pattern 50 of the LOG type gate low voltage transmission line 52 and the storage line GL0 and the source / drain metal pattern 58 of the connection line 56. Contact holes 62, 64, and 66 are formed. Finally, after depositing and patterning the transparent conductive material, a pixel electrode connected to the drain electrode, a gate electrode, a data pad, a protective electrode connected to pads of the LOG signal line group 44, and a connection line ( The transparent conductive layer pattern 60 of 56 is formed. The transparent conductive material pattern 60 of the connection line 56 is the gate metal of the LOG type gate low voltage transmission line 52 and the storage line GL0 via the first to third contact holes 62, 64, and 66. The pattern 50 is connected to the source / drain metal pattern 58 of the connection line 56.

As described above, in the LOG type liquid crystal panel according to the present invention, the storage line can be connected to the LOG gate low voltage transmission line in the shortest distance through a connection line formed across other LOG type signal lines. As a result, the length of the LOG signal line that supplies the gate low voltage to the storage line is shortened, and the line resistance value is reduced, thereby reducing the gate low voltage (VGL) of the storage line to prevent the first scan line from appearing bright. do. In addition, in the LOG type liquid crystal panel according to the present invention, the LOG type gate low voltage transmission line connected between the first gate TCP and the storage line is removed, thereby increasing the formation margin of the LOG type signal line group. Increasing the line width not only reduces the line resistance, but also facilitates the LOG line design.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

A plurality of liquid crystal cells formed at the intersections of the gate lines and the data lines, a storage capacitor of a gate-on storage type formed in each of the liquid crystal cells to maintain a pixel voltage charged in the liquid crystal cell, and a first scan line. An image display unit having a storage line for forming a storage capacitor of liquid crystal cells included in the liquid crystal cells; Line on glass type signal lines formed in an outer region of the image display unit to transmit driving signals required by drive integrated circuits driving the gate lines and the data lines; The storage line is connected to a line on glass type gate low voltage transmission line for supplying a gate low voltage among the line on glass type signal lines through a connection line that is insulated from the other line on glass type signal lines. Line on glass type liquid crystal display panel. The method of claim 1, The line on glass transmission line And a gate voltage required by a gate drive integrated circuit driving the gate lines and a common voltage required by a common electrode included in the image display unit. The method of claim 1, The line-on-glass gate low-voltage transmission line to which the storage line is connected is connected to a line-on-glass signal line connected between a data tape carrier package on which a data drive integrated circuit is mounted and a gate tape carrier package on a gate drive integrated circuit. Line on glass type liquid crystal display panel, characterized in that located in the outermost portion. The method of claim 1, The gate low voltage transmission line and the storage line are formed together with the gate line in a gate metal pattern. The connection line overlaps the source / drain metal pattern and the source / drain metal pattern intersecting the gate line insulating layer with the other line-on-glass signal lines interposed therebetween, and the gate low voltage through the contact hole. A line-on-glass type liquid crystal display panel comprising a gate metal pattern of a transmission line, a storage line, and a transparent conductive layer pattern connected to the source / drain metal pattern. A plurality of liquid crystal cells formed at the intersections of the gate lines and the data lines, a storage capacitor of a gate-on storage type formed in each of the liquid crystal cells to maintain a pixel voltage charged in the liquid crystal cell, and a first scan line. An image display unit having a storage line for forming a storage capacitor of liquid crystal cells included in the liquid crystal cells; A method of manufacturing a liquid crystal display panel including line-on-glass signal lines formed in an outer region of the image display unit in a line-on-glass manner and transmitting driving signals required by drive integrated circuits for driving the gate lines. , Depositing and patterning a gate metal on a lower substrate to form a gate metal pattern of the line-on-glass signal lines together with the gate lines and the storage line; Forming an active layer of the thin film transistor by applying a gate insulating film over the entire surface, depositing a semiconductor material, and then patterning the semiconductor material; Depositing and patterning a source / drain metal to form a source / drain metal pattern of a connection line intersecting the line-on-glass signal lines with the data lines; Forming contact holes for partially exposing the gate metal pattern and the source / drain metal pattern after the entire surface of the protective film is applied; The connection line for depositing and patterning a transparent conductive material to interconnect the gate low voltage transmission line and the gate metal pattern of the storage line and the source / drain metal pattern of the connection line among the pixel electrode and the line-on-glass signal line. A method of manufacturing a line on glass type liquid crystal display panel comprising the step of forming a transparent conductive material pattern.

Images