KR100806801B1 - Thin film transistor array panel for liquid crystal display and manufacturing method of the same - Google Patents

Abstract

An object of the present invention is to realize a high opening ratio by superimposing a pixel electrode and a gate or a data line, and comprising: a plurality of color filter layers formed on a substrate; A planarization film formed on the entire surface of the substrate including the color filter layer; A plurality of data lines and a plurality of gate lines formed to cross each other on the planarization film; A thin film transistor formed near the intersection of each data line and each data line; A passivation layer formed on an entire surface of the substrate including the plurality of data lines, gate lines, and thin film transistors and having a low dielectric constant; And a plurality of pixel electrodes formed on the passivation layer so as to be connected to each of the thin film transistors.

High opening ratio, TOC, color filter on TFT

Description

Thin film transistor array panel for liquid crystal display and manufacturing method of the same

1 is a structural cross-sectional view of a liquid crystal display device according to a first prior art.

2 is a structural cross-sectional view of an array substrate for a liquid crystal display device according to a second prior art.

3A is a structural plan view of an array substrate for a liquid crystal display device according to the present invention;

Figure 3b is a cross-sectional view taken along the line A-A 'of Figure 3a.

4A through 4B are cross-sectional views illustrating a method of manufacturing an array substrate for a liquid crystal display device according to the present invention.

Explanation of symbols for the main parts of the drawings

301: insulated substrate 302: black matrix

303: color filter layer 304: overcoat

305: data line 306: protective film

307: pixel electrode

The present invention relates to a display device, and more particularly, to an array substrate for a liquid crystal display device and a manufacturing method thereof.

Generally, backlight accounts for more than 60% of the power consumption of TFT-LCD modules in notebook monitors. To reduce this power consumption, the aperture ratio must be increased. Aperture Ratio refers to the ratio of the active contrast generation area to the total display area.It is the sum of the area contributing to the display and the black matrix in the ITO pixel electrode except for the portion not contributing to the display in the liquid crystal display panel. Dividing the area except for by the total pixel area, the ratio becomes the effective transmission area contributing to the actual light transmission as the aperture ratio.

Factors affecting the aperture ratio include the thickness of the gate wiring and the data wiring, the distance between the pixel electrode and the data wiring or the gate wiring, the overlapping distance between the black matrix and the pixel electrode, the storage capacitance, and the area of the thin film transistor.

In order to realize a high opening rate, the size of the above elements should be reduced.

The data wiring is the open and mask alignment error of the data wiring, the gate wiring is the delay of the gate wiring, the gap between the pixel electrode and the data line is the mask alignment error, the short circuit of the two electrodes, and the liquid crystal Distinlination should be taken into consideration, and the pixel electrode and gate wiring spacing should be considered for mask alignment error and parasitic capacitance, and the black matrix and pixel electrode overlap spacing should take into account black matrix etching loss, bonding margin, and pixel electrode alignment error. In addition, the storage capacitance should raise the threshold voltage and the thin film transistor area should increase the charge rate.                         

Hereinafter, the structure of a liquid crystal display device according to the related art will be described in detail with reference to the accompanying drawings.

1 is a structural cross-sectional view of a liquid crystal display device according to a first prior art.

As shown in FIG. 1, the liquid crystal display according to the first conventional technology includes a lower substrate 101a on which a thin film transistor (not shown) is formed and an upper substrate 101b on which a color filter is formed. The gate insulating layer 102 is formed on the lower substrate 101a, and the data lines 103 are patterned on the gate insulating layer 102. In addition, a silicon nitride protective film 104 is stacked on the entire surface of the lower substrate 101a including the data line 103, and a pixel electrode of ITO (Indium Tin Oxide) material is disposed on the protective film 104 at regular intervals. 105 is formed.

The black matrix layer 106 is patterned at a predetermined interval on the upper substrate 101b to prevent light transmission to the plurality of data lines, gate lines, and thin film transistors formed on the lower plate, and the black matrix layer 106 is formed. The color filter layers 107 of R, G, and B that implement color expression are formed in the spaces therebetween. It is also possible to form a planarization film 108 for the protection and planarization of the color filter layer 107 on the color filter layer 107. A common electrode 109 made of ITO is formed on the planarization layer.

2 is a structural cross-sectional view of an array substrate for a liquid crystal display device according to a second prior art.

In the array substrate for a liquid crystal display device according to the second conventional technology, as shown in FIG. 2, a black matrix layer 202 is formed on the lower substrate 201 at regular intervals, and the black matrix layer 202 is formed. R, G, and B color filter layers 203 are formed in the spaces therebetween, and the planarization film 204 is formed over the entire lower substrate 201 including the color filter layers 203. . In addition, a plurality of data lines 205, gate lines, and thin film transistors (not shown) are formed on the planarization layer 204 through a series of processes. In addition, a passivation layer 206 is formed on an entire surface of the lower substrate 201 including the plurality of data lines 205, the gate lines, and the thin film transistor. An ITO pixel electrode 207 is formed on the passivation layer 206 so as to overlap a predetermined portion of the black matrix layer 202.

delete

However, the conventional method for manufacturing an array substrate for a liquid crystal display device has the following problems.

The liquid crystal display according to the first and second prior arts has a wider black than the width of the gate or data line in order to prevent light leakage between the gate or data line and the pixel electrode due to unevenness of the upper and lower plates or discontinuity of the liquid crystal. Since the matrix had to be designed, there was a disadvantage that the aperture ratio was lowered.

Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which improves the aperture ratio by designing or eliminating the black matrix layer smaller than the wiring width of the gate line or data line. There is this.

An array substrate for a liquid crystal display device of the present invention for achieving the above object comprises a plurality of color filter layers formed on the substrate; A planarization film formed on the entire surface of the substrate including the color filter layer; A plurality of data lines and a plurality of gate lines formed to cross each other on the planarization film; A thin film transistor formed near the intersection of each data line and each data line; A passivation layer formed on an entire surface of the substrate including the plurality of data lines, gate lines, and thin film transistors and having a low dielectric constant; And a plurality of pixel electrodes formed on the passivation layer so as to be connected to each of the thin film transistors.
In addition, the method of manufacturing an array substrate for a liquid crystal display device of the present invention for achieving the above object comprises the steps of: forming a plurality of color filter layers on the substrate; Forming a planarization film on the entire surface of the substrate including the color filter layer; Forming a plurality of data lines and a plurality of gate lines on the planarization layer so as to cross each other; Forming a thin film transistor near the intersection of each data line and each data line; Forming a passivation layer having a low dielectric constant formed on an entire surface of the substrate including the plurality of data lines, gate lines, and thin film transistors; And forming a plurality of pixel electrodes formed on the passivation layer so as to be connected to each of the thin film transistors, respectively.

delete

delete

Hereinafter, an array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3A is a plan view of an array substrate for a liquid crystal display according to the present invention, and FIG. 3B is a structural cross-sectional view taken along the line A-A 'of FIG. 3A.

Referring to the array substrate for a liquid crystal display according to the present invention, as shown in FIGS. 3A and 3B, the lower substrate 301 has a smaller width than the gate line 308 or the data line 305 at regular intervals. The black matrix layer 302 is formed, and the color filter layers 303 of R, G, and B for implementing color expression are formed in the space between the black matrix layers 302, and the color filter layer 303 The planarization film 304 is formed on the entire surface of the lower substrate 301 including the. In addition, a plurality of data lines 305, gate lines 308, and thin film transistors 310 are formed on the planarization layer 304 through a series of processes. The passivation layer 306 is formed on the entire surface of the lower substrate 301 including the plurality of data lines 305, the gate lines 308, and the thin film transistor 310. The pixel electrode 307 of ITO (Induim Tin Oxide) material is formed on the passivation layer 306 to overlap the gate line 308 or the data line 305 with predetermined portions d1 and d2.

The black matrix layer 302 may be omitted.

Meanwhile, in the liquid crystal display device according to the first and second prior arts, the gate line 308 or the data line 305 and the pixel electrode 307 do not overlap with each other because of the gate line 308 or the data line 305. This is because of the parasitic capacitor existing between the pixel electrode 307 and the pixel electrode 307. Conventionally, in order to reduce this parasitic capacitor, it has been designed so that each component listed above does not overlap.

In the array substrate for a liquid crystal display according to the present invention, the parasitic capacitance between the gate line 308 or the data line 305 and the pixel electrode 307 is reduced by replacing the protective film 306 with an organic insulating film having a low dielectric constant. Therefore, the pixel electrode 307 and the gate line 308 or the data line 305 may be overlapped.

The overlapping portion of the pixel electrode 307 and the gate line 308 or the data line 305, that is, the overlapping portion of the pixel electrode 307 on the left and right sides of the gate line 308 or the data line 305 may be asymmetrical. Do. In this case, the minimum thickness of the overlapping portions d1 and d2 between the pixel electrode 307 and the gate line 308 (or the data line 305) should take into account the foreground of the liquid crystal.

The foreground line refers to a boundary between liquid crystal regions having opposite directors. At the end of the pixel electrode 307, a disintegration is induced by liquid crystal alignment and an electric field effect, causing light leakage. do.

4A to 4B are cross-sectional views illustrating a method of manufacturing an array substrate for a liquid crystal display device according to the present invention.

As shown in FIG. 4A, a black matrix layer 302 smaller than a width of the gate line 308 or the data line 305 is formed on the lower substrate 301 at intervals between the black matrix layer 302. The color filter layers 303 of R, G, and B are formed to implement color expression in the space of. The black matrix layer 302 may not be formed.

Next, as shown in FIG. 4B, an overcoat 304 is formed on the entire surface of the lower substrate 301 including the color filter layer 303 to protect the color filter layer 303. The material of the planarization film 304 may be any organic compound whose physical properties are hardened by Cure after spin coating such as BCB, HSQ, SSQ, MSSQ, POSS, and FO _x .

Next, as shown in FIG. 4C, a plurality of data lines 305, gate lines 308, and thin film transistors (not shown) are formed on the planarization film 304 in a series of processes. In the case of the thin film transistor 310, the thin film transistor 310 refers to a process of forming a gate electrode, stacking a gate insulating layer, forming a semiconductor layer, and forming a source / drain electrode. The data line 305 is a source / drain electrode, and the gate line 308 is the same material and the same process as the gate electrode.

As shown in FIG. 4D, a protective film 306 is formed by stacking an insulating material such as silicon nitride on the entire surface of the lower substrate 301 including the plurality of data lines 305, the gate lines 308, and the thin film transistor 310. ), A transparent conductive film of ITO material is deposited by sputtering, and patterned to overlap the gate line 308 or the data line 305 on the passivation layer 306. 307 is formed.

Subsequently, although not shown in the drawings, a black matrix is formed to prevent light from being transmitted to the lower substrate 301 on which the color filter layer 303 and the thin film transistor 310 are formed and to face the thin film transistor (not shown). After bonding the upper substrate (not shown) to form a liquid crystal and then sealed, the manufacturing process of the array substrate for a liquid crystal display device according to the present invention is completed.

 As described above, the liquid crystal display array substrate of the present invention and its manufacturing method have the following effects.

By using an organic insulating material as a protective film, it is possible to superimpose the gate or data line and the pixel electrode, so that the aperture ratio improvement can be realized by designing or eliminating the black matrix formed below the gate or data line smaller than the width of the two lines. There are advantages to it.

Claims (29)

A plurality of color filter layers formed on the substrate; A planarization film formed on the entire surface of the substrate including the color filter layer; A plurality of data lines and a plurality of gate lines formed to cross each other on the planarization film; A thin film transistor formed near the intersection of each data line and each data line; A passivation layer formed on an entire surface of the substrate including the plurality of data lines, gate lines, and thin film transistors; And a plurality of pixel electrodes formed on the passivation layer so as to be connected to each of the thin film transistors, respectively. delete delete delete The array substrate of claim 1, wherein the passivation layer is one of an acrylic resin, benzocyclobutene (BCB), and polyimide. delete delete delete delete delete The array substrate of claim 1, further comprising a black matrix layer formed on the substrate to be positioned between the color filter layers. 12. The array substrate of claim 11, wherein a width of the black matrix layer is smaller than a width of the gate line. 12. The array substrate of claim 11, wherein a width of the black matrix layer is smaller than a width of the data line. 2. The array substrate of claim 1, wherein each pixel electrode overlaps a portion of adjacent gate lines. 15. The method of claim 14, wherein an area in which any pixel electrode overlaps an arbitrary first gate line and an area in which any pixel electrode overlaps a second gate line adjacent to the first gate line are the same. Array substrate for liquid crystal display device. 15. The method of claim 14, wherein an area in which an arbitrary pixel electrode overlaps an arbitrary first gate line and an area in which an arbitrary pixel electrode overlaps a second gate line adjacent to the first gate line are different from each other. Array substrate for liquid crystal display device. The array substrate of claim 1, wherein each pixel electrode overlaps a portion of each adjacent data line. 18. The method of claim 17, wherein an area in which any pixel electrode overlaps any first data line and an area in which any pixel electrode overlaps a second data line adjacent to the first data line are the same. Array substrate for liquid crystal display device. 18. The method of claim 17, wherein an area in which an arbitrary pixel electrode overlaps an arbitrary first data line and an area in which an arbitrary pixel electrode overlaps a second data line adjacent to the first data line are different from each other. Array substrate for liquid crystal display device. Forming a plurality of color filter layers on the substrate; Forming a planarization film on the entire surface of the substrate including the color filter layer; Forming a plurality of data lines and a plurality of gate lines on the planarization layer so as to cross each other; Forming a thin film transistor near the intersection of each data line and each data line; Forming a protective film having a dielectric constant formed on an entire surface of the substrate including the plurality of data lines, gate lines, and thin film transistors; And forming a plurality of pixel electrodes formed on the passivation layer so as to be connected to each of the thin film transistors, respectively. 21. The method of claim 20, further comprising forming a black matrix layer formed on the substrate to be positioned between the color filter layers. 22. The method of claim 21, wherein the width of the black matrix layer is smaller than the width of the gate line. 22. The method of claim 21, wherein the width of the black matrix layer is smaller than the width of the data line. 21. The method of claim 20, wherein each pixel electrode overlaps a portion of adjacent gate lines. 25. The method of claim 24, wherein an area in which an arbitrary pixel electrode overlaps an arbitrary first gate line and an area in which an arbitrary pixel electrode overlaps a second gate line adjacent to the first gate line are identical to each other. Method of manufacturing array substrate for liquid crystal display device. 25. The method of claim 24, wherein an area in which an arbitrary pixel electrode overlaps an arbitrary first gate line and an area in which an arbitrary pixel electrode overlaps a second gate line adjacent to the first gate line are different from each other. Method of manufacturing array substrate for liquid crystal display device. 21. The method of claim 20, wherein each of the pixel electrodes overlaps a portion of each adjacent data line. 28. The method of claim 27, wherein an area in which any pixel electrode overlaps any first data line and an area in which any pixel electrode overlaps a second data line adjacent to the first data line are the same. Method of manufacturing array substrate for liquid crystal display device. 28. The method of claim 27, wherein an area in which an arbitrary pixel electrode overlaps an arbitrary first data line and an area in which an arbitrary pixel electrode overlaps an adjacent second data line adjacent to the first data line are different from each other. Method of manufacturing array substrate for liquid crystal display device.

Images