KR100804645B1 - Continuous time delta-sigma modulator with self cut-off current dac - Google Patents

Abstract

A continuous time delta-sigma modulator with a self cut off current mode DAC is provided to suppress a jitter noise by supplying a constant amount of charges to a DAC, even when a size of a coupling capacitor is varied. A DAC(Digital to Analog Converter) includes a coupler capacitor(CC), first switches, at least one current source(32,33), and second and third switches. The first switch couples both ends of the coupling capacitor with a reference voltage according to a first control signal. The current source generates a current with a constant value when a voltage difference between both ends is bigger than a predetermined level. When the voltage difference becomes smaller than the predetermined level, the current generated by the current source is decreased. The second switch selectively couples the other end of the coupling capacitor with the current source according to a second control signal and a digital output. An activation period of the second control signal is not overlapped with that of the first control signal. The third switch couples one end of the coupling capacitor with a first input terminal of the operational amplifier according to the second control signal.

Description

CONTINUOUS TIME DELTA-SIGMA MODULATOR WITH SELF CUT-OFF CURRENT DAC} with Self-Blocking Current-Mode Digital-to-Analog Converter

1 is a block diagram illustrating a basic structure of a continuous time delta sigma modulator.

2A and 2B are block diagrams illustrating only an input portion of the delta sigma modulator of FIG. 1, and FIG. 2C is a graph comparing a change in current with time of the I-DAC of FIG. 2A and the SC-DAC of FIG. 2B.

FIG. 3 is a circuit diagram illustrating an input portion of a continuous time delta sigma modulator including a self cut off current mode digital-to-analog converter according to an embodiment of the present invention.

4A is a graph illustrating current characteristics of the self-blocking current mode digital-to-analog converter of FIG. 3, and FIG. 4B is a graph illustrating voltage changes of the summation node and the first node of FIG. 3.

5 is a circuit diagram illustrating an input portion of a continuous time delta sigma modulator with a self-blocking current mode digital-to-analog converter in accordance with one embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11: active integrator

31: Self-Blocking Current-Mode Digital-to-Analog Converter

Cc: coupling capacitor

32, 33: current source

The present invention relates to an electronic circuit having a digital to analog conversion feedback path therein, and more particularly to a continuous time delta sigma modulator having a digital to analog conversion feedback path therein.

Delta sigma modulators offer high precision, low noise, and are widely used in professional audio systems, communication systems, and precision measurement devices.

1 is a block diagram illustrating a basic structure of a delta sigma modulator. Referring to FIG. 1, a continuous time delta sigma modulator (CTDSM) 10 is basically an integrator 11, a quantum 12, and a feedback digital-to-analog converter (DAC) ( 13). The input signal V _IN is taken as a single-ended signal, but may be a differential signal. An input resistor R _IN may be further included on the input side. Although the structure of the continuous time delta sigma modulator 10 may be modified according to an order or a differential signal, the basic structure may be avoided.

In addition to the CTDSM, the basic structure of a widely used discrete time delta sigma modulator (DTDSM) is similar to that of the CTDSM. However, the integrator of the DTDSM receives a discrete input pulse, whereas the integrator 11 of the CTDSM receives an analog input signal that continuously varies with time.

Since the CTDSM 10 integrates the analog input signal, the requirements such as the settling time for stabilizing the output of the operational amplifier 111 used when implementing the internal integrator 11 are relaxed compared to the DTDSM. Can be. In addition, the CTDSM may not require an anti-aliasing filter, may be implemented in a lower order structure, and consumes less power.

The integrator 11 integrates the current which is summed to the input signal (V _IN) to the input resistor (R _IN) to the value of input current (I _IN) and the converted analog feedback signal (I _F) divided. The more linear the integrator 11 is, the better the characteristics of the entire delta sigma modulator 10 are. In FIG. 1, the integrator 11 is illustrated in the form of an active RC using an operational amplifier 111 and a capacitor C _I.

The quantizer 12 quantizes the output of the integrator 11 and outputs the result to the digital output Q. The feedback DAC 13 feeds back the digital output Q to provide an analog feedback signal I. _F ) The converted feedback signal I _F is summed with the input current I _IN at the summing node N _SUM and applied to the integrator 11.

The feedback DAC 13 may be implemented in various forms. Basically, providing the analog feedback current I _F corresponding to the digital output Q of the quantizer 12 to the summing node N _SUM . That is the purpose. Such a DAC includes a current DAC (I-DAC) having predetermined current sources and combining an output of the current sources according to a digital output to provide an analog current, and a predetermined voltage every clock using predetermined voltage sources, switches and capacitors. Switched capacitor DACs (SC-DACs), which control analog current by supplying or receiving charges, are typical.

FIG. 2A is a block diagram illustrating only an input portion of the delta sigma modulator of FIG. 1, wherein the feedback DAC is implemented as a current DAC.

Referring to FIG. 2A, the current DAC 13A includes first and second current sources 21, 22, and the first and second current sources 21, 22 are digital outputs Q of the quantizer 12. ) Is connected or disconnected to the summing node N _SUM by the first and second switches S ₁ , S ₂ , respectively. The current DAC 13a provides a predetermined feedback current to the summing node for one or half periods of the digital output Q according to the form of the digital output Q.

FIG. 2B is a block diagram illustrating only an input portion of the delta sigma modulator of FIG. 1, wherein the feedback DAC is implemented as a switched capacitor DAC.

Referring to Figure 2b, the switched-capacitor (C _S) respectively, the first to third charging switches _{(S C1, S C2, S} C3) of the first and second discharging switches (S _D1, S _D2) in both ends of the It is arranged. The first and second charge switches connect first and second voltage sources 23 and 24 to the switched capacitor C _S , and the third charge switch S _C3 is the switched capacitor C _S. And the summation node (N _SUM ). The first control signal by (φ ₁₎ of the first and second discharging switches (S _D1, S _D2) is turned on (on), and the first control signal a second (φ ₁₎ than is the active period that does not overlap According to the digital output Q, the first charging switch or the second charging switch S _C1 , S _C2 and the third charging switch S _C3 are turned on according to the control signal φ ₂ . The voltage source 23 or the second voltage source 24 is connected to the summing node N _SUM through the switched capacitor C _S. When the first voltage source 23 or the second voltage source 24 is connected to the switched capacitor C _S according to the second control signal φ ₂ , the switched capacitor C _S is rapidly charged. In the initial stage of charging, an impulse current appears in the summation node N _SUM .

Either way, Fig. 2A or Fig. 2B is intended to transfer an amount of charge corresponding to the digital output to the integrating capacitor, so the sum of the amount of charge transferred is equal.

FIG. 2C is a graph comparing changes of current with time of the I-DAC of FIG. 2A and the SC-DAC of FIG. 2B. Referring to Figure 2c, the current of the I-DAC is characterized in that the overall low and constant size, the current of the SC-DAC has a characteristic that the magnitude of the initial increase and then rapidly decreases after the peak and very small later.

Since the current in the DAC is applied to the integrator, it has much to do with the current driving capability of the op amps that make up the integrator. In the case of the I-DAC, since a relatively small current flows constantly, the operational amplifier may have a low current driving capability and consume less power in actual implementation. In the case of SC-DAC, on the other hand, large current flows initially, so the op amp needs to have good current driving capability and consumes a lot of power in actual implementation.

On the other hand, the clock for controlling the switches may have jitter. In the case of the I-DAC, since a constant current flows even later in the period of the digital output, an amount of charge that is proportional to the jitter is supplied more or less so that an error may occur. Grows On the other hand, in the case of the SC-DAC, the current becomes very small later in the cycle of the digital output, so even if there is jitter, the error is minimal.

As described above, when implementing a feedback DAC using a conventional I-DAC or SC-DAC, the sigma delta sigma modulator adopts the I-DAC to reduce power consumption, so that the SC-DAC is sensitive to jitter or vice versa. If the power consumption is increased, there is a problem in that the optimal design is difficult.

In order to improve this, a structure of inserting a resistor of a predetermined size between the switching capacitor and the summing node while adopting the SC-DAC has been proposed, but it limits the initial current size but also the jitter since the current decreases later. There is a problem to be sensitive to the above problem can not be solved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a current supply source capable of blocking current by itself and a current mode digital / analog converter using the same.

Another object of the present invention is to provide a continuous time delta sigma modulator with a current mode digital-to-analog converter capable of blocking current on its own.

Still another object of the present invention is to provide an electronic circuit having a current mode digital-to-analog converter in a feedback path that can cut off current by itself.

An electronic circuit according to an embodiment of the present invention is a digital-to-analog converter for converting and feeding back a digital feedback output to an analog feedback signal, and the first input terminal receives the sum of the input signal and the analog feedback signal, the second input terminal Includes an active integrator using an operational amplifier connected to a reference potential, wherein the digital-to-analog converter comprises: a coupling capacitor, a first switch connecting both ends of the coupling capacitor to the reference potential according to a first control signal, respectively. For example, at least one current source that has a constant value while the voltage difference between each end is greater than a predetermined level, but generates a current that decreases when the voltage difference between the both ends is less than a predetermined level, and the second control signal does not overlap the active section. The other end of the coupling capacitor in accordance with a control signal and the digital output And second switches for selectively connecting between the current source and the current source, and a third switch for connecting one end of the coupling capacitor and the first input terminal of the operational amplifier according to the second control signal.

According to an embodiment, the current source may generate the current such that a time point when the voltage difference between each end becomes smaller than a predetermined level reaches a time point when the second control signal is inactivated.

In some embodiments, the current source may include a metal oxide semiconductor (MOS) transistor biased to a gate-source voltage above a threshold voltage, in which case the current may be generated based on the drain current of the MOS transistor. In addition, the voltage difference between the both ends may be a drain-source voltage of the MOS transistor.

In some embodiments, the electronic circuit may further include an input resistor coupling the input signal and the first input terminal.

In some embodiments, the input signal and the analog feedback signal may be single-ended signals or differential signals.

According to another aspect of the present invention, an electronic circuit includes a coupling capacitor, first switches connecting both ends of the coupling capacitor to the reference potential according to a first control signal, and a voltage difference between each end is greater than a predetermined level. The coupling capacitor according to at least one current source having a constant value but generating a reduced current when the voltage difference between the both ends is smaller than a predetermined level, a second control signal in which an active period does not overlap with the first control signal, and the digital output. Second switches for selectively connecting between the other end of the current source and the current source, an operational amplifier having first and second input terminals virtually or directly connected to a reference potential, respectively, and the coupling capacitor according to the second control signal. And a third switch connecting one end and a first input terminal of the operational amplifier.

According to an embodiment, the current source may generate the current such that a time point when the voltage difference between each end becomes smaller than a predetermined level reaches a time point when the second control signal is inactivated.

In some embodiments, the current source may include a metal oxide semiconductor (MOS) transistor biased to a gate-source voltage above a threshold voltage, in which case the current may be generated based on the drain current of the MOS transistor. In addition, the voltage difference between the both ends may be a drain-source voltage of the MOS transistor.

In some embodiments, the electronic circuit may further include an input resistor coupling the input signal and the first input terminal.

In some embodiments, the input signal and the analog feedback signal may be single-ended signals or differential signals.

A continuous time delta sigma modulator according to another embodiment of the present invention is an active integrator using an operational amplifier receiving an input signal and an analog feedback signal, a quantizer for generating a digital output, and a digital for converting the digital output into the analog feedback signal. And an analog converter, wherein the operational amplifier includes a first input terminal receiving the input signal and an analog feedback signal and second input terminals connected to a reference potential, wherein the digital to analog converter comprises a coupling capacitor. First switches that connect both ends of the coupling capacitor to the reference potential, respectively, according to a first control signal, and have a constant value while a voltage difference between each end is greater than a predetermined level, but a voltage difference between the both ends is smaller than a predetermined level. At least one current source that produces ground-decreased current, According to the second control signal and the second switches for selectively connecting between the other end of the coupling capacitor and the current source according to the second control signal and the digital output that does not overlap the first control signal and the active period And a third switch connecting one end of a coupling capacitor and the first input terminal of the operational amplifier.

According to an embodiment, the current source may generate the current such that a time point when the voltage difference between each end becomes smaller than a predetermined level reaches a time point when the second control signal is inactivated.

In some embodiments, the current source may include a metal oxide semiconductor (MOS) transistor biased to a gate-source voltage above a threshold voltage, in which case the current may be generated based on the drain current of the MOS transistor. In addition, the voltage difference between the both ends may be a drain-source voltage of the MOS transistor.

In some embodiments, the continuous time delta sigma modulator may further include an input resistor coupling the input signal and the first input terminal.

In some embodiments, the input signal and the analog feedback signal may be single-ended signals or differential signals.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" or "coupled" to another component, it may be directly connected to or coupled to that other component, but it may be understood that other components may be present in the middle. Should be. On the other hand, when a component is said to be "directly connected" or "directly coupled" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, component, part, or combination thereof that is described, and that one or more other features, numbers, components, It should be understood that it does not exclude in advance the possibility of the presence or addition of parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

FIG. 3 is a circuit diagram illustrating an input portion of a continuous time delta sigma modulator (CTDSM) including a self cut-off current-mode digital-to-analog converter according to an embodiment of the present invention.

Referring to FIG. 3, the self-blocking I-DAC 31 may configure a feedback path of the CTDSM (not shown), and the predetermined feedback current signal I _F according to the digital output Q of the CTDSM. ) To the summing node (N _SUM ). The input current I _IN , which is a value obtained by dividing the input signal V _IN by the input resistance R _IN , is summed with the feedback signal I _F at the summation node N _SUM , and the summed current component is integrated capacitor ( Is integrated in C _I ). The active integrator 11 consists of an integrating capacitor C _I and an operational amplifier 111, which has an input terminal directly or virtually connected to a reference potential.

The self-blocking type I-DAC 31 uses a 1-bit DAC as an example for convenience of description, and includes first and second current sources 32 and 33 and first and second discharge switches S _D1 and S. _D2 ), the first to third charging switches S _C1 , S _C2 , S _C3 , and a coupling capacitor CC.

The self-blocking type I-DAC 31 has a structure in which a coupling capacitor C _C is inserted between the current sources 32 and 33 and the summing node N _SUM based on the current DAC described in FIG. 2A. can do. The self-blocking I-DAC 31 may look similar to the SD-DAC of FIG. 2B, but its fundamental operations are different from each other. While the switched capacitor C _S of the SD-DAC basically acts as an equivalent resistance by transferring charge through fast switching, the coupling capacitor C _{C is} connected to the first and second nodes N ₁ ,. The difference is that the voltage of N ₂ ) is different.

The digital output Q of the CTDSM is a 1-bit or multi-bit digital signal, and the first and second current sources 32 and 33 are first and second corresponding to logic values 0 and 1 of the corresponding digital output bits, respectively. Generate 2 currents I ₁ , I ₂ . In this case, the first and second currents I ₁ and I ₂ may have the same magnitude and opposite signs. The first and second current sources 32 and 33 have constant values while the voltage difference between both ends is greater than a predetermined level, but generate currents having a characteristic of decreasing when the voltage difference between both ends is smaller than a predetermined level. If the time difference between the voltage difference between the current source 32, 33 reaches a predetermined level, the current source 32, 33 may have a very strong jitter characteristic.

The first and second charge switches S _C1 and S _C2 connect the first and second current sources 32 and 33 and the coupling capacitor C _C at the first node N ₁ , and The third charging switch S _C3 connects the coupling capacitor C _C and the summing node N _SUM at a second node N ₂ .

The first and second discharge switches S _D1 and S _D2 are turned on by a first control signal φ ₁ having a first phase, and the coupling capacitor C _C The potentials at both ends, i.e., the first and second nodes N ₁ and N ₂ , are equal to the reference potential and all of the charges charged in the coupling capacitor C _C are discharged. In this case, since the third charging switch S _C3 is off according to the second control signal φ2, the coupling capacitor C _C is different from the summing node N _SUM and the current sources 32 and 33. Each is electrically disconnected. On the other hand, the summing node N _SUM is connected to the input terminal of the operational amplifier 111 in the active integrator 11. Since the input terminal is connected to the reference potential, the summing node N _SUM also has a reference potential. do.

After the voltage across the coupling capacitor C _C becomes the reference potential, the first charge switch or the second charge switch according to the second control signal φ ₂ having the second phase and the digital output Q. When S _C1 and S _C2 and the third charging switch S _C3 are turned on, the first current source or the second current source 32, 33 is connected to the summing node N through the coupling capacitor C _{C. SUM} ). Meanwhile, the first and second discharge switches S _D1 and S _D2 are turned off according to the first control signal φ ₁ .

When the second control signal (φ ₂₎ applied to the first node (N ₁₎ in the first current or the second current (I _1, I ₂₎ is so flowing, the potential of the first node (N ₁₎ is the current flowing It is getting lower or getting higher depending on the sign of. However, since the potential of the second node N ₂ or the summation node N _SUM is virtually connected to the reference potential, it is kept at the reference potential. The first current source or the second current source 32, 33 is reduced when the voltage difference between both ends is smaller than a predetermined level. If the voltage difference between the first and second current sources 32 and 33 is set to be smaller than a predetermined level before a sufficient time for the second control signal φ ₂ to be deactivated, the second control signal φ ₂ may be set. Even with large jitter, the error due to jitter can be minimized.

Immediately after the second control signal φ ₂ is applied, both ends of the coupling capacitor C _C have a reference potential, and in this state, the first current or the second current I ₁ , I ₂ is discharged. Since it is forcibly applied from one node (N ₁ ) to the coupling capacitor (C _C ), even in the summing node (N _SUM ) to the coupling capacitor (C _C ), the first current or the second current (I ₁ , A current corresponding to I ₂ ), that is, a feedback current I _F , flows.

In this way, the self-blocking I-DAC generates a feedback current I _F having the same magnitude as the first current or the second current I ₁ , I ₂ , and delivers the feedback current I _F to the summing node N _SUM , Initially, the feedback current I _F may be supplied in a constant magnitude, and then the feedback current I _F may be blocked by itself before the second control signal φ ₂ is deactivated.

FIG. 4A is a graph illustrating current characteristics of the self-blocking I-DAC of FIG. 3, and FIG. 4B is a graph illustrating voltage changes of the summation node and the first node of FIG. 3.

Since the first or second currents I ₁ and I ₂ provided by the first and second current sources 32 and 33 of the self-blocking I-DAC have only the same sign but have substantially the same characteristics, Only the current I ₁ will be described.

Referring to FIG. 4A, a relative waveform of the second control signal φ ₂ and the first current I ₁ is shown. The second control signal φ ₂ is activated from the reference time t ₀ to the end time t ₁ . The first current I ₁ is kept constant with a predetermined magnitude from the first period, i.e., immediately after the reference time t ₀ to the cutoff time t _c , and then, the second period, i.e., the predetermined time ( decreases from t _c ) until the end time t ₁ .

The self-blocking type I-DAC of FIG. 3 has a structure in which a coupling capacitor C _C is added based on a conventional I-DAC, and a feedback current I _F is illustrated by the first and second current sources. It has the same waveform as the first current I ₁ of 4a. That is, the feedback current I _F initially has a constant magnitude and greatly decreases before the cycle of the second control signal φ ₂ ends.

In the operation of the self-blocking I-DAC, the total amount of charge transferred is most important. Since the charge transfer starts from the moment when the second control signal φ ₂ is activated, the jitter at the time when the second control signal φ ₂ starts is not important. In the prior art, since the jitter at the end of the second control signal φ ₂ changes the amount of charge transferred, it may have a great influence on the operation of the conventional I-DAC. However, when the self-blocking type I-DAC according to the exemplary embodiment of the present invention as shown in FIG. 3 is used, the feedback current I _F is very small or absent at the time when the second control signal φ ₂ ends. There is also little effect. In addition, the operational amplifier 111 in the active integrator 11 of the CTDSM to which the feedback current I _F is applied does not have to have a large current driving capability.

If the magnitude of the feedback current I _F becomes zero before the second control signal φ ₂ is deactivated by adjusting the cutoff time t _c , the influence on jitter may be completely eliminated.

Referring to FIG. 4B, at the reference time t ₀ , both ends of the coupling capacitor C _C are immediately connected to the reference potential V _R by the first control signal φ ₁ . One node N ₁ has a reference potential V _R. In addition, the summing node N _SUM or the second node N ₂ is also connected to the input terminal of the operational amplifier 111 having the reference potential V _R , and thus has a reference potential. After the reference time t ₀ , the potential V _SUM of the summing node N _SUM maintains the reference potential V _R , while the potential of the first node N ₁ is the first current I. ₁ ) gradually decreases as it flows.

The first node (N ₁₎ jidaga potential is still low, the makin lower than the predetermined potential in the cut-off time (t _c), off time (t _c) if reduced in size in the first current (I ₁₎ after the The potential V _N1 of the first node N ₁ becomes close to zero more slowly than before.

Although not shown in FIG. 4B, if the direction of the first current is different, the potential of the first node will be increased little by little, but the principle is the same.

5 is a circuit diagram illustrating an input portion of a continuous time delta sigma modulator (CTDSM) having a self-blocking I-DAC in accordance with an embodiment of the present invention.

5, the self-blocking type I-DAC is summing the predetermined feedback current (I _F) depending on the digital output (Q) of and the CTDSM constitute a feedback path of the CTDSM Like Fig node (N _SUM To provide. An input signal I _IN is summed with the feedback current I _F at the summation node N _SUM , and the summed current component is integrated at an integration capacitor C _I.

The self-blocking I-DAC, for convenience of description, uses a 1-bit DAC as an example. First and second current sources 32 and 33, first and second discharge switches, and first to third charge switches. And a coupling capacitor. The first and second current sources 32 and 33 include transistors MN and MP, respectively. Each drain current of the first and second transistors MN and MP is referred to as first and second currents I ₁ and I ₂ and corresponds to logic values 0 and 1, respectively. The first transistor MN may be an n-type metal oxide semiconductor (NMOS) transistor, and the second transistor MP may be an n-type metal oxide semiconductor (PMOS) transistor. The first and second transistors MN and MP are biased with gate-source voltages V _NB and V _PB sufficient to turn on, respectively, and the high power supply voltage VDD and the low power supply voltage VSS are respectively. Higher or lower than the reference potential.

As in FIG. 3, the first and second discharge switches S _D1 and S _D2 are turned on by the first control signal φ ₁ having the first phase, and are both ends of the coupling capacitor C _C. That is, the potentials of the first and second nodes N ₁ and N ₂ are equal to the reference potential, and all of the charges charged in the coupling capacitor C _C are discharged. The summing node N _SUM also has a reference potential. The reference potential is high enough to allow any MOS transistor to operate in saturation mode. According to the second control signal φ ₂ , the third charging switch S _C3 is turned off, so the coupling capacitor C _C is electrically connected to the summing node N _SUM and the current sources 32 and 33, respectively. Is blocked.

After the voltage across the coupling capacitor C _C becomes the reference potential, the first charge switch or the second charge switch according to the second control signal φ ₂ having the second phase and the digital output Q. When S _C1 and S _C2 and the third charging switch S _C3 are turned on, the first current source or the second current source 32, 33 is connected to the summing node N through the coupling capacitor C _{C. SUM} ). Meanwhile, the first and second discharge switches S _D1 and S _D2 are turned off according to the first control signal φ ₁ .

Assuming that the digital output Q is 0, the first transistor MN is connected to the coupling capacitor C _C by a first charge switch S _C1 . Since the bias voltage V _NB is supplied to the gate of the first transistor MN, the first transistor MN is turned on, and the drain, that is, the potential of the first node N _{1 is} referred to as the reference potential. It is sufficient to operate one transistor MN in saturation mode. Accordingly, the drain current I _D1 having a constant magnitude determined by the bias voltage V _NB is generated at the drain of the first transistor MN. Due to the drain current I _D1 , the potential of the first node N ₁ is slowly lowered linearly from the reference potential. When the potential of the first node N ₁ falls below a predetermined level, or when the drain-source voltage of the first transistor MN is lower than a predetermined level, the first transistor MN enters a triode mode. The drain current I _D1 starts to decrease. Since the potential of the first node N ₁ continues to drop, the drain current I _D1 eventually approaches almost zero, whereby the self-blocking I-DAC self-reduces the output feedback current I _F by itself. You can block.

If the digital output Q is 1, the second transistor MP is connected to the coupling capacitor C _C through a second charge switch S _C2 . The only difference is that the second transistor S _C2 is a PMOS transistor, and the basic operation is substantially similar to that of the first transistor MN when the digital output Q is zero. However, when the second transistor MP operates, the potential of the first node N ₁ becomes higher than the reference potential. Then, when the source-drain voltage of the second transistor MP, which is a PMOS, is lower than a predetermined level, the second transistor MP is operated in the triode mode, and the drain current starts to decrease, and is soon cut off.

First and second transistors because the drain current of the (MN, MP) is the coupling capacitor (C _C) sikineunde charging a negative charge or a positive charge to the charge conservation to be satisfied by the coupling capacitor (C _C), the summing node From N _SUM , a feedback current I _F having the same magnitude as the drain current is generated from the coupling capacitor C _C.

Although the 1-bit DAC has been described as an example in FIGS. 3 and 5, when the multi-bit quantizer is used, the technical idea of the present invention can be easily applied to the multi-bit DAC. In addition, although the case where the input and output are single-ended signals has been described as an example, it is natural that the technical idea of the present invention can be easily applied even when the input or output is a differential signal. In addition, although the current source is implemented as an MOS transistor, the current source may be implemented as a properly biased bipolar junction transistor.

Although the above example is used as a delta sigma modulator, the present invention can be applied to any application circuit as long as the electronic circuit has a DAC that converts and outputs a digital output into an analog signal. In particular, the present invention can be applied to an electronic circuit having a structure in which the analog signal is applied to an input terminal of an active integrator using an operational amplifier.

It can be widely applied to electronic circuits including op amps and DACs and configured to receive analog signals converted from digital signals through op amps, or any electronic circuit requiring a current source that is blocked by itself.

When the embodiments of the present invention are actually implemented using current semiconductor process technology, the interruption time of the current source is changed according to the change of the size of the current source or the change of the coupling capacitor due to the process change, and as a result, The amount of charge may change. In general, high-resolution ADCs or filters add self-calibration or auto-tuning circuits to correct process problems. Embodiments of the present invention may further include a self-correction circuit or a self-correction circuit for correcting a process error of the current source or coupling capacitor.

The electronic circuit including the self-blocking current DAC and the feedback path according to an embodiment of the present invention is jitter-resistant and can reduce the current driving capability requirement of the internal operational amplifier. Therefore, the overall design burden can be reduced and power consumption can be reduced.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (24)

A digital-to-analog converter for converting and feeding back a digital output into an analog signal, and an active integrator using an operational amplifier coupled to a first input terminal, the first input terminal being summed with the analog feedback signal, and a second input terminal coupled to a reference potential; In the electronic circuit, The digital to analog converter, Coupling capacitors; First switches respectively connecting both ends of the coupling capacitor to the reference potential according to a first control signal; At least one current source having a constant value while the voltage difference between each end is greater than a predetermined level, but generating a current which decreases when the voltage difference between the both ends is less than a predetermined level; Second switches for selectively connecting between the other end of the coupling capacitor and the current source according to the second control signal and the digital output where the active period does not overlap the first control signal; And And a third switch connecting one end of the coupling capacitor and the first input terminal of the operational amplifier according to the second control signal. The electronic circuit of claim 1, wherein the current source generates the current such that a time point when the voltage difference between the both ends becomes smaller than a predetermined level reaches a time point when the second control signal is deactivated. The method of claim 1, wherein the current source includes a metal oxide semiconductor (MOS) transistor biased to a gate-source voltage equal to or greater than a threshold voltage. The current is generated based on the drain current of the MOS transistor. 4. The electronic circuit according to claim 3, wherein the voltage difference between the both ends is a drain-source voltage of the MOS transistor. The electronic circuit of claim 1, further comprising an input resistor coupling the input signal and the first input terminal. The electronic circuit of claim 1, wherein the input signal and the analog feedback signal are differential signals. The electronic circuit of claim 1, further comprising a self-calibration circuit for correcting a process error of the current source. 2. The electronic circuit of claim 1, further comprising a self-tuning circuit for correcting the process error of the coupling capacitance. Coupling capacitors; First switches respectively connecting both ends of the coupling capacitor to the reference potential according to a first control signal; At least one current source having a constant value while the voltage difference between each end is greater than a predetermined level, but generating a current which decreases when the voltage difference between the both ends is less than a predetermined level; Second switches for selectively connecting between the other end of the coupling capacitor and the current source according to the second control signal and the digital output where the active period does not overlap the first control signal; An operational amplifier having first and second input terminals, respectively, virtual or directly connected to a reference potential; And And a third switch connecting one end of the coupling capacitor and the first input terminal of the operational amplifier according to the second control signal. The electronic circuit of claim 9, wherein the current source generates the current such that a time point at which the voltage difference between each end becomes smaller than a predetermined level reaches a time point at which the second control signal is deactivated. 10. The method of claim 9, wherein the current source comprises a metal oxide semiconductor (MOS) transistor biased to a gate-source voltage above a threshold voltage. The current is generated based on the drain current of the MOS transistor. 12. The electronic circuit of claim 11, wherein the voltage difference between the both ends is a drain-source voltage of the MOS transistor. The electronic circuit of claim 9, further comprising an input resistor coupling the input signal and the first input terminal. The electronic circuit of claim 9, wherein the input signal and the analog feedback signal are differential signals. 10. The electronic circuit of claim 9, further comprising a self-calibration circuit for correcting process errors in the current source. 10. The electronic circuit of claim 9, further comprising a self-tuning circuit for correcting the process error of the coupling capacitance. A continuous time delta sigma modulator comprising an active integrator using an operational amplifier receiving an input signal and an analog feedback signal, a quantizer for generating a digital output, and a digital-to-analog converter for converting the digital output to the analog feedback signal. The operational amplifier includes a first input terminal receiving the input signal and an analog feedback signal and second input terminals connected to a reference potential, The digital to analog converter Coupling capacitors; First switches respectively connecting both ends of the coupling capacitor to the reference potential according to a first control signal; At least one current source having a constant value while the voltage difference between each end is greater than a predetermined level, but generating a current which decreases when the voltage difference between the both ends is less than a predetermined level; Second switches for selectively connecting between the other end of the coupling capacitor and the current source according to the second control signal and the digital output where the active period does not overlap the first control signal; And And a third switch connecting one end of the coupling capacitor and the first input terminal of the operational amplifier according to the second control signal. 18. The continuous time delta sigma modulator of claim 17, wherein the current source generates the current such that a time point at which the voltage difference between each end becomes smaller than a predetermined level reaches a time point at which the second control signal is deactivated. 18. The method of claim 17, wherein the current source comprises a metal oxide semiconductor (MOS) transistor biased to a gate-source voltage above a threshold voltage. And the current is generated based on the drain current of the MOS transistor. 20. The continuous time delta sigma modulator of claim 19, wherein the voltage difference between the two ends is a drain-source voltage of the MOS transistor. 18. The continuous time delta sigma modulator of claim 17, further comprising an input resistor coupling the input signal and the first input terminal. 18. The continuous time delta sigma modulator of claim 17, wherein the input signal and the analog feedback signal are differential signals. 18. The continuous time delta sigma modulator of claim 17 further comprising a self-calibration circuit for correcting process errors in the current source. 18. The continuous time delta sigma modulator of claim 17, further comprising a self-tuning circuit for correcting the process error of the coupling capacitance.

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