CN113114251B

CN113114251B - Analog-to-digital converter, sigma-delta modulator and control circuit thereof

Info

Publication number: CN113114251B
Application number: CN202110434911.5A
Authority: CN
Inventors: 吕达文
Original assignee: RDA Microelectronics Beijing Co Ltd
Current assignee: RDA Microelectronics Beijing Co Ltd
Priority date: 2021-04-22
Filing date: 2021-04-22
Publication date: 2024-02-20
Anticipated expiration: 2041-04-22
Also published as: CN113114251A

Abstract

The invention discloses an analog-to-digital converter, an sigma-delta modulator and a control circuit thereof. The sigma-delta modulator includes: the input end of the integrating circuit is used as the input end of the sigma-delta modulator, and the output end of the integrating circuit is connected with the input end of the quantization circuit; the quantization circuit is used for carrying out quantization processing on the integration result output by the integration circuit to generate a digital signal; the input end of the feedback circuit is connected with the output end of the control circuit, the output end of the feedback circuit is connected with the input end of the integrating circuit, and the feedback circuit is used for generating feedback current according to the digital signal and inputting the feedback current into the integrating circuit; and a control circuit for adjusting the feedback current so that a difference between increments of integration results of adjacent two integration periods among the integration results output by the integration circuit based on the feedback current after the adjustment reaches a difference threshold. The sigma-delta modulator has the property of being insensitive to clock jitter.

Description

Analog-to-digital converter, sigma-delta modulator and control circuit thereof

Technical Field

The present invention relates to the field of electronic products, and in particular, to an analog-to-digital converter, an sigma-delta modulator, and a control circuit thereof.

Background

The Sigma-Delta modulator (Sigma-Delta ADC) is an oversampling (oversampling) analog-to-digital converter, and has wide application prospects in the fields of sensors, digital audio, wireless communication, and the like by adopting the oversampling, noise shaping and digital filtering technologies. Currently, the accuracy of sigma-delta modulators remains to be improved.

Disclosure of Invention

The invention aims to overcome the defect that the precision of an sigma-delta modulator in the prior art cannot meet the requirement, and provides an analog-to-digital converter, the sigma-delta modulator and a control circuit thereof.

The invention solves the technical problems by the following technical scheme:

in a first aspect, there is provided a sigma-delta modulator comprising:

the input end of the integrating circuit is used as the input end of the sigma-delta modulator, and the output end of the integrating circuit is connected with the input end of the quantization circuit;

the quantization circuit is used for carrying out quantization processing on the integration result output by the integration circuit to generate a digital signal;

the input end of the feedback circuit is connected with the output end of the control circuit, the output end of the feedback circuit is connected with the input end of the integrating circuit, and the feedback circuit is used for generating feedback current according to the digital signal and inputting the feedback current into the integrating circuit;

the control circuit is used for adjusting the feedback current so that the difference between the increment of the integration results of two adjacent integration periods in the integration results output by the integration circuit based on the feedback current after adjustment reaches a difference threshold.

Optionally, the control circuit is specifically configured to reduce the feedback current to a current threshold before the sigma-delta modulator ends the integration phase, so that a difference between the increments of the integration results of the two adjacent integration periods reaches a difference threshold.

Optionally, the control circuit includes: an image current sub-circuit, a switch sub-circuit and a regulator sub-circuit;

the output end of the mirror current sub-circuit is connected with the input end of the switch sub-circuit, and the control end of the switch sub-circuit is connected with the output end of the regulating sub-circuit; the output end of the switch sub-circuit is used as the output end of the control circuit;

and the regulating sub-circuit reduces the feedback current output by the feedback circuit to a current threshold value by controlling the on or off of the switching sub-circuit.

Optionally, the regulating sub-circuit includes a first switch, a second switch, a third switch, an operational amplifier, a capacitor, and a current source;

the positive-phase input end of the operational amplifier is grounded, the negative-phase input end of the operational amplifier is respectively connected with one end of the first switch, one end of the second switch and one end of the capacitor, the other end of the first switch is grounded, and the second switch is grounded through the current source; the output end of the operational amplifier is connected with the other end of the capacitor and the control end of the switch sub-circuit, and the output end of the operational amplifier is grounded through the third switch.

Optionally, the regulating sub-circuit includes a capacitor and a resistor, one end of the capacitor is connected with the positive power supply, the other end of the capacitor is respectively connected with the control end of the switch sub-circuit and one end of the resistor, and the other end of the resistor is used for inputting a clock signal, and the clock signal is related to an integration phase of the sigma-delta modulator.

Optionally, the switch sub-circuit includes a PMOS transistor, where a gate of the PMOS transistor is used as a control end of the switch sub-circuit, a source of the PMOS transistor is used as an input end of the switch sub-circuit, and a drain of the PMOS transistor is used as an output end of the switch sub-circuit.

In a second aspect, a control circuit is provided for use with a sigma-delta modulator, the sigma-delta modulator comprising a feedback circuit and an integrating circuit;

the control circuit is used for reducing the feedback current output by the feedback circuit to a current threshold before the integrating phase of the sigma-delta modulator is finished, so that the difference between the increment of the integration results of two adjacent integration periods in the integration results output by the integrating circuit based on the feedback current after adjustment reaches a difference threshold.

the output end of the mirror current sub-circuit is connected with the input end of the switch sub-circuit, and the control end of the switch sub-circuit is connected with the output end of the regulating sub-circuit; the output end of the switch sub-circuit is used as the output end of the control circuit.

In a third aspect, there is provided an analog-to-digital converter comprising a digital decimation filter and a sigma-delta modulator according to any of the preceding claims;

the sigma-delta modulator is used for converting an input analog signal into a digital signal;

the digital decimation filter is used for performing decimation filtering processing on the digital signal.

The invention has the positive progress effects that:

in the embodiment of the invention, the control circuit controls the feedback circuit to ensure that the feedback current output by the feedback circuit is not constant current any more, and the feedback current output by the feedback circuit is regulated according to the integration result output by the integration circuit, so that the increment difference of the integration result output by the integration circuit in two adjacent integration periods is zero or small, thereby achieving the purpose of reducing or eliminating the influence of clock jitter on the sigma-delta modulator, and further ensuring that the sigma-delta modulator has the characteristic of insensitivity to the clock jitter.

Drawings

Fig. 1a is a schematic block diagram of an analog-to-digital converter according to an exemplary embodiment of the present invention;

FIG. 1b is a circuit diagram of a discrete time sigma-delta modulator according to an exemplary embodiment of the present invention;

FIG. 1c is a switching timing control diagram of a discrete time sigma-delta modulator according to an exemplary embodiment of the present invention;

FIG. 1d is a schematic diagram of a clock jitter provided by an exemplary embodiment of the present invention;

FIG. 1e is a circuit diagram of a continuous time sigma-delta modulator according to an exemplary embodiment of the present invention;

FIG. 1f is a timing diagram of a feedback error due to clock jitter provided by an exemplary embodiment of the present invention;

FIG. 1g is a timing diagram of an integrated voltage delta error due to clock jitter provided by an exemplary embodiment of the present invention;

FIG. 2 is a block diagram of a sigma-delta modulator according to an exemplary embodiment of the present invention;

FIG. 3 is a timing diagram of an integrated voltage increment that is not noticeable to clock jitter, in accordance with an exemplary embodiment of the present invention;

FIG. 4 is a circuit diagram of a sigma-delta modulator according to an exemplary embodiment of the present invention;

FIG. 5 is a time domain waveform diagram provided by an exemplary embodiment of the present invention;

FIG. 6 is a circuit diagram of another sigma-delta modulator provided in an exemplary embodiment of the present invention;

FIG. 7 is another time domain waveform diagram according to an exemplary embodiment of the present invention

Detailed Description

The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.

Sigma-delta analog-to-digital converters (sigma-delta analog-to-digital converters) are increasingly being used in terms of their high resolution, good linearity, low cost, etc. The sigma-delta analog-to-digital converter consists of two parts, see fig. 1a, the first part being a sigma-delta modulator and the second part being a digital decimation filter. The sigma-delta modulator samples the input analog signal at an extremely high sampling frequency and performs low-order quantization on the difference between the two samples, so as to obtain a digital signal represented by a low-order code, namely a sigma-delta code; this sigma-delta code is then fed to a digital decimation filter of the second part for decimation filtering, resulting in a high resolution linear pulse code modulated digital signal. The digital decimation filter thus effectively corresponds to a transcoder.

The sigma-delta modulator is classified into a discrete time type and a continuous time type. Discrete-time sigma-delta modulators operate by sampling of voltage and transfer of charge, and continuous-time sigma-delta modulators operate by current integration principles.

FIG. 1B is a circuit diagram of a discrete time sigma-delta modulator according to an exemplary embodiment of the present invention, which is exemplified by a sigma-delta modulator with first order bit, referring to FIG. 1B, and includes a sampling circuit A, an integrating circuit B, a feedback circuit C and a quantization circuit D; the sampling circuit A comprises a switch 102, a capacitor 103, a switch 104 and a switch 105; the integrating circuit B includes an operational amplifier 109 and an integrating capacitor 110; the feedback circuit C includes a switch 106, a switch 107, and a voltage source 113 as a reference voltage; the quantization circuit D includes a quantizer 111.

The number of the discrete time type sigma-delta modulators is determined by the number of the integrating circuits, and the n-order sigma-delta modulators comprise n integrating circuits which are sequentially connected in series; the bit number of the discrete time sigma-delta modulator is determined by the bit number of the quantizer, and when the quantizer with i bits is adopted, the bit number of the sigma-delta modulator is i bits.

In the figure, ckb and ck represent clock signals with opposite phases, which are used for controlling the closing and opening of the switch 102, the switch 104 and the switch 105, and the voltage is sampled and integrated through the cooperation of ckb and ck. In the embodiment of the invention, the working principle of the sigma-delta modulator is introduced by taking the example that the switch is closed when the clock signal is in a high level and the switch is opened when the clock signal is in a low level; of course, according to actual requirements, each switch in the sigma-delta modulator can also be set to be opened when the clock signal is at a high level, and be closed when the clock signal is at a low level. Dout represents the digital signal output by the quantizer, and ckb & Dout represents the result of the and operation on ckb and Dout for controlling the closing and opening of the switches 106 and 107. Vin represents an input signal, which is an analog signal.

Fig. 1c is a switching timing control diagram of a discrete-time sigma-delta modulator according to an exemplary embodiment of the present invention, and the following description will discuss the operation of the discrete-time sigma-delta modulator with reference to fig. 1b and 1 c:

fig. 1c shows 4 clock cycles Ts of the clock signals ckb and ck, each clock cycle corresponding to one integration period, each integration period comprising a sampling phase and an integration phase, the sampling phase corresponding to the sampling phase and the integration phase corresponding to the integration phase.

In the sampling phase, ck is high level, ckb is low level, in the figure, the switch 102 and the switch 104 are closed, and the input signal Vin101 charges the capacitor 103 when the switch 105, the switch 106 and the switch 107 are opened; in the case where ck changes from high level to low level, the voltage of the input signal Vin101 is stored in the capacitor 103, and sampling is completed.

During the integration phase, ck is low, ckb is high, switches 102 and 104 are open, switch 105 is closed, and when one of switch 106 and switch 107 is closed, the charge stored on capacitor 103 will be transferred to integrating capacitor 110 through switch 105, thus completing the integration and outputting the integration result.

The quantizer 111 quantizes the integration result (analog signal) output from the integrator circuit into a digital signal Dout, and the integration result (digital signal) of the quantizer is 1 or 0 for 1 integration period for a quantizer with a bit number of 1.

How does the digital output of a bit represent an input signal of different voltage values? This is an over-sampling concept, because the conversion accuracy obtained by one sampling is not high, and multiple sampling averages are required to obtain relatively high accuracy, that is, the magnitude of the voltage value is represented by the digital signal output by the quantizer with multiple integration periods. For example, assuming that the reference voltage vref=1v output by the voltage source 113 is sampled for 10 clock cycles (i.e. 10 integration periods pass) for a constant input signal of vin=0.5V, the digital signal output by the quantizer is 1010101010, wherein the number of "1" accounts for 50%, and it can be determined that the voltage of Vin is 50% of Vref, i.e. 0.5V; for another example, for a constant input signal with vin=0.2v, sampling for 10 clock cycles (i.e. over 10 integration periods) yields a digital output of 1000010000, where the number of "1" s is 20%, it can be determined that the voltage of Vin is 20% of Vref, i.e. 0.2V.

For the discrete time type sigma-delta modulator, the discrete time type sigma-delta modulator works by controlling the on and off of a switch through a clock signal and realizing the sampling of voltage and the transfer of charge, and researches show that the performance of the discrete time type sigma-delta modulator is seriously dependent on the performance of the clock signal. Clock jitter in the clock signal can cause an integrated voltage error in the integrating circuit, reducing the overall SNR (signal-to-noise ratio) of the discrete-time sigma-delta modulator. To obtain a high SNR discrete time sigma-delta modulator, it is necessary to provide it with a clock signal with low clock jitter, which may require up to 1ps for clock jitter, which greatly increases the design difficulty and power consumption of the clock circuit. The clock jitter of the prior clock circuit can only reach about 50ps, the SNR of the discrete time type sigma-delta modulator can only reach about 80dB, and the precision of the discrete time type sigma-delta modulator can not meet the requirements.

The clock signal is provided by a clock circuit, which in practice provides a time difference between the rising or falling edge of the clock signal and the ideal clock signal, which time difference is called clock jitter. Referring to fig. 1d, the ideal clock signal performs high-low level conversion once every half clock period Ts, and precisely outputs a waveform according to the period of the clock period Ts; the inversion time of the high level and the low level of the actual clock signal is not exactly equal to Ts/2, and there is a time difference dt between the actual clock signal and the rising edge or the falling edge of the ideal clock signal, that is, clock jitter, which is random, and the arrival time of each rising edge or each falling edge has a random variation, which cannot be estimated.

Discrete time sigma-delta modulators are commonly used in the low frequency, high precision field, whereas continuous time sigma-delta modulators are more widely used for high frequency, low power applications.

Fig. 1E is a circuit diagram of a continuous-time sigma-delta modulator according to an exemplary embodiment of the present invention, which is exemplified by a sigma-delta modulator with a first order bit, referring to fig. 1E, the continuous-time sigma-delta modulator includes a current converting circuit E, an integrating circuit F, a feedback circuit G, and a quantization circuit H; the current conversion circuit E includes a resistor 202; the integrating circuit F includes an operational amplifier 204 and an integrating capacitor 205; the feedback circuit G includes a switch 203 and a current source 209; the quantization circuit H includes a quantizer 206.

Like a discrete-time sigma-delta modulator, the order of a continuous-time sigma-delta modulator is determined by the number of integrating circuits; the number of bits of the continuous time sigma-delta modulator is determined by the number of bits of the quantizer.

For continuous time sigma-delta modulators, this operates by the principle of current integration. The operation of the continuous-time sigma-delta modulator is described as follows:

during the current transition phase, ckb & Dout is low, switch 203 is open, input signal Vin201 is converted to signal current by resistor 202, and integrating capacitor 205 is continuously charged. This path has no switch nor sampling operation and is insensitive to clock signals.

In the integration stage, ckb & Dout is high, switch 203 is closed, feedback current output by current source 209 charges integration capacitor 205, and the integration is completed, and the integration result is output. This path has a switch and is therefore relatively sensitive to the clock signal, i.e. jitter affects the feedback current.

The feedback current, i.e. the current output by the current source 209 in fig. 1e through the switch 203 and into the integrating circuit. Since the feedback duration of the feedback current is directly related to the high level width of the clock signal, the clock jitter causes a random variation in the high level width of the clock signal (ckb & Dout) in fig. 1e, and the amount of charge output by the current source 209 flowing through the switch 203 to the integrating capacitor 205 is different, see fig. 1f, which introduces a feedback voltage error, which causes an integrating voltage error in the integrating circuit, and a feedback error introduced by the clock jitter. Referring to fig. 1f, if the high level width of the actual clock signal is larger than the high level width of the ideal clock signal, the high level width of the actual feedback current is larger than the high level width of the ideal feedback current, introducing a positive feedback error, and if the high level width of the actual clock signal is smaller than the high level width of the ideal clock signal, the high level width of the actual feedback current is smaller than the high level width of the ideal feedback current, introducing a negative feedback error.

Referring again to fig. 1g, the "switch voltage" in the figure corresponds to the clock signal ckb & Dout208 in fig. 1e for controlling the switch 203 to be turned on or off, and the width of the high level is affected by clock jitter; the "feedback current" corresponds to the current outputted from the current source 209 through the switch 203 and inputted to the integrating circuit in fig. 1e, the current outputted from the current source 209 is constant, but when the "switch voltage" is at a low level, the switch 203 is turned off, and the "feedback current" also becomes 0; the integrator is used for integrating the sum of the feedback current and the signal current converted by the resistor 202, and the integration result is the area of a shaded part in the graph; the "integral voltage increment" corresponds to the increment of the integral result output by the integral circuit in two adjacent integral periods in fig. 1e, that is, the first ramp wave in the integral voltage increment waveform represents the integral result output by the integral circuit at the end of the first clock period, the second ramp wave represents the difference between the integral result output by the integral circuit at the end of the second clock period and the integral result output by the integral circuit at the end of the first clock period, the third ramp wave represents the difference between the integral result output by the integral circuit at the end of the third clock period and the integral result output by the integral circuit at the end of the second clock period, and so on.

As is evident from fig. 1g, the magnitude of the integral voltage increment obtained for each clock cycle is different, and there is a random error, which increases the output noise of the continuous-time sigma-delta modulator as a whole, and causes a decrease in the signal-to-noise ratio, thereby resulting in a decrease in accuracy.

It can be seen that the performance of both continuous-time sigma-delta modulators and discrete-time sigma-delta modulators is affected by the clock jitter of the clock signal, resulting in a reduced signal-to-noise ratio and an impact on accuracy.

Based on the above situation, the invention provides a sigma-delta modulator, so that the integration result output by an integration circuit in the sigma-delta modulator is not influenced by clock jitter of a clock signal, and thus the problem of integral noise rise of the sigma-delta modulator caused by random error of the integration result can be eliminated.

Fig. 2 is a circuit diagram of a sigma-delta modulator according to an exemplary embodiment of the present invention, referring to fig. 2, the sigma-delta modulator includes: the device comprises an integrating circuit, a quantizing circuit, a feedback circuit and a control circuit.

The input end of the integrating circuit is used as the input end of the integrating triangle modulator, the output end of the integrating circuit is connected with the input end of the quantizing circuit, the output end of the quantizing circuit is used as the output end of the integrating triangle modulator, and the output end of the quantizing circuit is also connected with the control end of the feedback circuit; the input end of the feedback circuit is connected with the output end of the control circuit, and the output end of the feedback circuit is connected with the input end of the integrating circuit.

The feedback circuit is used for generating feedback current according to the digital signal Dout output by the quantizer, and the control circuit is used for adjusting the feedback current so that the integration circuit is used for integrating the input signal Vin and the adjusted feedback current. The feedback current is input into the integrating circuit, so that the difference between the increment of the integrating result output by the integrating circuit corresponding to the adjacent two integrating periods reaches a difference threshold value, and the effect of reducing or eliminating the integrating voltage error caused by clock jitter is achieved. The quantization circuit is used for carrying out quantization processing on the integration result output by the integration circuit to generate a digital signal Dout.

The difference threshold may be a specific value or a range of values. The difference threshold can be set by itself according to practical situations, and theoretically, the closer to zero, the better. When the difference threshold is 0, referring to fig. 3, the integral voltage increment in the graph is equal, that is, the error of the integral voltage increment caused by clock jitter is eliminated, so that the precision of the sigma-delta modulator is improved.

In the embodiment of the invention, the control circuit controls the feedback circuit to ensure that the feedback current output by the feedback circuit is not constant as shown in fig. 1b and 1e in the integration stage of the sigma-delta modulator, and the feedback current output by the feedback circuit is adjusted according to the integration result output by the integration circuit, so that the increment difference of the integration result output by the integration circuit in two adjacent integration periods reaches a difference value threshold value, thereby achieving the purpose of reducing or eliminating the influence of clock jitter.

In one embodiment, the control circuit achieves the purpose of reducing or eliminating the integrated voltage error caused by clock jitter by reducing the feedback current to a current threshold before the integrating delta modulator ends the integration phase such that the difference between the increments of the integrated results output by the integrating circuit in adjacent two integration periods reaches a difference threshold, i.e. the difference between the increments of the integrated results output by the integrating circuit in adjacent two integration periods reaches a difference threshold. Thus, referring to fig. 3, during the integration phase, the "feedback current" is no longer a constant current, but a current that decays to a current threshold for a finite time (before the sigma-delta modulator ends the integration phase) for a duration less than the minimum high level width. The minimum high level width is the high level width with the minimum width in each clock period of the clock signal controlling the sigma-delta modulator in the integration stage. For example, in fig. 3, the switching voltage waveform includes 4 clock cycles, in which the width of the high level of the second clock cycle is the smallest, and the width of the high level of the second clock cycle is determined as the smallest high level width.

Before the integrating triangle modulator ends the integrating phase, if the feedback current is reduced to 0 (current threshold), the increment of the integrating voltage output by the integrating circuit, that is, the area of the feedback current waveform in fig. 3 is a fixed value, and the amplitude of the increment of the integrating voltage is also a fixed value, which is irrelevant to the switching time of the high level and the low level of the clock signal for controlling the switch to be closed and opened, and is irrelevant to the width of the high level. I.e. the integration voltage per clock cycle is no longer related to the width of the high level of the clock but becomes related to the rising edge of the clock signal only, becomes an edge triggered signal, and as soon as a rising edge of the clock signal occurs, the sigma-delta modulator is in the integration phase, the feedback circuit feeds back a voltage value to the integration circuit, whereas before the clock signal switches to a low level, i.e. before the sigma-delta modulator ends the integration phase, the feedback circuit has stopped feeding back the voltage value to the integration circuit, which in fact results in that the feedback is not only independent of the width of the clock signal, but also independent of the jitter of the rising edge of the clock signal. Thus, the "integral voltage delta" in fig. 3 is no longer a difference between different integration periods, but the magnitude of the integral voltage delta per clock period is a fixed value, which eliminates the integral voltage error.

In one embodiment, referring to fig. 4, a continuous time sigma-delta modulator is used as an example to illustrate the operation of the control circuit. The control circuit comprises an image current sub-circuit a, a switch sub-circuit b and a regulating sub-circuit c; the output end of the mirror current sub-circuit a is connected with the input end of the switch sub-circuit b, and the control end of the switch sub-circuit b is connected with the output end of the regulating sub-circuit c; the output end of the switch sub-circuit b is used as the output end of the control circuit and is connected with the input end of the feedback circuit; the regulating sub-circuit c is used for reducing the feedback current output by the feedback circuit to a current threshold value by controlling the opening or closing of the switching sub-circuit b before the integrating triangle modulator ends the integrating phase.

The mirror current sub-circuit a comprises a current source 701, a PMOS tube 702 and a PMOS tube 703, one end of the current source 701 is grounded, the other end of the current source 701 is connected with the drain electrode of the PMOS tube 702, the source electrode of the PMOS tube 702 is connected with a power supply VDD, the grid electrode of the PMOS tube 702 is connected with the grid electrode of the PMOS tube 703, the source electrode of the PMOS tube 703 is connected with the power supply VDD, and the drain electrode of the PMOS tube 703 is used as the output end of the mirror current sub-circuit a.

The switch sub-circuit b comprises a PMOS tube 704, the grid electrode of the PMOS tube 704 is connected with the output end of the regulating sub-circuit c, the source electrode is connected with the output end of the mirror image current sub-circuit, and the drain electrode is connected with the input end of the integrating circuit through a switch 712 of the feedback circuit.

The regulating sub-circuit c includes a third switch 705, an operational amplifier 707, a capacitor 706, a second switch 708, a first switch 717, and a current source 709; the positive phase input end of the operational amplifier 707 is grounded, the negative input end of the operational amplifier 707 is respectively connected with one end of the second switch 708, one end of the first switch 717 and one end of the capacitor 706, the other end of the second switch 708 is grounded through the current source 709, and the other end of the first switch 717 is grounded; an output terminal of the operational amplifier 707 is connected to the other terminal of the capacitor 706 and to a control terminal of the switching sub-circuit, and is further grounded through a third switch 705.

Fig. 5 is a time domain waveform diagram according to an exemplary embodiment of the present invention, and the working principle of the control circuit in fig. 4 is described below with reference to fig. 5:

before time t1, ck is high, ckb is low, switch 705 is closed, switch 712 is open in fig. 4, then the gate voltage of PMOS transistor 704 becomes low, both the drain voltage and the source voltage become high, PMOS transistor 704 is open, in the linear region, and no current flows. The same holds true for PMOS tube 703 which is on but no current flows. Switch 705 and switch 717 are simultaneously closed and the charge on capacitor 706 is released.

In the period t1 to t2 ck goes low and ckb goes high, in fig. 4, switch 705 is open and switch 708 is closed, the current of current source 709 can flow to capacitor 706, and op-amp 707 and integrating capacitor 706 form an integrator whose input current is constant (provided by current source 709), which causes the potential at the output of the integrator, i.e. node 710, to appear as a constant slope rising pattern, such as the potential waveform of node 710 of fig. 5.

During the time period t1 to t2, the potential of node 711 increases linearly with the potential of node 710, and since node 711 is at a lower potential, PMOS tube 703 operates in the saturation region, and the current (supplied by current source 701) mirrored PMOS tube 702 remains constant, see the waveform of the current at node 702 and the waveform of the current at node 703 in FIG. 5.

During the period of t2 to t3, the potential of node 710 continues to increase linearly, but the potential of node 711 continues to increase such that PMOS tube 703 enters a linear region, which is no longer able to replicate the current of PMOS tube 702, but the smaller the current, the smaller the current of PMOS tube 703 decreases such that the bias voltage VGS of PMOS tube 704 also becomes smaller, and thus the potential of node 711 no longer increases linearly.

As shown in fig. 5, at time t3, the potential of node 711 changes to the supply potential VDD, resulting in no more current on PMOS tube 703, then for fig. 4, although switch 712 is closed, no current has been flowing through integrating capacitor 715, and the integration process ends.

During the period t3 to t4, the potential at node 710 continues to increase linearly until VDD is reached, during which time PMOS transistor 704 is in the off-state and no more current flows through PMOS transistor 703.

t5 is the time when the falling edge of the clock signal ckb arrives, as can be seen from fig. 5, the 703 current (i.e. the feedback current) has decayed to 0 before the time t5, so that the feedback current is not affected by the high level width of the clock, i.e. the feedback current is not affected by clock jitter.

It should be noted that the above-mentioned control circuit is applicable not only to the continuous time type sigma-delta modulator shown in fig. 4, but also to the discrete time type sigma-delta modulator, and is applicable not only to the sigma-delta modulator of one order bit, but also to the sigma-delta modulator of multiple orders and/or multiple bits. For a multi-bit sigma-delta modulator, multiple current source feedback is required.

Therefore, the feedback current output by the feedback circuit is regulated by the control circuit, so that in the integration stage of the sigma-delta modulator, the feedback current is not constant but is attenuated to a current threshold before the integration stage is finished, namely, the feedback current output by the feedback circuit is non-constant current, the non-constant current is obtained by controlling the control circuit and is irrelevant to the width of the high level of the clock signal, the integration result output by the integration circuit is irrelevant to the width of the clock signal, and the sigma-delta modulator has the characteristic of insensitivity to clock jitter.

The regulating sub-circuit is not limited to the implementation shown in fig. 4, and the regulating sub-circuit may be flexibly changed, and fig. 6 is a circuit diagram of another sigma-delta modulator according to an exemplary embodiment of the present invention, and the control circuit includes a mirror current sub-circuit a, a switch sub-circuit b, and a regulating sub-circuit c.

The mirror current sub-circuit a comprises a current source 901, a PMOS tube 902 and a PMOS tube 903, one end of the current source 901 is grounded, the other end of the current source 901 is connected with the drain electrode of the PMOS tube 902, the source electrode of the PMOS tube 902 is connected with a power supply VDD, the grid electrode of the PMOS tube 902 is connected with the grid electrode of the PMOS tube 903, the source electrode of the PMOS tube 903 is connected with the power supply VDD, and the drain electrode of the PMOS tube 903 is used as the output end of the mirror current sub-circuit a.

The switch sub-circuit b comprises a PMOS tube 904, the grid electrode of the PMOS tube 904 is connected with the output end of the regulating sub-circuit c, the source electrode is connected with the output end of the mirror image current sub-circuit, and the drain electrode is connected with the input end of the integrating circuit through a switch 909 of the feedback circuit.

The regulator sub-circuit in this embodiment is different from the regulator sub-circuit shown in fig. 4, in this embodiment, the regulator sub-circuit includes a capacitor 905 and a resistor 906, one end of the capacitor 905 is connected to a power supply VDD, the other end of the capacitor 905 is connected to the gate of the PMOS transistor 904 and one end of the resistor 906, the other end of the resistor 906 is used for inputting a clock signal ckb, and in this embodiment, the nonlinear charging of the capacitor 905 by the resistor 906 replaces the linear charging of the integrator (including the operational amplifier 707 and the capacitor 706) in fig. 4.

Fig. 7 is a time domain waveform diagram according to an exemplary embodiment of the present invention, and the working principle of the control circuit in fig. 6 is described below with reference to fig. 7:

in fig. 7, the state before time t1 is substantially the same as that of fig. 5, the only difference being that the voltage at node 907 is slowly decreasing, because the charge on capacitor 905 needs to be released through resistor 906, which is a non-linear discharge process.

The difference between the time period t1 to t4 in fig. 7 and the time period t1 to t4 in fig. 5 is that the rise in voltage at point 710 in fig. 5 is linear, whereas the rise in voltage at node 907 in fig. 7 is exponentially varying as e, in theory node 907 never charges to VDD, but we do not care because PMOS transistor 904 has turned off and node 908 has increased to VDD when the voltage at node 907 charges to time t3, at which point no current has been drawn on PMOS transistor 903 and the integration process of the system has ended.

The operation states of 901 to 904 in fig. 7 are identical to 701 to 704 in fig. 5, and will not be described again.

Compared to the sigma-delta modulator shown in fig. 4, in this embodiment, the feedback current is adjusted by a simpler circuit, so that in the integration phase of the sigma-delta modulator, the feedback current is not a constant current but is attenuated to the current threshold before the end of the integration phase, that is, the feedback current output by the feedback circuit is a non-constant current, and the non-constant current is obtained by the control circuit, and is independent of the width of the high level of the clock signal, so that the integration result output by the integration circuit is independent of the width of the clock signal, and the sigma-delta modulator has the characteristic of being insensitive to clock jitter.

In any of the embodiments, an NMOS tube may be used instead of a PMOS tube, and if the NMOS tube is used instead of the PMOS tube, the connection relationship of the devices in the circuit needs to be modified, and the detailed implementation process is not repeated here.

The embodiment of the invention also provides an analog-to-digital converter, which comprises a digital decimation filter and the sigma-delta modulator according to any one of the above;

the digital decimation filter is used for performing decimation filtering processing on the digital signal. Thereby obtaining a high-resolution linear pulse code modulated digital signal.

While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.

Claims

1. A sigma-delta modulator, comprising:

the input end of the feedback circuit is connected with the output end of the control circuit, the output end of the feedback circuit is connected with the input end of the integration circuit, and the feedback circuit is used for generating feedback current according to the digital signal and inputting the feedback current into the integration circuit;

the control circuit is used for adjusting the feedback current so that the difference between the increment of the integration results of two adjacent integration periods in the integration results output by the integration circuit based on the feedback current after adjustment reaches a difference threshold;

the control circuit includes: an image current sub-circuit, a switch sub-circuit and a regulator sub-circuit;

2. The sigma-delta modulator of claim 1, wherein said control circuit is operable to reduce said feedback current to a current threshold value such that a difference between increments of integration results of said adjacent two integration periods reaches a difference threshold value, in particular before said sigma-delta modulator ends an integration phase.

3. The sigma-delta modulator of claim 1, wherein said regulation subcircuit comprises a first switch, a second switch, a third switch, an operational amplifier, a capacitor, and a current source;

4. The sigma-delta modulator of claim 1, wherein said regulation sub-circuit comprises a capacitor and a resistor, one end of said capacitor being connected to a positive power supply, the other end of said capacitor being connected to a control terminal of said switching sub-circuit and to one end of said resistor, respectively, the other end of said resistor being for inputting a clock signal, said clock signal being associated with an integration phase of said sigma-delta modulator.

5. The sigma-delta modulator of claim 1, wherein the switching sub-circuit comprises a PMOS transistor, a gate of the PMOS transistor being a control terminal of the switching sub-circuit, a source being an input terminal of the switching sub-circuit, and a drain being an output terminal of the switching sub-circuit.

6. A control circuit applied to a sigma-delta modulator, the sigma-delta modulator comprising a feedback circuit and an integrating circuit;

the control circuit is used for reducing the feedback current output by the feedback circuit to a current threshold before the integrating phase of the sigma-delta modulator is finished, so that the difference between the increment of the integration results of two adjacent integration periods in the integration results output by the integrating circuit based on the feedback current after adjustment reaches a difference threshold; the control circuit includes: an image current sub-circuit, a switch sub-circuit and a regulator sub-circuit;

7. An analog-to-digital converter comprising a digital decimation filter and a sigma-delta modulator according to any one of claims 1-5;