KR100787311B1 - Method for forming a dual gate insulation - Google Patents

Method for forming a dual gate insulation Download PDF

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KR100787311B1
KR100787311B1 KR1020010089112A KR20010089112A KR100787311B1 KR 100787311 B1 KR100787311 B1 KR 100787311B1 KR 1020010089112 A KR1020010089112 A KR 1020010089112A KR 20010089112 A KR20010089112 A KR 20010089112A KR 100787311 B1 KR100787311 B1 KR 100787311B1
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oxide film
semiconductor substrate
gate oxide
forming
dual gate
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KR20030058598A (en
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선우경
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02249—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by combined oxidation and nitridation performed simultaneously
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma

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Abstract

본 발명은 듀얼(Dual) 게이트 산화막의 형성 방법에 관한 것으로, 특히 반도체 기판에 중수소를 주입한 후 듀얼 게이트 산화막의 형성 공정을 진행하므로, 상기 중수소가 결합성이 우수하기 때문에 종래의 열 산화막과 반도체 기판의 불포화 결합 대신 상기 중수소와 반도체 기판의 불포화 결합이 발생되어 종래의 4Å 이하 두께의 열 산화막 성장 공정 시 발생되는 터널링(Tunneling) 현상을 방지하므로 소자의 집적화, 수율 및 신뢰성을 향상시킨다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a dual gate oxide film. In particular, since a process of forming a dual gate oxide film is performed after injecting deuterium into a semiconductor substrate, since the deuterium has excellent bonding properties, the conventional thermal oxide film and the semiconductor Unsaturated bonds between the deuterium and the semiconductor substrate are generated in place of the unsaturated bonds of the substrate, thereby preventing tunneling occurring during the conventional thermal oxide growth process having a thickness of 4 두께 or less, thereby improving device integration, yield, and reliability.

Description

듀얼 게이트 산화막의 형성 방법{Method for forming a dual gate insulation}Method for forming a dual gate insulation

도 1a와 도 1b는 종래 기술에 따른 듀얼 게이트 산화막의 형성 방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method of forming a dual gate oxide film according to the prior art.

도 2a 내지 도 2c는 본 발명의 실시 예에 따른 듀얼 게이트 산화막의 형성 방법을 도시한 단면도.2A to 2C are cross-sectional views illustrating a method of forming a dual gate oxide film according to an exemplary embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11, 31: 반도체 기판 13, 37: 감광막 패턴11 and 31: semiconductor substrate 13 and 37: photosensitive film pattern

15, 3: 질소 이온 17, 339: 게이트 산화막15, 3: nitrogen ion 17, 339: gate oxide film

33: 중수소 이온 35: 산화막33: deuterium ion 35: oxide film

본 발명은 듀얼(Dual) 게이트 산화막의 형성 방법에 관한 것으로, 특히 반도체 기판에 중수소를 주입한 후 듀얼 게이트 산화막의 형성 공정을 진행하여 소자의 집적화, 수율 및 신뢰성을 향상시키는 듀얼 게이트 산화막의 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a dual gate oxide film. In particular, a method of forming a dual gate oxide film to improve integration, yield, and reliability of a device by injecting deuterium into a semiconductor substrate and then proceeding to form a dual gate oxide film. It is about.                         

듀얼 게이트 산화막 공정은 동일 웨이퍼 내에서 두께가 서로 다른 두 가지 종류의 게이트 산화막을 형성하는 공정으로서, 빠른 동작을 요구하는 코아(Core) 칩 부분과 신뢰성이 중요시되는 입/출력 블록(Block)으로 구성되는 회로 소자에서 일반적으로 사용하는 공정이다.The dual gate oxide film process is to form two kinds of gate oxide films having different thicknesses in the same wafer. The dual gate oxide film process is composed of a core chip portion requiring fast operation and an input / output block where reliability is important. It is a process generally used in circuit devices.

도 1a와 도 1b는 종래 기술에 따른 듀얼 게이트 산화막의 형성 방법을 도시한 단면도로서,“Ⅰ”는 고 신뢰성이 요구되는 영역인 제 1 영역을 도시한 것이고,“Ⅱ”는 고 스피드가 요구되는 영역인 제 2 영역을 도시한 것이다.1A and 1B are cross-sectional views showing a method of forming a dual gate oxide film according to the prior art, in which “I” shows a first region which is a region requiring high reliability, and “II” shows a high speed required. The second area, which is the area, is shown.

도 1a를 참조하면, 반도체 기판(11)상에 감광막을 도포하고, 상기 감광막을 상기 제 1 영역(Ⅰ)에만 남도록 선택적으로 노광 및 현상하여 감광막 패턴(13)을 형성한다.Referring to FIG. 1A, a photoresist film is coated on a semiconductor substrate 11, and the photoresist film is selectively exposed and developed to remain only in the first region I to form a photoresist pattern 13.

그리고, 상기 감광막 패턴(13)을 마스크로 하는 이온 주입 공정에 의해 상기 제 2 영역(Ⅱ)의 반도체 기판(11)에 질소 이온(15)을 주입한다.Then, nitrogen ions 15 are implanted into the semiconductor substrate 11 in the second region (II) by an ion implantation process using the photosensitive film pattern 13 as a mask.

도 1b를 참조하면, 상기 감광막 패턴(13)을 제거하고, 열산화 공정으로 상기 반도체 기판(11) 상에 게이트 산화막(17)을 형성한다. 이때, 상기 제 2 영역(Ⅱ)의 게이트 산화막(17)은 상기 질소 이온(15)이 주입되어 상기 제 1 영역(Ⅰ)의 게이트 산화막(17)보다 그 두께가 얇게 형성되어 듀얼 게이트 산화막을 형성한다.Referring to FIG. 1B, the photoresist layer pattern 13 is removed and a gate oxide layer 17 is formed on the semiconductor substrate 11 by a thermal oxidation process. In this case, the gate oxide film 17 of the second region (II) is implanted with the nitrogen ions 15 to be thinner than the gate oxide film 17 of the first region (I) to form a dual gate oxide film. do.

그러나 종래의 듀얼 게이트 산화막의 형성 방법은 열 산화막의 두께를 다르게 하여 듀얼 게이트 산화막을 형성하므로, 전기적으로 상기 4Å 이하 두께의 열 산화막은 반도체 기판의 표면 또는 계면에서 포화되지 않는 실리콘 결합에 의해 발생되는 불포화 결합을 하기 때문에 터널링(Tunneling)을 일으키는 등 게이트 산화막으로의 역할을 할 수 없으므로 소자의 수율 및 신뢰성이 저하되는 문제점이 있었다.However, in the conventional method of forming the dual gate oxide film, since the dual gate oxide film is formed by varying the thickness of the thermal oxide film, the thermal oxide film having a thickness of 4 Å or less is generated by silicon bonding that is not saturated at the surface or interface of the semiconductor substrate. Since unsaturated bonds do not act as gate oxides such as tunneling, the yield and reliability of the device are deteriorated.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 반도체 기판에 중수소를 주입한 후 듀얼 게이트 산화막의 형성 공정을 진행하므로, 종래의 4Å 이하 두께의 열 산화막 성장 공정 시 발생되는 터널링 현상을 방지하는 듀얼 게이트 산화막의 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above problems, and since the process of forming a dual gate oxide film after injecting deuterium into a semiconductor substrate, the dual to prevent the tunneling phenomenon occurring during the conventional thermal oxide growth process of less than 4kW thick Its purpose is to provide a method for forming a gate oxide film.

이상의 목적을 달성하기 위한 본 발명은 고 신뢰성이 요구되는 제 1 영역과 고 스피드가 요구되는 제 2 영역이 각각 정의된 기판에 이온 주입 공정으로 중수소 이온을 주입하는 단계, 상기 제 2 영역의 반도체 기판 상에 질소 이온이 함유된 산화막을 형성하는 단계, 상기 산화막과 제 1 영역의 반도체 기판 상에 게이트 산화막을 성장시키는 단계를 포함하는 듀얼 게이트 산화막의 형성 방법을 제공하는 것과,The present invention for achieving the above object is a step of injecting deuterium ions into the substrate defined by the first region is required for high reliability and the second region is required for high speed by an ion implantation process, the semiconductor substrate of the second region Providing a method of forming a dual gate oxide film comprising forming an oxide film containing nitrogen ions thereon, and growing a gate oxide film on the oxide film and a semiconductor substrate in a first region;

상기 중수소 이온을 주입하는 단계는 20 ∼ 30 KeV의 이온 주입 에너지로 5E13 ∼ 1E15/㎠ 도즈량을 상기 반도체 기판에 주입하는 것과,The step of implanting deuterium ions is to inject 5E13 ~ 1E15 / ㎠ dose to the semiconductor substrate with an ion implantation energy of 20 ~ 30 KeV,

상기 산화막을 N2 또는 NH3 분위기의 어닐 공정 또는 RPN 공정으로 형성하는 것을 특징으로 한다.The oxide film is formed by an annealing process or an RPN process in an N 2 or NH 3 atmosphere.

본 발명의 원리는 반도체 기판에 중수소를 주입한 후 듀얼 게이트 산화막의 형성 공정을 진행하므로, 상기 중수소가 결합성이 우수하기 때문에 종래의 열 산화막과 반도체 기판의 불포화 결합 대신 상기 중수소와 반도체 기판의 불포화 결합이 발생되어 종래의 4Å 이하 두께의 열 산화막 성장 공정 시 발생되는 터널링 현상을 방지하는 발명이다.In the principle of the present invention, since the process of forming the dual gate oxide film is performed after the injection of deuterium into the semiconductor substrate, since the deuterium has excellent bondability, the desaturation of the deuterium and the semiconductor substrate instead of the unsaturated bond of the conventional thermal oxide film and the semiconductor substrate is performed. Bonding occurs to prevent the tunneling phenomenon that occurs during the conventional thermal oxide film growth process of less than 4Å thickness.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명의 실시 예에 따른 듀얼 게이트 산화막의 형성 방법을 도시한 단면도로서,“Ⅰ”는 고 신뢰성이 요구되는 영역인 제 1 영역을 도시한 것이고,“Ⅱ”는 고 스피드가 요구되는 영역인 제 2 영역을 도시한 것이다.2A through 2C are cross-sectional views illustrating a method of forming a dual gate oxide film according to an exemplary embodiment of the present invention, in which “I” illustrates a first region in which high reliability is required, and “II” represents a high speed. Fig. 2 shows a second area in which is required area.

도 2a를 참조하면, 20 ∼ 30 KeV의 에너지로 반도체 기판(31)에 5E13 ∼ 1E15/㎠ 도즈(Dose)량의 중수소 이온(33)을 주입한 후, 중수소 또는 ND3 분위기의 어닐(Anneal) 공정을 진행한다.Referring to FIG. 2A, after injecting 5E13 to 1E15 / cm 2 dose of deuterium ions 33 into the semiconductor substrate 31 with an energy of 20 to 30 KeV, annealing in deuterium or ND 3 atmosphere is performed. Proceed with the process.

도 2b를 참조하면, N2 또는 NH3 분위기의 어닐 공정 또는 RPN(Remote Plasma Nitridation) 공정으로 상기 반도체 기판(31) 상에 질소 이온이 많이 함유된 산화막(35)을 형성한다. 이때, 상기 질소 이온이 많이 함유된 산화막(35)은 상기 반도체 기판(31)에 주입된 중수소 이온(33)의 해리를 방지하는 역할을 한다.Referring to FIG. 2B, an oxide film 35 containing a large amount of nitrogen ions is formed on the semiconductor substrate 31 by an annealing process in an N 2 or NH 3 atmosphere or a remote plasma nitridation (RPN) process. At this time, the oxide film 35 containing a large amount of nitrogen ions serves to prevent the dissociation of the deuterium ions 33 injected into the semiconductor substrate 31.

그리고, 상기 산화막(35) 상에 감광막을 도포하고, 상기 감광막을 상기 제 1 영역(Ⅰ)에만 제거되도록 선택적으로 노광 및 현상하여 감광막 패턴(37)을 형성한다.Then, a photoresist film is coated on the oxide film 35, and the photoresist film is selectively exposed and developed to be removed only in the first region I to form a photoresist pattern 37.

이어, 상기 감광막 패턴(37)을 마스크로 상기 제 1 영역(Ⅰ)의 산화막(35)을 식각한다.Subsequently, the oxide layer 35 of the first region I is etched using the photoresist pattern 37 as a mask.

도 2c를 참조하면, 상기 감광막 패턴(37)을 제거하고, 열산화 공정으로 상기 반도체 기판(31)과 산화막(35) 상에 게이트 산화막(39)을 형성한다. 이때, 상기 제 2 영역(Ⅱ)의 게이트 산화막(39)은 상기 질소 이온이 많이 함유된 산화막(35)에 의해 상기 제 1 영역(Ⅰ)의 게이트 산화막(39)보다 그 두께가 얇게 형성되어 듀얼 게이트 산화막을 형성한다.Referring to FIG. 2C, the photoresist layer pattern 37 is removed and a gate oxide layer 39 is formed on the semiconductor substrate 31 and the oxide layer 35 by a thermal oxidation process. At this time, the gate oxide film 39 of the second region (II) is formed to be thinner than the gate oxide film 39 of the first region (I) by the oxide film 35 containing a large amount of nitrogen ions. A gate oxide film is formed.

본 발명의 듀얼 게이트 산화막의 형성 방법은 반도체 기판에 중수소를 주입한 후 듀얼 게이트 산화막의 형성 공정을 진행하므로, 상기 중수소가 결합성이 우수하기 때문에 종래의 열 산화막과 반도체 기판의 불포화 결합 대신 상기 중수소와 반도체 기판의 불포화 결합이 발생되어 종래의 4Å 이하 두께의 열 산화막 성장 공정 시 발생되는 터널링 현상을 방지하므로 소자의 집적화, 수율 및 신뢰성을 향상시키는 효과가 있다.In the method of forming a dual gate oxide film according to the present invention, since deuterium is injected into a semiconductor substrate and then a dual gate oxide film is formed, the deuterium has excellent bonding property, so the deuterium is replaced with the unsaturated bond between the conventional thermal oxide film and the semiconductor substrate. And unsaturated bonds of the semiconductor substrate are prevented, thereby preventing tunneling occurring during the conventional thermal oxide growth process of 4 Å or less in thickness, thereby improving integration, yield, and reliability of the device.

Claims (3)

고 신뢰성이 요구되는 제 1 영역과 고 스피드가 요구되는 제 2 영역이 각각 정의된 기판에 중수소 이온을 주입하는 단계;Implanting deuterium ions into a substrate in which a first region requiring high reliability and a second region requiring high speed are respectively defined; 상기 제 2 영역의 반도체 기판 상에 질소 이온이 함유된 산화막을 형성하는 단계;Forming an oxide film containing nitrogen ions on the semiconductor substrate of the second region; 상기 산화막과 제 1 영역의 반도체 기판 상에 게이트 산화막을 성장시키는 단계를 포함하는 듀얼 게이트 산화막의 형성 방법.And growing a gate oxide film on the oxide film and the semiconductor substrate in the first region. 제 1 항에 있어서,The method of claim 1, 상기 중수소 이온을 주입하는 단계는 20 ∼ 30 KeV의 이온 주입 에너지로 5E13 ∼ 1E15/㎠ 도즈량을 상기 반도체 기판에 주입함을 특징으로 하는 듀얼 게이트 산화막의 형성 방법.The method of implanting deuterium ions comprises implanting 5E13-1E15 / cm 2 dose into the semiconductor substrate at an ion implantation energy of 20 to 30 KeV. 제 1 항에 있어서,The method of claim 1, 상기 산화막을 N2 또는 NH3 분위기의 어닐 공정 또는 RPN 공정으로 형성함을 특징으로 하는 듀얼 게이트 산화막의 형성 방법.The oxide film is formed by an annealing process in a N 2 or NH 3 atmosphere or a RPN process.
KR1020010089112A 2001-12-31 2001-12-31 Method for forming a dual gate insulation KR100787311B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000004483A (en) * 1998-06-30 2000-01-25 김영환 Method for forming dual gate oxide
KR20010046508A (en) * 1999-11-12 2001-06-15 박종섭 Method for fabricating of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000004483A (en) * 1998-06-30 2000-01-25 김영환 Method for forming dual gate oxide
KR20010046508A (en) * 1999-11-12 2001-06-15 박종섭 Method for fabricating of semiconductor device

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