KR100780770B1 - Method of manufacturing a semiconductor device having a structure of a recess gate - Google Patents

Method of manufacturing a semiconductor device having a structure of a recess gate Download PDF

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KR100780770B1
KR100780770B1 KR1020060059903A KR20060059903A KR100780770B1 KR 100780770 B1 KR100780770 B1 KR 100780770B1 KR 1020060059903 A KR1020060059903 A KR 1020060059903A KR 20060059903 A KR20060059903 A KR 20060059903A KR 100780770 B1 KR100780770 B1 KR 100780770B1
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South Korea
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recess
semiconductor substrate
threshold voltage
gate
photoresist pattern
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KR1020060059903A
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Korean (ko)
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이민용
노경봉
정용수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Abstract

A method for manufacturing a semiconductor device having a recess gate structure is provided to prevent alternation of a threshold voltage and device characteristic by implanting a punch-through prevention ion when a photoresist pattern remains. A recess(115) is formed on a selected region of a semiconductor substrate(100) on which an active region is defined. A threshold voltage control ion is selectively implanted into the recess. A gate structure is deposited on the semiconductor substrate including the recess. A photoresist pattern(135) for defining a gate is formed to include the recess. The gate structure is etched in form of the photoresist pattern to form a recess gate. A punch-through prevention ion is implanted into the entire exposed active region when a photoresist pattern remains. When the recess is formed, a mask pattern is formed until the selected region of the semiconductor substrate is exposed. The semiconductor substrate exposed by the mask pattern is etched to form the recess. The threshold voltage control ion is implanted into the recess. The mask pattern is removed.

Description

리세스 게이트 구조를 갖는 반도체 소자의 제조방법{Method of manufacturing a semiconductor device having a structure of a recess gate}Method of manufacturing a semiconductor device having a recess gate structure {Method of manufacturing a semiconductor device having a structure of a recess gate}

도 1은 종래 방식에 따른 문턱 전압 조절층 및 펀치스루 방지용 이온층이 형성된 리세스 게이트 구조의 반도체 소자를 보여주는 개략도이다.1 is a schematic diagram illustrating a semiconductor device having a recess gate structure in which a threshold voltage adjusting layer and a punchthrough prevention ion layer according to the related art are formed.

도 2a 내지 도 2b는 본 발명에 따른 리세스 게이트 구조를 갖는 반도체 소자의 제조방법을 설명하기 위한 각 공정별 단면도이다. 2A to 2B are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device having a recess gate structure according to the present invention.

본 발명은 리세스 게이트 구조를 갖는 반도체 소자의 제조방법에 관한 것으로, 보다 구체적으로는 노이즈를 유발하는 셀 문턱 전압(Vt) 변화를 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a recess gate structure, and more particularly, to a method of manufacturing a semiconductor device capable of preventing a cell threshold voltage (Vt) change that causes noise.

반도체 소자의 집적 밀도가 증가됨에 따라, 한정된 공간에 더 많은 수의 소자를 집적시키기 위하여 MOS 트랜지스터의 크기 즉, MOS 트랜지스터의 채널 길이가 감소되고 있다. 그런데, 이와 같이 MOS 트랜지스터의 채널 길이를 감소시키게 되면, 반도체 소자의 집적 밀도는 증가되나, 부수적으로 드레인 유기 장벽 저하(DIBL:drain induced barrier lowering), 핫 캐리어 이펙트(hot carrier effect) 및 펀치 스루(punch through) 등과 같이 반도체 소자를 비정상적으로 구동시키는 단채널 효과(short channel effect)가 유발된다. 현재에는 상기한 단채널 효과를 방지하기 위하여, 게이트 전극을 리세스(recess) 구조로 형성하는 방법이 제안되었다. As the integration density of semiconductor devices is increased, the size of the MOS transistors, that is, the channel length of the MOS transistors, has been reduced in order to integrate more devices in a limited space. However, when the channel length of the MOS transistor is reduced in this way, the integration density of the semiconductor device is increased, but concomitantly, drain induced barrier lowering (DIBL), hot carrier effect, and punch through ( Short channel effects that abnormally drive the semiconductor elements such as punch through are caused. At present, in order to prevent the short channel effect described above, a method of forming a gate electrode in a recess structure has been proposed.

리세스 게이트 전극은 도 1에 도시된 바와 같이, 소자 분리막(15)이 한정된 반도체 기판(10)내에 소정 깊이의 리세스(20)를 형성하고, 상기 리세스(20)내에 도전물을 매립하는 방식이다.As shown in FIG. 1, the recess gate electrode forms a recess 20 having a predetermined depth in the semiconductor substrate 10 in which the device isolation layer 15 is defined, and fills the conductive material in the recess 20. That's the way.

이때, 상기 리세스(20)내에 도전물을 매립하기 전에, 상기 리세스(20) 주변에 문턱 전압 조절층(25)을 형성하여야 하고, 연이어, 반도체 기판(10) 내부에 펀치스루 방지 이온층(30)을 형성하기 위하여, 반도체 기판(10) 전면에 펀치스루 방지 이온을 주입하여야 한다. At this time, before filling the conductive material in the recess 20, the threshold voltage adjusting layer 25 should be formed around the recess 20, and subsequently, a punch-through prevention ion layer is formed in the semiconductor substrate 10. In order to form 30, punch-through prevention ions must be implanted into the entire surface of the semiconductor substrate 10.

그런데, 상기 펀치수루 방지 이온이 기판(10) 전면에 주입됨에 따라, 다음과 같은 문제점이 발생될 수 있다. However, as the punch-through prevention ions are injected into the entire surface of the substrate 10, the following problems may occur.

첫째로, 상기 리세스(20)의 깊이에 의해 상기 펀치스루 이온층(30)에 투사 깊이(Rp) 차이가 발생될 수 있다. 투사 깊이 차이로 인해, 상기 리세스(20) 하부의 펀치스루 이온층(30)은 사실상 펀치 스루 방지의 역할을 하지 못하고, 반도체 기판의 농도만 증대시킨다. 그러므로 디램 소자의 경우, 리프레쉬 특성을 열화시킨다.First, a difference in the projection depth Rp may occur in the punch-through ion layer 30 due to the depth of the recess 20. Due to the difference in projection depth, the punchthrough ion layer 30 under the recess 20 does not actually serve as a punchthrough prevention, but only increases the concentration of the semiconductor substrate. Therefore, in the case of DRAM devices, the refresh characteristics are degraded.

둘째로, 상기 펀치스루 이온층(30)을 형성하기 위한 이온 주입 공정시, 상기 펀치 스루 이온이 문턱 전압 조절층(25)에도 일부 주입되어, 문턱 전압 조절층(25)의 농도를 변이시킨다. 이로 인해 문턱 전압을 상승시키게 되어, 소자 특성을 열화 시키는 문제점이 있다. Second, during the ion implantation process for forming the punch-through ion layer 30, the punch-through ions are partially injected into the threshold voltage adjusting layer 25, thereby changing the concentration of the threshold voltage adjusting layer 25. As a result, the threshold voltage is increased to deteriorate device characteristics.

본 발명이 이루고자 하는 기술적 과제는, 문턱 전압 및 기판 농도를 변형없이 선택적으로 펀치 스루 이온을 주입할 수 있는 리세스 게이트 구조를 갖는 반도체 소자의 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device having a recess gate structure capable of selectively injecting punch-through ions without modifying threshold voltage and substrate concentration.

상기 기술적 과제를 달성하기 위하여, 본 발명은, 액티브 영역이 한정된 반도체 기판의 선택된 영역에 리세스를 형성하는 단계를 포함한다. 이어서, 상기 리세스 내부에 선택적으로 문턱 전압 조절 이온을 주입하고, 상기 리세스를 포함하는 반도체 기판 상에 게이트 구조물을 증착한다. 그후에, 상기 리세스 부분을 포함하도록 게이트 한정용 포토레지스트 패턴을 형성한다. 다음, 상기 포토레지스트 패턴의 형태로 게이트 구조물을 식각하여, 리세스 게이트를 형성하고, 상기 포토레지스트 패턴을 잔류시킨 채로, 노출된 액티브 영역 전체에 펀치 스루 방지용 이온을 주입한다.In order to achieve the above technical problem, the present invention includes forming a recess in a selected region of a semiconductor substrate in which an active region is defined. Subsequently, a threshold voltage regulation ion is selectively implanted into the recess, and a gate structure is deposited on the semiconductor substrate including the recess. Thereafter, a gate defining photoresist pattern is formed to include the recess portion. Next, the gate structure is etched in the form of the photoresist pattern to form a recess gate, and the punch-through prevention ion is implanted into the exposed active region with the photoresist pattern remaining.

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2a 및 도 2b는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 각 공정별 단면도이다.2A and 2B are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to the present invention.

도 2a를 참조하면, 반도체 기판(100)의 소정 영역에 액티브 영역을 한정하기 위한 소자 분리막(105)을 형성한다. 다음, 게이트 예정 영역이 노출되도록 마스크 패턴(110)을 형성한다음, 상기 노출된 반도체 기판(100)을 소정 깊이만큼 식각하여 리세스(115)를 형성한다. 또는 상기 리세스(115)는 마스크 패턴(110)에 의해 국부 산화막(도시되지 않음)을 형성한 다음, 국부 산화막을 제거함으로써 얻어질 수 있다. 그후, 노출된 리세스(115) 내부에 문턱 전압 조절 이온을 주입하여 문턱 전압 조절층(120)을 형성한다.Referring to FIG. 2A, an isolation layer 105 for defining an active region is formed in a predetermined region of the semiconductor substrate 100. Next, the mask pattern 110 is formed to expose the gate predetermined region, and then the recess 115 is formed by etching the exposed semiconductor substrate 100 by a predetermined depth. Alternatively, the recess 115 may be obtained by forming a local oxide film (not shown) by the mask pattern 110 and then removing the local oxide film. Thereafter, the threshold voltage regulation layer 120 is formed by implanting threshold voltage regulation ions into the exposed recess 115.

그 다음, 도 2b에 도시된 바와 같이, 상기 마스크 패턴(110)을 공지의 방식으로 제거한다. 그 후, 상기 리세스(115)를 포함하는 반도체 기판(100) 표면에 게이트 산화막(125)을 형성한다음, 상기 게이트 산화막(125) 상부에 게이트 전극용 도전층을 형성한다. 상기 게이트 산화막(125) 및 게이트 전극용 도전층은 게이트 구조물을 구성한다. 상기 게이트 전극용 도전층은 예를 들어 상기 리세스(115)가 충분히 매립될 수 있을 정도의 두께로 형성된다. 그후, 상기 게이트 전극용 도전층 상부에 게이트 한정용 포토레지스트 패턴(135)을 형성한다. 상기 포토레지스트 패턴(135)은 상기 리세스(115)를 포함하도록 형성된다. 다음, 상기 포토레지스트 패턴(135)의 형태로 상기 도전층을 식각하여, 게이트 전극(130)을 형성한다. 상기 도전층의 식각은, 도전층 위에 하드마스크를 증착한 후에 수행될 수도 있다.Next, as shown in FIG. 2B, the mask pattern 110 is removed in a known manner. Thereafter, the gate oxide film 125 is formed on the surface of the semiconductor substrate 100 including the recess 115, and then a conductive layer for the gate electrode is formed on the gate oxide film 125. The gate oxide layer 125 and the conductive layer for the gate electrode constitute a gate structure. The conductive layer for the gate electrode is, for example, formed to a thickness such that the recess 115 can be sufficiently buried. Thereafter, a gate defining photoresist pattern 135 is formed on the gate electrode conductive layer. The photoresist pattern 135 is formed to include the recess 115. Next, the conductive layer is etched in the form of the photoresist pattern 135 to form a gate electrode 130. The etching of the conductive layer may be performed after depositing a hard mask on the conductive layer.

이어서, 노출된 반도체 기판(100)의 액티브 영역에 펀치스루 방지용 이온을 주입하여, 펀치스루 방지용 이온층(140)을 형성한다. 상기 펀치스루 방지용 이온 주입시, 리세스(115)가 게이트 전극(130) 및 포토레지스트 패턴(135)에 의해 덮혀 있으므로, 상기 펀치스루 방지용 이온이 상기 문턱 전압 조절층(120)에 영향을 미치지 않으며, 상기 리세스(115) 하부에 펀치스루 이온이 주입되지 않으므로, 불필 요한 기판 농도 상승을 방지할 수 있다. Next, punch-through prevention ions are implanted into the exposed active region of the semiconductor substrate 100 to form the punch-through prevention ion layer 140. When the punchthrough prevention ion is implanted, the recess 115 is covered by the gate electrode 130 and the photoresist pattern 135, so that the punchthrough prevention ion does not affect the threshold voltage adjusting layer 120. Since punchthrough ions are not implanted into the recess 115, an unnecessary increase in substrate concentration can be prevented.

그후, 도면에는 도시되지 않았지만, 상기 포토레지스트 패턴(135)을 공지의 방식으로 제거한 다음, 후속의 접합 영역 형성 공정을 진행한다. Thereafter, although not shown in the figure, the photoresist pattern 135 is removed in a known manner, and then a subsequent bonding region forming process is performed.

이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 리세스 게이트 전극을 형성한 다음, 게이트 마스크 패턴(포토레지스트 패턴)이 형성되어 있는 상태에서 펀치스루 방지용 이온을 주입한다.As described above in detail, according to the present invention, after the recess gate electrode is formed, punch-through prevention ions are implanted in the state where the gate mask pattern (photoresist pattern) is formed.

이에 의해, 리세스 하단의 불필요한 펀치 쓰루 이온층의 형성을 방지할 수 있고, 문턱 전압 조절층의 농도 변화를 방지할 수 있다. 이에 따라, 반도체 소자의 문턱 전압 변이 및 이에 의한 소자 특성 변이를 방지할 수 있고, 리플레쉬 특성을 확보할 수 있다. As a result, unnecessary formation of the punch through ion layer at the lower end of the recess can be prevented, and a change in concentration of the threshold voltage regulating layer can be prevented. As a result, it is possible to prevent the threshold voltage variation of the semiconductor device and the variation of the device characteristics thereby, and to secure the refresh characteristics.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러가지 변형이 가능하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (2)

액티브 영역이 한정된 반도체 기판의 선택된 영역에 리세스를 형성하는 단계;Forming a recess in a selected region of the semiconductor substrate in which the active region is defined; 상기 리세스 내부에 선택적으로 문턱 전압 조절 이온을 주입하는 단계;Selectively implanting threshold voltage regulating ions into the recess; 상기 리세스를 포함하는 반도체 기판 상에 게이트 구조물을 증착하는 단계;Depositing a gate structure on the semiconductor substrate including the recess; 상기 리세스 부분을 포함하도록 게이트 한정용 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern for defining a gate to include the recess portion; 상기 포토레지스트 패턴의 형태로 게이트 구조물을 식각하여, 리세스 게이트를 형성하는 단계; 및Etching a gate structure in the form of the photoresist pattern to form a recess gate; And 상기 포토레지스트 패턴을 잔류시킨 채로, 노출된 액티브 영역 전체에 펀치 스루 방지용 이온을 주입하는 단계를 포함하는 반도체 소자의 제조방법.Implanting punch-through prevention ions into the entire exposed active region while the photoresist pattern remains. 제1항에 있어서, 상기 리세스를 형성하는 단계 및 상기 리세스내에 문턱 전압 조절 이온을 주입하는 단계는,The method of claim 1, wherein forming the recess and implanting threshold voltage regulating ions into the recess comprises: 상기 반도체 기판의 선택된 영역이 노출되도록 마스크 패턴을 형성하는 단계;Forming a mask pattern to expose a selected region of the semiconductor substrate; 상기 마스크 패턴에 의해 노출된 반도체 기판을 소정 깊이만큼 식각하여, 리세스를 형성하는 단계;Etching the semiconductor substrate exposed by the mask pattern by a predetermined depth to form a recess; 상기 리세스 내부에 문턱 전압 조절 이온을 주입하는 단계; 및Implanting threshold voltage regulating ions into the recess; And 상기 마스크 패턴을 제거하는 단계를 포함하는 반도체 소자의 제조방법.Removing the mask pattern.
KR1020060059903A 2006-06-29 2006-06-29 Method of manufacturing a semiconductor device having a structure of a recess gate KR100780770B1 (en)

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Publication number Priority date Publication date Assignee Title
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