KR100778986B1 - Insulated gate type semiconductor device and manufacturing method thereof - Google Patents

Abstract

Conventionally, one metal electrode layer was contacted to an element region, and a bonding wire was fixed on the metal electrode layer. In order to reduce the on resistance of the apparatus, it is preferable to increase the thickness of the metal electrode layer, but there is a limit in the accuracy of patterning. In addition, when Au thin wires are used as the bonding wires, Au / Al eutectic layers are formed with time, and there is a problem of giving pressure to the interlayer insulating film in the element region. The metal electrode layer is made into two layers. The first electrode layer is patterned at a fine separation distance matched with the element region as in the prior art. On the other hand, the second electrode layer may be in contact with the first electrode layer, and there is no problem even if the separation distance increases. That is, a 2nd electrode layer can be made into a desired film thickness. In addition, by arranging the nitride film on the first electrode layer below the wire bond region, it is possible to prevent the stress from being transferred to the element region even when volume expansion by the Au / Al process layer occurs.

Electrode layer, wire bond region, nitride film, bonding wire, insulating film

Description

INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

1 is a cross-sectional view of a semiconductor device of the present invention.

2 is a plan view illustrating a semiconductor device of the present invention.

3 is a plan view illustrating a semiconductor device of the present invention.

4 is a cross-sectional view illustrating a semiconductor device of the present invention.

5 is a cross-sectional view showing the manufacturing method of the semiconductor device of the present invention.

6 is a cross-sectional view showing the manufacturing method of the semiconductor device of the present invention.

7 is a cross-sectional view showing the manufacturing method of the semiconductor device of the invention.

8 is a cross-sectional view showing the manufacturing method of the semiconductor device of the invention.

9 is a cross-sectional view (A) and a plan view (B) illustrating a conventional semiconductor device.

<Description of the symbols for the main parts of the drawings>

1: n + type silicon semiconductor substrate

2: n-type epitaxial layer (drain region)

3: p + type region

4: channel layer

8: trench

11: gate oxide film

13: gate electrode

14: body area

15: source area

16: interlayer insulation film

17: first electrode layer

17s: first source electrode

17g: first gate pad electrode

18: second electrode layer

18s: second source electrode

18g: second gate pad electrode

20: device region

21: first nitride film

22: second nitride film

25: MOSFET

26: wire bond area

27: bonding wire

28: protective film

31: n + type silicon semiconductor substrate

32: drain region

33: p + type region

34: channel layer

37: trench

41: gate oxide film

43: gate electrode

44: body area

45: source region

46: interlayer insulation film

50: shield

51: device region

52: MOSFET

60: bonding wire

[Patent Document 1] Japanese Unexamined Patent Publication No. 2002-368218 (Fig. 5)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device and a method for manufacturing the same, and more particularly, to an insulated gate semiconductor device and a method for manufacturing the same, which reduce the on-resistance of the device and improve defects in wire bonding.

9 shows a conventional semiconductor device. FIG. 9A is a sectional view, and FIG. 9B is a plan view. FIG. 9A is a cross-sectional view taken along the line b-b of FIG. 9B.

As shown in FIG. 9A, a MOSFET 52 having a trench structure is formed in the element region 51, for example. That is, the drain region 32 formed of the n-type epitaxial layer is formed on the n + type silicon semiconductor substrate 31, and the p-type channel layer 34 is formed on the surface thereof. A trench 37 penetrating through the channel layer 34 and reaching the drain region 32 is formed, the inner wall of the trench 37 is coated with a gate oxide film 41, and the polysilicon filled in the trench 37 is formed. A gate electrode 43 is formed. An n + type source region 45 is formed on the surface of the channel layer 34 adjacent to the trench 37, and a p + type body region is formed on the surface of the channel layer 34 between the source regions 45 of two adjacent cells. Form 44. The gate electrode 43 is covered with an interlayer insulating film 46. On the surface, a metal electrode layer 47 is formed which is connected to the element region 51.

As shown in FIG. 9B, the metal electrode layer 47 is patterned into a predetermined shape to form a source electrode 47s covering the entire surface of the element region 51, a gate pad electrode 47g, and the like. The source electrode 47s contacts the source region 45 and the body region 44. The gate pad electrode 47g is connected to the gate electrode 43 of the element region 51 via the protection diode D.

On the metal electrode layer 47, a nitride film 50 serving as a protective film is formed, and the nitride film 50 is opened to fix the bonding wire 60 (see Patent Document 1, for example).

For example, four bonding wires 60 are fixed on the source electrode 47s covering the element region 51 and one on the gate pad electrode 47g.

In insulated gate semiconductor devices such as MOSFETs, the reduction of the on resistance is an important factor for improving the characteristics. Various methods are employed to reduce the on resistance, but for example, it is relatively low cost and easy to reduce the resistance value of the metal electrode layer 47 (source electrode 47s) that contacts the entire surface of the element region. Do. Specifically, as the metal layer having a low resistance value, a metal electrode layer 47 made of an aluminum alloy is generally employed.

By the way, in the case of the metal electrode layer 47 of an aluminum alloy, when a gold (Au) thin wire is employ | adopted as a bonding wire, there exists a problem that a defect generate | occur | produces, for example after a certain period of time passes. That is, when Au balls are directly fixed to the metal electrode layer 47, Au and Al diffuse to each other at the interface with time, and an Au / Al process layer is formed. The Au / Al process causes volume expansion, and the stress at that time gives the interlayer insulating film 46 a pressure.

If pressure is applied to the interlayer insulating film 46, crack C occurs (see Fig. 9A), which causes a problem of leakage between the gate and the source.

Moreover, when aiming at the further reduction of an on resistance, it is also considered to employ | adopt a metal layer with a lower resistance value instead of an aluminum alloy layer, for example. If it is not an aluminum alloy layer, the generation of the crack C by the Al / Au process mentioned above can also be avoided. However, the aluminum alloy layer can use the existing sputtering apparatus, and cost is also inexpensive. Moreover, patterning is also easy and it is suitable as the metal electrode layer 47. FIG. Therefore, an aluminum alloy is employ | adopted as the metal electrode layer 47, and the thickness of the metal electrode layer 47 is made thick, and a resistance value can be reduced more.

However, there is a limit to the thickening of the aluminum alloy film. That is, when the aluminum alloy is patterned by the low cost wet etching, side etching that is equivalent to the etching amount in the depth direction occurs, so that the thicker the film thickness is, the adjacent pattern (for example, the gate pad electrode 47g) is formed. And a separation distance from the source electrode 47s). Therefore, there is a problem that the pattern arrangement with the element region 51 and the gate pad electrode 47g becomes wider than necessary and the chip size is increased.

On the other hand, if it is dry etching, side etching does not generate | occur | produce, but an etching apparatus is expensive. Moreover, the film thickness which can be etched has a limit from the relationship of the etching selectivity of the resist film used as an etching mask and an aluminum alloy. That is, the dry etchant of the aluminum alloy has a low selectivity with respect to the resist film, so that the resist film to be left during the etching of the thick aluminum alloy also undergoes etching, so that a mask pattern cannot be formed accurately. Although the resist film may be thickly formed, since the resolution deteriorates in that case, it is unsuitable for a fine pattern.

This invention is made | formed in view of such a subject, Firstly, the insulated-gate semiconductor element area | region formed on the semiconductor substrate, the 1st electrode layer which coat | covers at least the said element area | region, and connects with this element area | region, This is solved by providing an insulating film covering a portion of the first electrode layer, a second electrode layer covering the first electrode layer and the insulating film, and contacting the first electrode layer exposed from the insulating film.

Secondly, an insulated gate semiconductor element region formed on a semiconductor substrate, a first electrode layer covering at least the element region and connected to the element region, an insulating film covering a portion of the first electrode layer, and This is solved by providing a first electrode layer and a second electrode layer covering the upper surface of the insulating film and contacting the first electrode layer exposed from the insulating film, and a bonding wire fixed to the second electrode layer above the insulating film.

Thirdly, forming an insulated gate semiconductor device region on the semiconductor substrate; forming a first electrode layer covering at least the device region and connecting to the device region; and a part of the first electrode layer. It is solved by providing the process of forming the insulating film to coat | cover, and the process of forming the 2nd electrode layer which coat | covers the said 1st electrode layer and the said insulating film, and contacts the said 1st electrode layer exposed from this insulating film.

<Example>

An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 8. As an example, the case where the n-channel MOSFET is arranged in the element region is described.

1 shows a cross-sectional view of the semiconductor device of this embodiment.

In the device region 20, a MOSFET 25 is formed. In this embodiment, the formation region of the channel layer in which the MOSFET 25 is arranged is referred to as the element region 20.

The first electrode layer 17 is formed on the device region 20. The first electrode layer 17 is an aluminum alloy layer and is connected to the element region 20. As shown in the drawing, the first electrode layer 17 is separated into a plurality of portions by the first opening OP1, whereby the first source electrode 17s and the first gate pad electrode 17g are formed.

The first source electrode 17s is formed covering the entire surface of the element region 20 and connected to the source region 15 of the MOSFET 25. The first gate pad electrode 17g is formed outside the element region 20, for example, on the substrate surface of the chip corner portion. The first gate pad electrode 17g is connected to the gate electrode 13 of the MOSFET 25 via the protection diode D. The film thickness d1 of the first electrode layer 17 (the first source electrode 17s and the first gate pad electrode 17g) is approximately 3 μm.

The first insulating layer 21 is disposed on the first electrode layer 17. The first insulating film is a nitride film (hereinafter referred to as first nitride film 21) and has a film thickness of 0.5 µm to 3 µm (for example, 0.7 µm). Although mentioned later, the 1st nitride film 21 is arrange | positioned below the area | region (wire bond area | region 26) to which the bonding wire 27 is fixed so that a part of 1st electrode layer 17 may be exposed.

The second electrode layer 18 covers the first electrode layer 17 and the first nitride film 21 and contacts the first electrode layer 17 exposed from the first nitride film 21. The second electrode layer 18 is also made of, for example, an aluminum alloy, and is separated in plurality by the second opening OP2 having a different opening width from the first opening OP1. As a result, the second source electrode 18s that contacts the first source electrode 17s and the second gate pad electrode 18g that contacts the first gate pad electrode 17g are formed. These film thicknesses d2 are about 3 micrometers, for example. In addition, this film thickness d2 is an example, and it selects suitably according to the resistance characteristic of an apparatus, such as a required ON resistance.

The MOSFET 25 forms an n-type semiconductor layer (epitaxial layer) 2 on the n + silicon semiconductor substrate 1 to serve as a drain region, and the p-type channel layer 4 formed on the surface thereof. Is formed. In the outer periphery of the channel layer 4, a deeper and higher concentration p + type region 3 is formed than the channel layer 4, thereby reducing the curvature of the depletion layer at the end of the channel layer 4 to suppress electric field concentration.

The trench 8 penetrates through the channel layer 4 and reaches the n-type semiconductor layer 2. Generally, patterning is carried out in a lattice shape or stripe shape on a semiconductor substrate. A gate oxide film 11 is formed on the inner wall of the trench 8, and polysilicon is embedded to form the gate electrode 13.

The gate oxide film 11 is formed on the inner wall of the trench 8 at least in contact with the channel layer 4 with a thickness of several hundred micrometers in accordance with the driving voltage. Since the gate oxide film 11 is an insulating film, the gate oxide film 11 is sandwiched between the gate electrode 13 formed in the trench 8 and the semiconductor substrate to have a MOS structure.

The gate electrode 13 is a conductive material embedded in the trench 8. The conductive material is, for example, polysilicon, and n-type impurities are introduced into the polysilicon in order to reduce the resistance. The gate electrode 13 is connected to the protection diode D and connected to the gate pad electrode 17g by a connection portion (not shown here) formed by patterning of polysilicon.

The source region 15 is a diffusion region in which n + -type impurities are injected into the surface of the channel layer 4 adjacent to the trench 8. In addition, a body region 14, which is a diffusion region of p + type impurity, is formed on the surface of the channel layer 4 between the adjacent source regions 15 and the surface of the channel layer 4 at the end of the element region 20. Stabilize the potential.

On the gate electrode 13, an interlayer insulating film 16 is formed. The first source electrode 17s contacts the source region 15 and the body region 14 through the contact holes between the interlayer insulating layers 16.

The first gate pad electrode 17g is disposed on the protection diode D that protects the weak gate oxide film 11 from overvoltage and the like, and is connected to one end of the protection diode D. One end of the protection diode D is connected to the gate electrode 13, and the other end of the protection diode D is connected to the first source electrode 17s.

FIG. 2 is a chip plan view of the semiconductor device of FIG. 1. FIG. 2A is a diagram showing a pattern of the first electrode layer 17 and the first nitride film 21, and FIG. 2B is a diagram showing a pattern of the second electrode layer 18. In FIG. 2, the device region 20 is indicated by a dashed dashed line. In addition, FIG. 1 is corresponded to the a-a cross section in FIG.2 (B).

As shown in FIG. 2A, the first nitride film 21 is disposed on the first electrode layer 17 in an island shape, for example. That is, the first electrode layer 17 is exposed around the first nitride film 21.

In FIG. 2B, the broken line indicates the pattern of the first nitride film 21 below the second electrode layer 18, and the circle mark indicates the wire bond region 26 on the surface of the second electrode layer 18.

For example, in the case of FIGS. 2A and 2B, the first source electrode 17s and the second source electrode 18s are formed to cover at least the element region 20 and form a plurality of wires. The bond area 26 is secured. On the other hand, it is sufficient that the first gate pad electrode 17g and the second gate pad electrode 18g can secure one wire bond region 26.

In the present embodiment, the first nitride film 21 is disposed on the first metal layer 17 below the wire bond region 26 so as to overlap at least the wire bond region 26. Thereby, the defect at the time of wire bonding can be avoided. That is, when Au wire is wire-bonded with respect to an aluminum alloy layer, an Au / Al process layer is formed and volume expansion arises and stresses the 1st nitride film 21. Although the first nitride film 21 is subjected to some damage such as crystal deformation and cracks, it is possible to prevent the stress from being transferred to the element region 20. Since the first nitride film 21 is not formed to electrically insulate the device region 20, the device does not affect the device even when the film quality is slightly degraded, such as crystal deformation or cracks.

As a result, the stress is not exerted on the interlayer insulating film 16 of the element region 20, and the short caused by the crack C of the interlayer insulating film 16 can be prevented. For example, when the 1st electrode layer 17 is the film thickness equivalent to the conventional thing, in addition to this, by arrange | positioning the 2nd electrode layer 18, on-resistance can be reduced.

In addition, the thicker the film thickness of the second electrode layer 18 is advantageous for reducing the on resistance, and the impact of the wire bond can be alleviated by the thickness of the second electrode layer 18.

The Au / Al eutectic layer is formed around the wire bond region. Therefore, if the 1st nitride film 21 is arrange | positioned in the area | region just under the wire bond between the 2nd electrode layer 18 and the 1st electrode layer 17, stress can be alleviated.

Referring back to FIG. 1, the first opening OP1 and the second opening OP2 will be described.

Although the second metal layer 18 is formed in a pattern almost similar to that of the first metal layer 17, the opening width w2 of the second opening OP2 separating the second source electrode 18s and the second gate pad electrode 18g is provided. Is different in size from the opening width w1 of the first opening OP1 separating the first source electrode 17s and the first gate pad electrode 17g.

Specifically, the opening width w1 of the first opening OP1 is 3 μm which is equivalent to the film thickness of the first electrode layer 17. The opening width w2 of the second opening OP2 is larger than the opening width w1 of the first opening OP1, for example, 30 μm.

In order to reduce the on resistance of the MOSFET, the thickness of the first electrode layer 17 and the second electrode layer 18 should be thicker. However, when patterning them by wet etching, the film thickness of the first electrode layer 17 is limited by the amount of side etching at the time of patterning (at the time of forming the first opening OP1). That is, since side etching of the amount equivalent to the depth (thickness) direction occurs, when the film thickness of the first electrode layer 17 is made too thick, the opening width w1 of the first opening OP1 becomes large. This means that the pattern arrangement of the first source electrode 17s (element region 20) and the first gate pad electrode 17g becomes wider than necessary, which hinders the miniaturization of a chip or an increase in the number of cells. It becomes

Accordingly, the first electrode layer 17 has a film thickness (3 μm) of a limit capable of forming a fine first opening OP1, and the opening width w1 of the first opening OP1 is the film thickness of the first electrode layer 17. Patterning is as small as possible in consideration of chip size (or number of cells).

On the other hand, the second source electrode 18s and the second gate pad electrode 18g may be insulated from each other, and the connection with the element region 20 is ensured by the first metal layer 17, respectively. That is, the second source electrode 18s and the second gate pad electrode 18g may contact the first source electrode 17s and the first gate pad electrode 17g, respectively, and may secure a fixing region of the bonding wire. It is enough, and a fine pattern is not required for the second opening OP2.

Therefore, there is no problem even if the opening width w2 is sufficiently wide as compared with the opening width w1, and specifically, the opening width w2 which becomes the separation distance between the second source electrode 18s and the second gate pad electrode 18g is, for example. It is about 30 micrometers.

The second opening OP2 is formed to overlap with the first opening OP1. Here, the 1st opening OP1 and the 1st electrode layer 17 surrounding it are covered with the nitride film (henceforth 2nd nitride film 22) used as a 2nd insulating film. The second nitride film 22 serves as an etching stopper of the second electrode layer 18 when the second opening OP2 is formed. Therefore, by covering the first opening OP1 with the second nitride film 22, the minute opening width w1 of the first opening OP1 (the separation distance between the first source electrode 17s and the first gate pad electrode 17g) is maintained. The wide second opening OP2 can be formed.

As described above, the second electrode layer 18 of the present embodiment is not limited by the opening width w2 of the second opening OP2, and the film thickness can be set according to the desired on resistance. In addition, since the on-resistance can be reduced only by controlling the film thickness of the second metal layer 18, an existing apparatus can be used, which results in low cost and easy reduction of the on-resistance.

The thickness of the second electrode layer 17 is as described above that the thicker side is advantageous to the on-resistance, and the thicker side also increases the uniformity of the operation of the element region 20 and can also cushion the impact during wire bonding. Done.

FIG. 3 is a plan view corresponding to FIG. 2A showing another pattern of the first nitride film 21. In addition, the wire bond area | region 26 is shown with the dashed circle display.

Although the case where the 1st nitride film 21 was island-patterned corresponding to each wire bond area | region 26 was shown in FIG. 2, you may form continuously in the some wire bond area | region 26. FIG. For example, FIG. 3A illustrates a case where the first nitride film 21 is formed such that the wire bond regions 26 adjacent to each other on the first source electrode 17s side are continuous.

3B is a case where the first nitride film 21 is patterned such that the wire bond region 26 is continuous on the first source electrode 17s side. In addition, when the first gate pad electrode 17g is sufficiently large with respect to the wire bond region 26, the first nitride film 21 on the first gate pad electrode 17g may be divided into a plurality of parts.

4, the protective film 28 may be further formed on the surface of the second metal layer 18. The protective film 28 is, for example, a nitride film and covers the entire chip surface, and the thickness thereof is about 7000 GPa. The bonding wire 27 is fixed to the wire bond region 26 of the second metal layer 18 through an opening formed in the protective film 28.

Next, the manufacturing method of the semiconductor device of this invention is shown to FIG. 5 thru | or FIG. 8 as an example of an n-channel MOSFET.

1st process (FIG. 5): The process of forming the insulated-gate semiconductor element area | region on a semiconductor substrate.

An n-type semiconductor layer (epitaxial layer) 12 is laminated on the n + type silicon semiconductor substrate 1 to form a drain region. A high concentration of boron is implanted and diffused into the end of the formation region of the channel layer to form the p + type region 3. After the thermal oxide film (not shown) is formed on the surface, the thermal oxide film in the formation region of the channel layer is etched. For example, boron is injected into the entire surface at a dose of 1.0 × 10 ¹³ cm ⁻² , and then diffused to form a p-type channel layer 4.

A CVD oxide film (not shown) of NSG (non-doped Silicate Glass) is formed on the entire surface by the CVD method. Then, the mask by a resist film is hanged except the opening part of a trench. The CVD oxide film is dry etched and partially removed to expose the channel layer 4.

Then, the trench 8 which dry-etches the silicon semiconductor substrate of the trench opening by CF type | system | group and HBr type gas by using a CVD oxide film as a mask, penetrates the channel layer 4 to the n-type semiconductor layer 2, ) Is formed (FIG. 5A).

A dummy oxidation is performed to form an oxide film (not shown) on the inner wall of the trench 8 and the surface of the channel layer 4 to remove etching damage during dry etching, and then the oxide film and the CVD oxide film are removed by etching.

Further, the entire surface is oxidized to form a gate oxide film 11 on the inner wall of the trench 8, for example, having a thickness of about 300 kPa to 700 kPa depending on the driving voltage. A polysilicon layer is deposited on the whole surface, and the mask of a desired pattern is formed and dry-etched. The polysilicon layer may be a layer in which polysilicon containing impurities is deposited, or a layer in which impurities are introduced after depositing undoped polysilicon.

As a result, the gate electrode 13 embedded in the trench 8 is formed. In addition, a polysilicon layer 13d serving as a protection diode and a connection portion (not shown) of the protection diode and the gate electrode 13 are also patterned (FIG. 5B).

Thereafter, in order to stabilize the potential of the substrate, a mask is formed by a resist film (not shown) to which the formation region of the body region is exposed, and optionally, boron is ionized, for example, in a dose amount of 2.0 × 10 ¹⁵ cm ^−2. Inject. Arsenic is implanted into a region of the source region with a new resist film (not shown), for example, in a dose of about 5.0 × 10 ¹⁵ cm ⁻² .

An insulating film 16 'in which an NSG or PSG (not shown) and a BPSG (Boron phosphorus Silicate Glass) layer or the like are deposited on the entire surface by a CVD method is formed. The body region 14 is formed on the surface of the channel layer 4 adjacent to the n + type source region 15 and the source region 15 by heat processing at this time.

The resist film masks at least the gate electrode 13 of the MOSFET, forms the contact hole CH in the insulating film 16 ', and forms the interlayer insulating film 16.

As a result, the element region 20 in which the MOSFET 25 is arranged is formed (FIG. 5C).

In addition, the order of implantation of impurities in the source region 15 and the body region 14 may be reversed.

2nd process (FIG. 6): The process of forming the 1st electrode layer which coat | covers at least an element region and connects with an element region.

For example, an aluminum alloy is sputtered on the whole surface, and the 1st electrode layer 17 is formed in the whole surface. Thereafter, a first opening OP1 having an opening width w1 is formed by using a mask having a desired pattern to separate the first electrode layer 17 into a plurality of regions. As a result, the first source electrode 17s and the first gate pad electrode 17g which contact the source region 15 and the body region 14 of the MOSFET 25 are formed. The film thickness d1 of the first metal layer 17 is about 3 μm. Further, the opening width w1, which is the distance between the first source electrode 17s and the first gate pad electrode 17g, is also about 3 µm, and the film thickness of the first electrode layer 17 for reducing the on-resistance and the chip It is made as small as possible in view of the size (number of cells), process limitations, and the like.

In addition, although illustration is abbreviate | omitted, the barrier metal layer etc. may be contained in the 1st electrode layer 17 in some cases. The barrier metal layer is a titanium-based metal layer (for example, Ti, TiN, TiON, TiW, etc.) formed before the sputter of the aluminum alloy, and suppresses the growth of Si nodules in the contact hole and the surface of the aluminum alloy layer and the semiconductor substrate. To prevent mutual diffusion.

3rd process (FIG. 7): The process of forming the insulating film which covers a part of 1st electrode layer.

For example, the first nitride film 21 having a film thickness of about 7000 GPa is deposited on the entire surface and patterned into a desired shape. The first nitride film 21 is formed larger than the wire bond region at least below the wire bond region and covers a part of the first electrode layer 17 (see FIGS. 2 and 3).

At the same time, the second nitride film 22 covering the first opening OP1 and the first electrode layer 17 around it is formed. By forming the second nitride film 22, the second opening OP2 of the second electrode layer 18 formed in a later step can be formed in a desired opening width while maintaining the opening width w1 of the first opening OP1 in a fine pattern. have.

In addition, the 1st nitride film 21 and the 2nd nitride film 22 are the same material as the protective film generally employ | adopted for protection of a chip | tip surface, and the film thickness should just be about the same as a protective film. That is, by using the existing apparatus and manufacturing process for forming a protective film, it can respond only by changing the mask of the patterning of the 1st nitride film 21 and the 2nd nitride film 22. FIG.

4th process (FIG. 8): The process of covering the 1st electrode layer and the insulating film, and forming the 2nd electrode layer which contacts the 1st electrode layer exposed from the insulating film.

On the whole surface, the aluminum alloy is sputtered and the 2nd electrode layer 18 which contacts the 1st electrode layer 17 exposed from the 1st nitride film 21 is formed. Thereafter, a mask having a desired pattern is formed in the second electrode layer 18 to be etched to form a second opening OP2 having an opening width w2, thereby separating the second electrode layer 18 into a plurality of regions. As a result, the second source electrode 18s in contact with the first source electrode 17s and the second gate pad electrode 18g in contact with the first gate pad electrode 17g are formed.

Here, the film thickness d2 of the 2nd electrode layer 18 is about 3 micrometers, for example. The opening width w2, which is the separation distance between the second source electrode 18s and the second gate pad electrode 18g, is different from the opening width w1 of the first opening OP1. Specifically, the opening width w2 is sufficiently larger than the opening width w1 and is about 30 μm.

The first electrode layer 17 and the second electrode layer 18 are the same aluminum alloy layer. In the present embodiment, since the second nitride film 22 serving as the etching stopper of the second electrode layer 18 is arranged, the second having the wide opening width w2 while maintaining the fine opening width w1 of the first opening OP1. The opening OP2 can be formed. In addition, since it is not necessary to consider the miniaturization of the opening width w2, the thickness of the second electrode layer 18 can be made the desired thickness according to the on resistance. In addition, the film thickness d2 of the 2nd electrode layer 18 is an example, and is selected suitably according to characteristics, such as an on resistance.

After that, the bonding wire (Au thin wire) is fixed to the predetermined wire bond region 26 of the second electrode layer 18 to obtain the final structure shown in FIG. 1. The first nitride film 21 is disposed below the wire bond region 26.

Au and Al diffuse together with time, and volume expansion by an Au / Al process layer may occur in some cases. However, in this embodiment, the stress due to volume expansion can be alleviated by the first nitride film 21. Therefore, the stress of volume expansion is not applied to the interlayer insulating film 16, so that crack C can be prevented.

In addition, the protective film 28 may be formed on the second electrode layer 18. In this case, a nitride film or the like is deposited on the entire surface of the second electrode layer 18 to form a protective film 28. And the wire bond area | region 26 of the protective film 28 is opened, and the bonding wire 27 is fixed.

As described above, in the embodiment of the present invention, the case where the n-channel MOSFET is disposed in the element region has been described as an example, but the present invention is not limited thereto. For example, in the device region, an insulated gate type semiconductor element such as an MOS transistor in which the conductivity type is reversed and an IGBT in which a p type semiconductor substrate is formed below the n + type semiconductor substrate may be disposed.

According to the present invention, first, the crack of the interlayer insulating film due to the formation of the Au / Al process layer can be prevented by the insulating film disposed between the first electrode layer and the second electrode layer in the bonding wire fixing region. In other words, even when volume expansion occurs due to the formation of the Au / Al process layer, the insulating film disposed between the first electrode layer and the second electrode layer receives the stress due to the volume expansion. Therefore, the pressure to the interlayer insulating film can be avoided and the crack of the interlayer insulating film can be prevented.

Second, the total film thickness of the metal electrode layer can be formed thick, so that the low temperature resistance of the semiconductor device can be realized. The metal electrode layer consists of a 1st electrode layer and a 2nd electrode layer, and a 1st electrode layer is formed in the film thickness which considered the side etching amount at the time of patterning (at the time of forming a 1st opening). Then, a second electrode layer is formed on the first electrode layer to a desired film thickness. The opening width of the first opening is a separation distance between the source electrode and the gate pad electrode on the element region, and is as close as possible to patterning. That is, the first electrode layer has a film thickness of a limit capable of forming a fine first opening. It is sufficient that the second electrode layer is in contact with the first electrode layer, and miniaturization is not required as a pattern of the second electrode layer. Therefore, since the resolution of the resist film is not required as much, it can be formed at a desired film thickness in accordance with the on resistance value.

Third, since the total thickness of the total electrode layer on the element region can be increased, the impact of the wire bonds on the element region can be alleviated.

Claims (16)

An insulated gate semiconductor device region formed on the semiconductor substrate, A first electrode layer covering at least the element region and connected to the element region; An insulating film covering a portion of the first electrode layer; A second electrode layer covering the first electrode layer and the insulating film and contacting the first electrode layer exposed from the insulating film; Bonding wires adhered to the second electrode layer Equipped with And the insulating film is formed on at least the entire lower side of the fixing region of the bonding wire. The method of claim 1, And the first and second electrode layers are metal layers mainly composed of aluminum. The method of claim 1, The bonding wire is an insulated gate semiconductor device, characterized in that gold is the main material. The method of claim 1, The insulating gate type semiconductor device, characterized in that a plurality of insulating films are formed in an island shape. The method of claim 1, The insulating film is an insulating gate type semiconductor device, characterized in that the nitride film. The method of claim 1, The insulating film is an insulating gate type semiconductor device, characterized in that the film thickness of 0.5㎛ 3㎛. The method of claim 1, An insulating gate type semiconductor device, wherein a protective film is formed on the second electrode layer, and the bonding wire is fixed to the second electrode layer through an opening formed in the protective film. The method of claim 1, The first electrode layer has a first opening, the second electrode layer has a second opening, and the opening width of the first opening and the opening width of the second opening have different sizes. Device. The method of claim 8, And an insulating film covering said first opening and said first electrode layer around said first opening. Forming an insulated gate semiconductor device region on the semiconductor substrate; Covering at least the element region and forming a first electrode layer connected to the element region; Forming an insulating film covering a portion of the first electrode layer; Forming a second electrode layer covering the first electrode layer and the insulating film and contacting the first electrode layer exposed from the insulating film; A method of manufacturing an insulated gate semiconductor device, comprising: The method of claim 10, A bonding wire is fixed to the second electrode layer above the insulating film. The method of claim 10, And separating the first electrode layer into a plurality of regions by a first opening, and separating the second electrode layer into a plurality of regions by a second opening having a different opening width from the first opening. The manufacturing method of the insulated-gate semiconductor device. The method of claim 12, And forming another insulating film covering the first opening and the first electrode layer around the first opening. The method of claim 13, A method for manufacturing an insulated gate semiconductor device, wherein the insulating film and the other insulating film are formed by the same process. delete delete

Images